CN112490184A - Multi-chip packaging method - Google Patents
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- CN112490184A CN112490184A CN202011344876.XA CN202011344876A CN112490184A CN 112490184 A CN112490184 A CN 112490184A CN 202011344876 A CN202011344876 A CN 202011344876A CN 112490184 A CN112490184 A CN 112490184A
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- 238000000034 method Methods 0.000 title claims abstract description 47
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 32
- 125000006850 spacer group Chemical group 0.000 claims abstract description 25
- 239000011159 matrix material Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims description 37
- 239000002313 adhesive film Substances 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 230000002441 reversible effect Effects 0.000 claims description 2
- 230000002829 reductive effect Effects 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 13
- 229910000679 solder Inorganic materials 0.000 description 10
- 238000010586 diagram Methods 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000012790 adhesive layer Substances 0.000 description 2
- 230000036961 partial effect Effects 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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Abstract
The application provides a multi-chip packaging method, which comprises the following steps: providing a first wafer, wherein the first wafer is provided with a plurality of main chips arranged in a matrix, the first wafer comprises a front surface and a back surface which are arranged in a back-to-back manner, the front surface of the main chip is the front surface of the first wafer, the back surface of the main chip is the back surface of the first wafer, and the front surface of the main chip is provided with a plurality of first bonding pads; arranging a spacer with a plurality of openings on the front surface of the first wafer, wherein each opening is correspondingly provided with a plurality of adjacent first bonding pads from adjacent main chips; arranging a bridge chip at each opening position, wherein the bridge chip is electrically connected with a plurality of first bonding pads in the openings; and cutting the first wafer to obtain a plurality of packaging bodies, wherein the packaging bodies comprise at least two main chips and at least one bridging chip which are electrically connected. By means of the mode, the alignment problem existing in the chip redistribution process can be solved, and the device cost required by alignment is reduced.
Description
Technical Field
The application belongs to the technical field of packaging, and particularly relates to a multi-chip packaging method.
Background
With the upgrading of electronic products, the functional requirements for the multi-chip package device are more and more, and the signal transmission between the chips in the multi-chip package device is more and more frequent. At present, an electrical interconnection structure is generally formed between a plurality of chips by using a silicon bridge or the like to realize signal transmission.
The conventional process for forming the above multi-chip package device mainly includes: firstly, cutting a wafer to obtain a single chip, then re-distributing a plurality of chips on a substrate, and then electrically connecting the silicon bridge with the plurality of chips at the corresponding positions. The redistribution process has high requirement on the alignment precision and high process cost.
Disclosure of Invention
The application provides a multi-chip packaging method, which aims to solve the alignment problem in the preparation process of a multi-chip packaging device.
In order to solve the technical problem, the application adopts a technical scheme that: provided is a multi-chip packaging method, including: providing a first wafer, wherein the first wafer is provided with a plurality of main chips arranged in a matrix, a non-through scribing groove is formed between every two adjacent main chips, the first wafer comprises a front surface and a back surface which are arranged in a reverse manner, the front surface of each main chip is the front surface of the first wafer, the back surface of each main chip is the back surface of the first wafer, and a plurality of first bonding pads are arranged on the front surface of each main chip; arranging a spacer with a plurality of openings on the front surface of the first wafer, wherein each opening is correspondingly provided with a plurality of adjacent first bonding pads from the adjacent main chips; providing a bridge chip at each of the opening locations, the bridge chip being electrically connected to the plurality of first pads within the opening such that adjacent main chips are electrically connected through the bridge chip; and cutting the first wafer to obtain a plurality of packaging bodies, wherein the packaging bodies comprise at least two main chips and at least one bridge chip which are electrically connected.
Wherein the spacer is a semiconductor substrate provided with a plurality of conductive through holes, and the step of providing the spacer having a plurality of openings on the front surface of the first wafer includes: and enabling part of the conductive through holes to correspond to part of the first bonding pads at the corresponding positions of the conductive through holes one by one and electrically connected with the first bonding pads.
Wherein, after the step of cutting the first wafer, the method further comprises: and forming a rewiring layer at a position of the semiconductor substrate, which is far away from the main chip, wherein the rewiring layer is electrically connected with the conductive through hole.
Wherein, the semiconductor substrate deviates from the side of the main chip and protrudes/flushes relative to the side of the bridge chip deviating from the main chip, and after the step of cutting the first wafer, the method further comprises the following steps: the bridge chip in the packaging body faces to a packaging substrate with a flat surface; electrically connecting the conductive via to the package substrate.
Wherein, the bridge chip is deviated from the main chip one side and protrudes from the semiconductor substrate one side deviated from the main chip, after the step of cutting the first wafer, the method further comprises: the bridge chip in the package body faces to a package substrate with a groove on the surface, and at least part of the bridge chip is located in the groove; electrically connecting the conductive via to the package substrate.
Wherein, after the step of disposing a bridge chip at each of the opening positions, the method further comprises: and arranging underfill between the bridge chip and the first wafer.
Wherein the area of the opening is larger than the area of the bridge chip, and after the step of disposing underfill between the bridge chip and the first wafer, the method further comprises: and forming a plastic packaging layer in the area of the opening which is not filled by the underfill and the bridge chip.
Wherein, before the step of providing the spacer with a plurality of openings on the front surface of the first wafer, the method further comprises the following steps: and forming a metal bump on each first bonding pad.
Wherein the step of cutting the first wafer comprises: attaching one side of the bridging chip, which is far away from the first wafer, to a first carrier plate by using a removable first adhesive film; grinding the back surface of the first wafer to reduce the thickness of the first wafer; cutting along at least a portion of the scribe line.
Wherein, before the step of disposing a bridge chip at each of the opening positions, the method further comprises: providing a second wafer, wherein a plurality of bridging chips which are arranged in a matrix manner are arranged on the second wafer; the front surface of the bridge chip is the front surface of the second wafer, the back surface of the bridge chip is the back surface of the second wafer, and a plurality of second bonding pads are arranged on the front surface of the bridge chip; attaching the front surface of the second wafer to a second carrier plate by using a removable second adhesive film; grinding the back surface of the second wafer to reduce the thickness of the second wafer; and cutting the second wafer to obtain single bridge chips.
Being different from the prior art situation, the beneficial effect of this application is: according to the multi-chip packaging method, the bridge chip is arranged on the front surface of the first wafer before the first wafer is cut, so that a chip redistribution process before the bridge chip is arranged in the prior art is omitted, the alignment problem in the chip redistribution process is solved, and the device cost required by alignment is reduced; in addition, the mode of electrically connecting two adjacent main chips by using the bridging chip reduces the alignment difficulty and improves the yield of the whole multi-chip packaging device compared with the silicon bridge mode in the prior art; in addition, a spacer with an opening is arranged before the bridge chip is arranged, then the bridge chip is arranged at the opening, and the spacer in the design mode can also play a certain limiting role on the bridge chip so as to reduce the alignment difficulty.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:
FIG. 1 is a schematic flow chart diagram illustrating an embodiment of a multi-chip packaging method according to the present application;
FIG. 2a is a schematic cross-sectional view of an embodiment corresponding to step S101 in FIG. 1;
FIG. 2b is a schematic cross-sectional view of an embodiment corresponding to step S102 in FIG. 1;
FIG. 2c is a schematic cross-sectional view of an embodiment corresponding to step S103 in FIG. 1;
FIG. 2d is a schematic cross-sectional view of an embodiment corresponding to step S104 in FIG. 1;
FIG. 3 is a schematic top view of one embodiment of the first wafer of FIG. 2 a;
FIG. 4a is a schematic cross-sectional view of an embodiment of a second wafer;
FIG. 4b is a schematic structural diagram of another embodiment corresponding to step S103 in FIG. 1;
FIG. 5 is a schematic cross-sectional view of an embodiment corresponding to step S104;
FIG. 6 is a schematic diagram of a multi-chip package device according to an embodiment after step S104 in FIG. 1;
FIG. 7 is a schematic diagram of another embodiment of a multi-chip package device after step S104 in FIG. 1;
fig. 8 is a schematic structural diagram of another embodiment of the multi-chip package after step S104 in fig. 1.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic flow chart of an embodiment of a multi-chip packaging method according to the present application, the multi-chip packaging method specifically includes:
s101: a first wafer 10 is provided, the first wafer 10 is provided with a plurality of main chips 100 arranged in a matrix, non-through scribe grooves 108 (as shown in fig. 3) are provided between adjacent main chips 100, the first wafer 10 includes a front surface 102 and a back surface 104 which are oppositely arranged, the front surface of the main chip 100 is the front surface 102 of the first wafer 10, the back surface of the main chip 100 is the back surface 104 of the first wafer 10, and the front surface of the main chip 100 is provided with a plurality of first pads 106.
Specifically, referring to fig. 2a and fig. 3, fig. 2a is a schematic cross-sectional view of an embodiment corresponding to step S101 in fig. 1, and fig. 3 is a schematic top view of the first wafer in fig. 2 a. The types of the master chips 100 on the first wafer 10 may be the same or different, and may be set according to actual requirements. For example, adjacent main chips a and B in the dashed line box in fig. 3 may be a group, and may be cut and retained in the same package, and the types of the main chips a and B in the group may be different, that is, the main chips a and B in the group may be heterogeneous chips. In addition, the number of adjacent main chips divided into a group may be 2, 3, 4, and the like, and may be specifically set according to requirements.
S102: spacers 105 having a plurality of openings 1050 are disposed on the front side 102 of the first wafer 10, wherein each opening 1050 is correspondingly disposed with an adjacent plurality of first pads 106 from an adjacent main chip 100.
Specifically, referring to fig. 2b, fig. 2b is a schematic cross-sectional view of an embodiment corresponding to step S102 in fig. 1. The spacer 105 may be a semiconductor substrate provided with a plurality of conductive through holes 1052 (e.g., conductive through silicon vias, etc.) in advance, and the step S102 specifically includes: the partial conductive through holes 1052 are in one-to-one correspondence and electrically connected with the partial first pads 106 at the corresponding positions thereof. In the present embodiment, the conductive via 1052 and the first pad 106 at the corresponding position may be electrically connected by using solder ball/solder or the like.
In addition, before the step S102, a metal bump may be formed on each first pad 106, and the material of the metal bump may be gold, copper, or the like; the process of forming the metal bump may specifically be: forming a first photoresist layer on the front surface 102 of the first wafer 10, wherein a first opening is formed in a position of the first photoresist layer corresponding to the first pad 106; forming a metal bump in the first opening by electroplating; the first photoresist layer is removed. Further, the step S102 specifically includes: the conductive through-hole 1052 is electrically connected to the metal bump at the corresponding position by solder/solder ball, so as to electrically connect to the first pad 106 at the corresponding position.
Of course, in other embodiments, the spacer 105 introduced in step S102 may also be an insulating substrate without the conductive through-holes 1052, and when the spacer 105 is disposed on the front surface 102 of the first wafer 10 and electrical connection with other components is required, a through-hole may be formed in the spacer 105 by laser or the like, and then a conductive layer may be formed in the through-hole to form the conductive through-hole.
S103: a bridge chip 103 is disposed at each opening 1050 position, and the bridge chip 103 is electrically connected with the plurality of first pads 106 within the opening 1050, so that the adjacent main chips 100 are electrically connected through the bridge chip 103.
Specifically, referring to fig. 2c, fig. 2c is a schematic cross-sectional view of an embodiment corresponding to step S103 in fig. 1. The bridge chip 103 may include a front surface (not labeled) and a back surface (not labeled) opposite to each other, the front surface of the bridge chip 103 may face the first wafer 10, and the second pads 1030 on the front surface of the bridge chip 103 may be electrically connected to the first pads 106 at corresponding positions by solder balls/solders, etc.
In one embodiment, before the step S103, a plurality of split bridge chips 103 may be provided in advance; in the step S103, the single bridge chip 103 may be respectively adsorbed to the corresponding positions by an adsorbing device. In order to reduce the thickness of the subsequent whole package, the step S103 further includes: A. providing a second wafer 20, wherein a plurality of bridge chips 103 arranged in a matrix are arranged on the second wafer 20, the front surface of each bridge chip 103 is the front surface 200 of the second wafer 20, the back surface of each bridge chip 103 is the back surface 202 of the second wafer 20, and a plurality of second bonding pads 1030 are arranged on the front surface of each bridge chip 103; specifically, as shown in fig. 4a, fig. 4a is a schematic cross-sectional view of an embodiment of the second wafer. The top view of the second disc 20 is similar to the top view of the first disc 10. B. The front side 200 of the second wafer 20 is attached to the second carrier sheet by a removable second adhesive film. C. The back side 202 of the second wafer 20 is ground to reduce the thickness of the second wafer 20. D. The second wafer 20 is cut to obtain individual bridge chips 103.
In another embodiment, when the height of the spacer 105 is less than the thickness of the bridge chips 103, that is, the height of the opening 1050 is less than the thickness of the bridge chips 103, before the step S103, the second wafer 20 containing a plurality of bridge chips 103 may also be provided in advance, as follows: A. providing a second wafer 20, wherein a plurality of bridge chips 103 arranged in a matrix are arranged on the second wafer 20; B. the front surface 200 of the second wafer 20 is attached to a second carrier by a removable second adhesive film (e.g., a double-sided adhesive tape, etc.), as shown in fig. 4 a. B. The back side 202 of the second wafer 20 is ground to reduce the thickness of the second wafer 20. Preferably, in this embodiment, before the step a, the method further includes: cutting off a part of the second wafer 20 at the scribing grooves 204 of the second wafer 20; the step B is specifically as follows: the back side 202 of the second wafer 20 is ground until the scribe lines 204 are exposed. The design mode can make the adjacent bridge chips 103 on the second wafer 20 disconnected; and due to the action of the second adhesive film, although the adjacent bridge chips 103 are disconnected, the position relationship between the adjacent bridge chips 103 is fixed. C. The back side 202 of the second wafer 20 is attached to a third carrier sheet by a third removable adhesive film. D. And removing the second adhesive film and the second carrier plate disposed on the front surface 200 of the second wafer 20. Accordingly, please refer to fig. 4b, wherein fig. 4b is a schematic structural diagram of another embodiment corresponding to step S103 in fig. 1. In the above step S103, the side of the spacer 105 facing away from the first wafer 10 is lower than the side of the bridge chip 103 facing away from the first wafer 10, or the side of the spacer 105 facing away from the first wafer 10 is flush with the side of the bridge chip 103 facing away from the first wafer 10. In the above design, the back surfaces of the multiple individual bridge chips 103 are fixedly disposed on the third carrier 40 by using a removable third adhesive film (not shown), and the multiple bridge chips 103 can be positioned by one positioning process, so as to further reduce the complexity of the positioning process.
In addition, in order to fix the position of the bridge chip 103 and protect the electrical connection structure between the bridge chip 103 and the main chip 100, after the step S103, the method may further include: an underfill is disposed between the bridge chip 103 and the first wafer 10, and the underfill may further fill the scribe line 108 under the bridge chip 103. Further, when the area of the opening 1050 projected forward on the first wafer 10 is larger than the area of the bridge chip 103 projected forward on the first wafer 10, after the step of disposing an underfill between the bridge chip 103 and the first wafer 10, the method may further include: a molding layer is formed in the region where the opening 1050 is not filled with the underfill and the bridge chip 103.
S104: the first wafer 10 is cut to obtain a plurality of packages 30, wherein the packages 30 comprise at least two main chips 100 and at least one bridge chip 103 electrically connected.
Specifically, the package 30 obtained after the dicing may include two main chips 100 and one bridge chip 103, and the package 30 may also include four main chips 100 and four bridge chips 103, and the number and arrangement manner of the main chips 100 in the package 30 may be set according to actual requirements; and the types of packages 30 obtained by cutting from the same first wafer 10 may be the same or different.
When the structure in step S103 is as shown in fig. 2c, please refer to fig. 2c and fig. 2d together, and fig. 2d is a schematic cross-sectional view of an embodiment corresponding to step S104 in fig. 1. In this embodiment, a cutter may be used to cut along the scribe line 108 in fig. 2c, and the center line of the cutter may be aligned with the center line of the scribe line 108 (as shown by the dotted line in fig. 2 c), and the structure of the obtained package 30 is shown in fig. 2 d. In this embodiment, the width of the cutter may be equal to or slightly greater than the width of the scribe line 108 as shown in fig. 2d to cut all of the first wafer 10 and the spacer 105 at the scribe line 108; in other embodiments, the width of the cutter may be smaller than the width of the scribing groove 108, and a step portion may remain on the outer side surface of the main chip 100 in the package 30.
When the structure in step S103 is as shown in fig. 4b, in order to reduce the resistance in cutting, before step S104 above, the method may further include: the third adhesive film and the third carrier 40 are removed.
In order to reduce the thickness of the entire package 30, the thickness of the first wafer 10 may be reduced so that the thickness of the main chip 100 is reduced when the step S104 is performed. Specifically, the step S104 includes: attaching the side of the bridge chip 103, which is far away from the first wafer 10, to the first carrier plate by using a removable first adhesive film; grinding the back surface of the first wafer 10 to reduce the thickness of the first wafer 10; the dicing is performed along at least a portion of the dicing channels 108.
In some cases, before the step S102, the method may further include: the first wafer 10 is cut to remove the portion of the first wafer 10 at the scribe line 108 to deepen the scribe line 108, and it is noted that the scribe line 108 does not penetrate the entire first wafer 10. When the adjacent main chips 100 are different types of chips, i.e. heterogeneous chips, after removing the portion of the first wafer 10 at the position of the scribe line 108, an insulating layer may be formed in the deepened scribe line 108, and the depth of the insulating layer may be the same as the depth of the deepened scribe line 108. The step of grinding the back surface of the first wafer 10 to reduce the thickness of the first wafer 10 may be: the back side 104 of the first wafer 10 may be ground until the scribe line 108 is exposed; at this time, although the adjacent main chips 100 on the first wafer 10 are disconnected from each other, the relative positional relationship between the main chips 100 does not change due to the first adhesive film. And when the types of the adjacent main chips 100 are different, namely, the main chips belong to heterogeneous chips, the design mode can reduce the signal interference between the adjacent main chips 100.
Correspondingly, please refer to fig. 5, wherein fig. 5 is a schematic cross-sectional view of an embodiment corresponding to step S104. The difference between the package 30a and the package 30 in fig. 2d is that a disconnected spacing region is disposed between adjacent main chips 100 in the package 30a, and an insulating layer 101 is disposed in the spacing region.
In addition, referring to fig. 2d again, the package 30 obtained through the steps S101 to S104 may include at least two main chips 100 and at least one bridge chip 103, each main chip 100 in the package 30 includes a first region 1000 and a second region 1002, all the first regions 1000 are adjacently disposed, and the first pads 106 on the adjacent first regions 1000 are electrically connected to the bridge chip 103; the first pads 106 on the second region 1002 are electrically connected to the conductive vias 1052 in the spacers 105. After obtaining the package 30, the package 30 may be electrically connected to a component such as a package substrate.
For example, referring to fig. 6, fig. 6 is a schematic structural diagram of an embodiment of a multi-chip package device after step S104 in fig. 1. The method may further include, after the step S104: the bridge chip 103 in the package 30 (not labeled in fig. 6) is faced to the package substrate 50 with a flat surface, and the conductive vias 1052 on the spacers 105 (i.e., semiconductor substrate) are electrically connected to the package substrate 50. Specifically, the package substrate 50 is provided with connection pads (not shown) corresponding to the positions of the conductive vias 1052, and the conductive vias 1052 may be electrically connected to the connection pads through solder/solder balls or the like. In order to stabilize the relative position between the package 30 and the package substrate 50, an adhesive layer may be disposed between the bridge chip 103 and the package substrate 50.
In addition, the package substrate 50 may further be electrically connected to other components (e.g., a circuit board); the conductive traces in the package substrate 50 may now extend from the connection pad locations to the side of the package substrate 50 facing away from the main chip 100.
For another example, referring to fig. 7, fig. 7 is a schematic structural diagram of another embodiment of the multi-chip package device after step S104 in fig. 1. The method may further include, after the step S104: a rewiring layer 51 is formed at a position of the spacer 105 (i.e., the semiconductor substrate) away from the main chip 100, and the rewiring layer 51 is electrically connected to the conductive via 1052. Preferably, in the present embodiment, the bridge chip 103 and the spacer 105 are flush with each other on the side facing away from the main chip 100.
For another example, referring to fig. 8, fig. 8 is a schematic structural diagram of another embodiment of the multi-chip package after step S104 in fig. 1. When the bridge chip 103 protrudes from the side of the main chip 100 away from the spacer 105 (i.e. the semiconductor substrate) away from the main chip 100, the step S104 further includes: A. facing the bridge chip 103 in the package 30 (not labeled in fig. 8) to the package substrate 52 having a groove (not labeled) on the surface thereof, and positioning at least a portion of the bridge chip 103 in the groove; the bridge chip 103 has a first projection area on the package substrate 50, the groove 500 has a second projection area on the package substrate 50, and the first projection area is smaller than the second projection area; B. electrically connecting the conductive vias 1052 with the package substrate 52; the package substrate 52 is provided with a connection pad (not shown) corresponding to the conductive via 1052, and the conductive via 1052 may be electrically connected to the connection pad through an electrical conductor such as solder/solder ball. In order to stabilize the relative position of the package 30 and the package substrate 52, an adhesive layer may be disposed between the bridge chip 103 and the bottom of the groove.
In summary, in the multi-chip packaging method provided by the present application, the bridge chip is disposed on the front surface of the first wafer before the first wafer is cut, so as to omit a chip redistribution process before the bridge chip is disposed in the prior art, thereby solving the alignment problem existing in the chip redistribution process and reducing the device cost required for alignment; in addition, the mode of electrically connecting two adjacent main chips by using the bridging chip reduces the alignment difficulty and improves the yield of the whole multi-chip packaging device compared with the mode of a silicon bridge in the prior art.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings, or which are directly or indirectly applied to other related technical fields, are intended to be included within the scope of the present application.
Claims (10)
1. A multi-chip packaging method, comprising:
providing a first wafer, wherein the first wafer is provided with a plurality of main chips arranged in a matrix, a non-through scribing groove is formed between every two adjacent main chips, the first wafer comprises a front surface and a back surface which are arranged in a reverse manner, the front surface of each main chip is the front surface of the first wafer, the back surface of each main chip is the back surface of the first wafer, and a plurality of first bonding pads are arranged on the front surface of each main chip;
arranging a spacer with a plurality of openings on the front surface of the first wafer, wherein each opening is correspondingly provided with a plurality of adjacent first bonding pads from the adjacent main chips;
providing a bridge chip at each of the opening locations, the bridge chip being electrically connected to the plurality of first pads within the opening such that adjacent main chips are electrically connected through the bridge chip;
and cutting the first wafer to obtain a plurality of packaging bodies, wherein the packaging bodies comprise at least two main chips and at least one bridge chip which are electrically connected.
2. The method of claim 1, wherein the spacer is a semiconductor substrate provided with a plurality of conductive vias, and the step of providing the spacer with a plurality of openings on the front surface of the first wafer comprises:
and enabling part of the conductive through holes to correspond to part of the first bonding pads at the corresponding positions of the conductive through holes one by one and electrically connected with the first bonding pads.
3. The method of claim 2, wherein the step of dicing the first wafer is followed by the steps of:
and forming a rewiring layer at a position of the semiconductor substrate, which is far away from the main chip, wherein the rewiring layer is electrically connected with the conductive through hole.
4. The multi-chip packaging method of claim 2, wherein a side of the semiconductor substrate facing away from the main chip protrudes/is flush with a side of the bridge chip facing away from the main chip, and wherein the step of cutting the first wafer further comprises:
the bridge chip in the packaging body faces to a packaging substrate with a flat surface;
electrically connecting the conductive via to the package substrate.
5. The multi-chip packaging method of claim 2, wherein the side of the bridge chip facing away from the main chip protrudes beyond the side of the semiconductor substrate facing away from the main chip, and wherein the step of cutting the first wafer further comprises:
the bridge chip in the package body faces to a package substrate with a groove on the surface, and at least part of the bridge chip is located in the groove;
electrically connecting the conductive via to the package substrate.
6. The multi-chip packaging method of claim 1, wherein after the step of disposing a bridge chip at each of the opening locations, further comprising:
and arranging underfill between the bridge chip and the first wafer.
7. The method of claim 6, wherein an area of the opening in an orthographic projection of the opening on the first wafer is larger than an area of the bridge chip in an orthographic projection of the bridge chip on the first wafer, and wherein the step of disposing an underfill between the bridge chip and the first wafer further comprises:
and forming a plastic packaging layer in the area of the opening which is not filled by the underfill and the bridge chip.
8. The method of claim 1, wherein the step of providing a spacer having a plurality of openings on the front side of the first wafer is preceded by the step of:
and forming a metal bump on each first bonding pad.
9. The method of claim 1, wherein the step of dicing the first wafer comprises:
attaching one side of the bridging chip, which is far away from the first wafer, to a first carrier plate by using a removable first adhesive film;
grinding the back surface of the first wafer to reduce the thickness of the first wafer;
cutting along at least a portion of the scribe line.
10. The multi-chip packaging method of claim 1, wherein the step of disposing a bridge chip at each of the opening locations is preceded by:
providing a second wafer, wherein a plurality of bridging chips which are arranged in a matrix manner are arranged on the second wafer; the front surface of the bridge chip is the front surface of the second wafer, the back surface of the bridge chip is the back surface of the second wafer, and a plurality of second bonding pads are arranged on the front surface of the bridge chip;
attaching the front surface of the second wafer to a second carrier plate by using a removable second adhesive film;
grinding the back surface of the second wafer to reduce the thickness of the second wafer;
and cutting the second wafer to obtain single bridge chips.
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