CN112466358A - Magnetic tunnel junction memory - Google Patents
Magnetic tunnel junction memory Download PDFInfo
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- CN112466358A CN112466358A CN202011371252.7A CN202011371252A CN112466358A CN 112466358 A CN112466358 A CN 112466358A CN 202011371252 A CN202011371252 A CN 202011371252A CN 112466358 A CN112466358 A CN 112466358A
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- 230000005291 magnetic effect Effects 0.000 title claims abstract description 38
- 230000015654 memory Effects 0.000 title claims abstract description 25
- 230000005294 ferromagnetic effect Effects 0.000 claims description 8
- 239000011229 interlayer Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 description 9
- 239000010410 layer Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000005034 decoration Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004774 atomic orbital Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000005610 quantum mechanics Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
- H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Mram Or Spin Memory Techniques (AREA)
- Hall/Mr Elements (AREA)
Abstract
The invention provides a magnetic tunnel junction memory, comprising: the writing control transistor and the reading control transistor are longitudinally stacked and arranged oppositely, and the source electrode of the writing control transistor is opposite to the source electrode of the reading control transistor; the drain of the write control transistor is electrically connected through a first end of a magnetic tunnel junction; the drain of the read control transistor is electrically connected to the second end of the magnetic tunnel junction through a bit line.
Description
Technical Field
The invention relates to the field of semiconductor memories, in particular to a magnetic tunnel junction memory.
Background
In recent years, MRAM using Magnetic Tunnel Junction (MTJ) is considered as a future solid-state nonvolatile memory, which has features of high speed read and write, large capacity, and low power consumption.
Patents US 10008662B 2 and US 2017/0117027 a1 disclose different logic methods for fabricating a magnetic random access memory, but the methods are limited to the current-controlled triode structure, and the unit area of MRAM is estimated to be larger than 40F2. F refers to the minimum feature size of the memory cell in the photolithography process. Patent US 9583615B2 discloses a method for fabricating a vertical transistor and interconnect structure, but is not limited to the structure connection and fabrication method, and such a transistor structure is not the best choice for the wiring of logic or non-NAND memory (including RRAM, MRAM, PCM, etc.).
Disclosure of Invention
The invention aims to provide a magnetic tunnel junction memory, which can reduce the area of the memory and improve the integration level.
In order to solve the above problems, the present invention provides a magnetic tunnel junction memory including: the writing control transistor and the reading control transistor are longitudinally stacked and arranged oppositely, and the source electrode of the writing control transistor is opposite to the source electrode of the reading control transistor; the drain of the write control transistor is electrically connected through a first end of a magnetic tunnel junction; the drain of the read control transistor is electrically connected to the second end of the magnetic tunnel junction through a bit line.
The invention optimizes the stacking of the two transistors, reduces the whole area of the circuit by stacking the two transistors, and can reduce the area of each digit of the memory to 4F2Left and right. F refers to the minimum feature size of the memory cell in the photolithography process.
Drawings
Fig. 1 is a schematic structural diagram of a magnetic tunnel junction memory according to this embodiment.
Detailed Description
The following describes in detail a specific embodiment of the magnetic tunnel junction memory according to the present invention with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a magnetic tunnel junction memory according to this embodiment. Each cell includes a write control transistor T1 and a read control transistor T2 stacked vertically in a top-to-top arrangement, the write control transistor T1 being in the top and source up and the read control transistor T2 being in the bottom and source down.
The writing control transistor and the reading control transistor respectively comprise a source electrode S +/-, a drain electrode D +/-, and a vertical channel between the source electrode and the drain electrode, and a grid electrode G +/-is arranged around the vertical channel. The drain electrode of the writing control transistor is electrically connected with the first end of the Magnetic Tunnel Junction (MTJ); the drain of the read control transistor is electrically connected to the second end of the magnetic tunnel junction MTJ through a bit line BL. The first end of the magnetic tunnel junction comprises a first ferromagnetic plate 01 and the second end comprises a second ferromagnetic plate 02. The magnetic tunnel junction MTJ also includes an insulating interlayer 03 between the first ferromagnetic plate 01 and the second ferromagnetic plate 02. The thickness of the insulating interlayer 03 is about 0.1nm to 2.0 nm.
In the resistance characteristics of the magnetic tunnel junction MTJ, when a specific external electrical signal is applied, the resistance changes due to the characteristics of the material itself, thereby playing a role in storing information. As the volume of the magnetic memory layer is reduced, the smaller the spin-polarized current that needs to be injected for a write or switch operation. Therefore, this writing method can achieve both device miniaturization and current reduction. In the prior art, the current (about 50 muA), the power consumption, the writing speed (about 10ns) and the unit area (about 50F) are written2) These characteristics are somewhat different from the ideal figures. The basic reason for this is that the Spin current-carrying carrier in the STT (Spin Transfer Torque) flip mechanism is an electron, which is light in weight and contains only 1/1840 of protons. It is known from the most basic physics that the force or torque is proportional to the mass, so even though the current can carry spin current to generate torque to the magnetic moment, the efficiency is not too high. Since the switching efficiency is low, the writing speed is slow, the current is large, and the power consumption is also large. Also, because a larger current is supplied, a larger CMOS is required and larger than the MTJ, which becomes a bottleneck in scaling. In quantum mechanics, the spin can interact with the angular momentum of the atomic orbital region, but the source of this force or torque is the nucleus. The larger the atomic order, the greater the spin-orbit interaction; in some special substances, such as topological insulators (topologic insulators), the surface also has an exceptionally large spin-orbit interaction. The Spin Orbit Torque (SOT) effect is used to flip the magnetic moment of the free layer in the MTJ, which is the SOT MRAM described above. There are two problems with the SOT architecture, the first is that the SOT MRAM is a 3-terminal component, the main reason being that the SOT MRAM reads from and writes from, and therefore requires additional terminals. This is troublesome in design and increases the cell area. The second problem is that the flipping mechanism of spin orbit torque can only flip the magnetic moment of the free layer to be perpendicular to the original direction, and the final stable direction can be adjusted and specified by a method. The most conceivable and obvious way isThe magnetic field is applied but this is the least desirable thing for the person designing the assembly. It is essential to create an asymmetry in the structure of the assembly that allows the direction in which the magnetic moment reverses after flipping to be controlled. The technical scheme solves the first problem by utilizing the vertical structure, creates asymmetry on the component structure, enables the direction of the reversed magnetic moment to be controlled and solves the second problem.
In the operation of the magnetic tunnel junction memory, the write control transistor T1 or the read control transistor T2 is gated by software to enter an operating state. When the write control transistor T1 enters a working state, the flip state of the Magnetic Tunnel Junction (MTJ) can be operated through an external level, so that the purpose of storing data is achieved; on the contrary, when the read control transistor T2 enters the operating state, the word line BL can output a high level or a low level according to the flip state of the magnetic tunnel junction MTJ, thereby achieving the purpose of reading data.
The technical scheme optimizes the stacking of the two transistors, and the stacking of the two transistors is related, so that the whole area of the circuit is reduced, and the area of each digit of the memory can be reduced to 4F2Left and right. F refers to the minimum feature size of the memory cell in the photolithography process.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (5)
1. A magnetic tunnel junction memory, comprising:
the writing control transistor and the reading control transistor are longitudinally stacked and arranged oppositely, and the source electrode of the writing control transistor is opposite to the source electrode of the reading control transistor;
the drain of the write control transistor is electrically connected with a first end of a magnetic tunnel junction;
the drain of the read control transistor is electrically connected to the second end of the magnetic tunnel junction through a bit line.
2. The magnetic tunnel junction memory of claim 1 wherein the first end of the magnetic tunnel junction comprises a first ferromagnetic plate and the second end comprises a second ferromagnetic plate.
3. The magnetic tunnel junction memory of claim 2 further comprising an insulating interlayer between the first ferromagnetic plate and the second ferromagnetic plate.
4. The magnetic tunnel junction memory of claim 3 wherein the insulating interlayer has a thickness of about 0.1nm to about 2.0 nm.
5. The magnetic tunnel junction memory of claim 1 wherein the write control transistor and the read control transistor each comprise a source, a drain, and a vertical channel between the source and the drain, the gate being disposed around the vertical channel.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011371252.7A CN112466358A (en) | 2020-11-30 | 2020-11-30 | Magnetic tunnel junction memory |
| PCT/CN2020/135746 WO2022110326A1 (en) | 2020-11-30 | 2020-12-11 | Magnetic tunnel junction memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011371252.7A CN112466358A (en) | 2020-11-30 | 2020-11-30 | Magnetic tunnel junction memory |
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| CN112466358A true CN112466358A (en) | 2021-03-09 |
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| CN202011371252.7A Pending CN112466358A (en) | 2020-11-30 | 2020-11-30 | Magnetic tunnel junction memory |
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| CN (1) | CN112466358A (en) |
| WO (1) | WO2022110326A1 (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120086065A1 (en) * | 2010-10-08 | 2012-04-12 | Samsung Electronics Co., Ltd. | Semiconductor device with vertical channel transistor and method of fabricating the same |
| CN103811045A (en) * | 2014-02-28 | 2014-05-21 | 北京航空航天大学 | Double-function storage unit with high reliability and multi-bit storage |
| US20160300612A1 (en) * | 2013-12-24 | 2016-10-13 | Sasikanth Manipatruni | Hybrid memory and mtj based mram bit-cell and array |
| CN106875969A (en) * | 2015-12-14 | 2017-06-20 | 株式会社东芝 | Magnetic memory |
| CN107689416A (en) * | 2016-08-04 | 2018-02-13 | 株式会社东芝 | Magnetic memory |
| US20190311956A1 (en) * | 2018-01-08 | 2019-10-10 | Spin Memory, Inc. | Methods of Fabricating Dual Threshold Voltage Devices |
| US20200202914A1 (en) * | 2018-12-20 | 2020-06-25 | Imec Vzw | Spin orbit torque magnetoresistive random access memory device |
| US20200212226A1 (en) * | 2019-01-02 | 2020-07-02 | International Business Machines Corporation | Area-efficient inverter using stacked vertical transistors |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106558333B (en) * | 2015-09-29 | 2018-11-09 | 中国科学院物理研究所 | Spin transfer torque MAGNETIC RANDOM ACCESS MEMORY including annular magnet tunnel knot |
| CN110890115A (en) * | 2018-09-07 | 2020-03-17 | 上海磁宇信息科技有限公司 | Spin orbit torque magnetic memory |
| CN111640769B (en) * | 2019-03-01 | 2023-04-18 | 中电海康集团有限公司 | Spin-orbit torque magnetic memory unit and magnetic memory |
| CN111863061A (en) * | 2020-07-21 | 2020-10-30 | 上海磁宇信息科技有限公司 | Magnetic random access memory and data read/write operation method thereof |
-
2020
- 2020-11-30 CN CN202011371252.7A patent/CN112466358A/en active Pending
- 2020-12-11 WO PCT/CN2020/135746 patent/WO2022110326A1/en active Application Filing
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120086065A1 (en) * | 2010-10-08 | 2012-04-12 | Samsung Electronics Co., Ltd. | Semiconductor device with vertical channel transistor and method of fabricating the same |
| US20160300612A1 (en) * | 2013-12-24 | 2016-10-13 | Sasikanth Manipatruni | Hybrid memory and mtj based mram bit-cell and array |
| CN103811045A (en) * | 2014-02-28 | 2014-05-21 | 北京航空航天大学 | Double-function storage unit with high reliability and multi-bit storage |
| CN106875969A (en) * | 2015-12-14 | 2017-06-20 | 株式会社东芝 | Magnetic memory |
| CN107689416A (en) * | 2016-08-04 | 2018-02-13 | 株式会社东芝 | Magnetic memory |
| US20190311956A1 (en) * | 2018-01-08 | 2019-10-10 | Spin Memory, Inc. | Methods of Fabricating Dual Threshold Voltage Devices |
| US20200202914A1 (en) * | 2018-12-20 | 2020-06-25 | Imec Vzw | Spin orbit torque magnetoresistive random access memory device |
| US20200212226A1 (en) * | 2019-01-02 | 2020-07-02 | International Business Machines Corporation | Area-efficient inverter using stacked vertical transistors |
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| Publication number | Publication date |
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| WO2022110326A1 (en) | 2022-06-02 |
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