CN112383384A - Large-size chip based on-chip serial data communication and communication method thereof - Google Patents

Large-size chip based on-chip serial data communication and communication method thereof Download PDF

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CN112383384A
CN112383384A CN202110041282.XA CN202110041282A CN112383384A CN 112383384 A CN112383384 A CN 112383384A CN 202110041282 A CN202110041282 A CN 202110041282A CN 112383384 A CN112383384 A CN 112383384A
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serial data
data
chip
serial
channel
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CN112383384B (en
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吴霜毅
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Mingkesi Shanghai Microelectronics Technology Co ltd
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Chengdu Mecs Microelectronics Technology Co ltd
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/0001Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0006Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format
    • H04L1/0007Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format by modifying the frame length
    • H04L1/0008Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format by modifying the frame length by supplementing frame payload, e.g. with padding bits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/06Notations for structuring of protocol data, e.g. abstract syntax notation one [ASN.1]

Abstract

The invention discloses a large-size chip based on-chip serial data communication and a communication method, wherein S channel groups are arranged on the large-size chip, and a data conversion channel, a serializer, a serial data encoder, a serial data receiving transponder and a serial data interface circuit which are connected in sequence are arranged in each channel group; a data clock feedback module which adopts a logic control mode to connect the serial data receiving repeaters in any more than two channel groups is also arranged on the large-size chip; on-chip communication is realized on the large-size chip, a plurality of parallel data groups on the large-size chip can be connected in series through a ring-shaped serial interface containing a token, and the serial connection of local data is completed at each channel grouping position; the high-speed and stable output of the serial data can be finished without solving the clock synchronization problem among all data packets.

Description

Large-size chip based on-chip serial data communication and communication method thereof
Technical Field
The invention relates to the field of integrated circuit technology and the like, in particular to a large-size chip based on-chip serial data communication and a communication method thereof.
Background
Data acquisition integrated circuits typically have multiple channels, each of which can acquire data. For example, the multi-channel analog-to-digital converter chip collects and converts multiple analog signals, and the converted digital codes need to be transmitted to a subsequent digital processing module through a digital interface.
Generally, when the data bit width is m and the number of channels is n, the number of parallel interfaces required is m × n. The high-performance CMOS integrated circuit technology is beneficial to converting data from parallel data into serial data, namely a parallel data group with data bit width of m and clock rate of f can be converted into a serial data group with data bit width of 1 and clock rate of m f. Thus, although the clock rate is increased by m times, the parallel data is converted into serial data, and the number of data interfaces is reduced to 1. For modern high performance CMOS integrated circuits, the highest clock rates can typically reach the level of 10 GHz. This means that when m x f <10GHz, parallel data on the chip can be output in serial mode. For example, when the conversion rate of the single-channel ADC of the chip is 1GHz and the bit width of the data is 10 bits, the data can be transmitted from the ADC chip to the post-stage data processing module DSP through a data interface of 10 GbpS.
For a multi-channel ADC, it may be considered that each channel converts parallel data into serial data through a serial mode and outputs the serial data, or may output the data of each channel through one serial data interface channel after integrating the data of each channel. For an ADC with n channels, m single-channel data bits wide, and f single-channel clock rate, the unified serial data interface channel data rate is n × m × f.
For example, for a 100-channel ADC, the data bit width of each channel is 10 bits, and the data rate of each channel is 1MHz, so that the total data can be output through a serial data interface channel with a data rate of 100 × 10 × 1MHz =1Gbps after integration. The channel data may also be grouped, for example, output through 2 groups of serial data interfaces, each group outputting data of 50 channels, and the data rate of each serial data channel is 50 × 10 × 1MHz =500 MHz.
In a conventional chip, data output is generally performed in the above-described mode.
In order to realize data integration, in the chip design technology, a data group needs to be converted from parallel data to serial data. This process is called parallel-to-serial conversion and the circuit on which it is based is a serializer circuit. For a multi-channel ADC, one serializer is required for each channel. In order to ensure that the data of multiple channels are not scrambled when being serialized, each serializer adopts the same clock frequency and synchronization mechanism. Generally, the on-chip clock frequency is not very high, and the chip size is not large, so that the parallel signal transmission delay does not exceed the clock period. Therefore, the data of each channel can be output to a module in parallel, and the data integration and parallel-serial conversion can be completed through a serializer in the module.
Such as the 100 channel ADC example described above, the data rate for a single channel is 1MHz with a clock period of 1 us. The transmission delay of the parallel data on the chip can not exceed 1 us. The parallel channel data sheet can be transmitted to a serializer on a chip to complete parallel-serial conversion.
As the manufacturing technology capabilities of existing chips continue to increase. The data channels of a single chip continue to increase, as do the chip sizes. Similar to CMOS image sensor chips, the number of data conversion channels is often more than 1024, and the size of the chip is more than tens of millimeters, even some chips reach the order of 100 millimeters. These dimensions have been much larger than the dimensions of conventional chips.
The increase in chip size has a significant impact on chip functionality. On the one hand, the increased chip area allows more switching channels to be added; on the other hand, the increased chip area results in parallel data needing to go through a more distant path before parallel-to-serial conversion to complete the integration.
For example, a CMOS image sensor usually employs a column ADC array, and the number of column ADCs reaches more than 1000, and may reach 8000 channels. Assuming that each channel is only 10um wide, 8000 channels will reach a width of 80 mm.
At this time, if data (assumed to be 12 bits) of each channel needs to be transferred to one serializer, two data transfer difficulties are faced.
One is that the transmission distance is too long. The serializer can only enable the data transmission distance of the far end to be the shortest at the center point of the chip. But even then the transmission distance of the data at the far end reaches a distance of 40 mm. Such a distance is unacceptable for on-chip data.
The other is that the input parallel data of the serializer reaches 8000 x 12 lines, and the excessive number of the lines can cause the serializer to be too large to finish accurate time sequence operation.
On the other hand, even if 8000 channels are split into multiple groups of channels to complete serialization respectively, synchronization problems are faced. Because the channels are grouped, each group integrates a respective independent serializer. Then, clock synchronization issues may be encountered between the multiple serializers. According to the channel distribution, if the number of the channels is divided into 8 groups, each group is 1000 channels, and one serializer is shared, the distance between adjacent serializers is up to 10mm, and the clock transmission distance between adjacent serializers is up to 10 mm. The data clock is transmitted for a long distance, so that the clock delay is caused, and the synchronization error of each serializer can also be caused.
Disclosure of Invention
The invention aims to provide a large-size chip based on-chip serial data communication and a communication method thereof, wherein the large-size chip based on-chip serial data communication can serially connect a plurality of parallel data groups on the large-size chip through a ring-shaped serial interface containing tokens, and the serial connection of local data is completed at each channel grouping position; when the communication method is used for data transmission, the problem of clock synchronization among all data packets does not need to be solved, and high-speed and stable output of serial data can be completed.
The invention is realized by the following technical scheme: a large-size chip based on serial data communication on a chip is provided with S channel groups, wherein S is a natural number which is not 0, each channel group is internally provided with a data conversion channel, a serializer, a serial data encoder, a serial data receiving transponder and a serial data interface circuit, the data conversion channel is connected with the serial data encoder through the serializer, the serial data encoder is connected with the serial data receiving transponder, and the serial data receiving transponder is connected with the serial data interface circuit; a data clock feedback module which adopts a logic control mode to connect the serial data receiving repeaters in any more than two channel groups is also arranged on the large-size chip; the serial data receiving repeaters in two adjacent channel packets are connected with each other, and the serial data output and the serial clock output of one serial data receiving repeater are used as the serial data input and the serial clock input of the other serial data interface circuit.
Further, in order to better implement the large-sized chip based on serial data communication on chip of the present invention, the following setting modes are particularly adopted: when two adjacent channel packets operate, the serial data receiving transponder serial clock output of one channel packet is also used as the serial clock input of the serializer of the other channel packet.
Further, in order to better implement the large-sized chip based on serial data communication on chip of the present invention, the following setting modes are particularly adopted: the data conversion channel is provided with n ADCs, the n ADCs convert input analog signals into m-bit-wide parallel data, and n is a natural number different from 0.
Further, in order to better implement the large-sized chip based on serial data communication on chip of the present invention, the following setting modes are particularly adopted: and the serializer carries out serial processing on the parallel data output by the data conversion channel to form a serial data stream with the data width of 1 bit and the data rate of m × n.
Further, in order to better implement the large-sized chip based on serial data communication on chip of the present invention, the following setting modes are particularly adopted: the serial data encoder is used for verifying the serial data output by the serializer and adding a verification code; the serial data encoder may also scramble the serial data.
Further, in order to better implement the large-sized chip based on serial data communication on chip of the present invention, the following setting modes are particularly adopted: the serial data receiving repeater is used for receiving serial data and a serial clock transmitted to the current channel packet by the previous channel packet, and adding the coded serial data of the current channel packet on the basis of the serial data and the serial clock to form cross-channel packet serial data increased group by group; when the current channel packet is selected as a chip data output port, forwarding the cross-channel packet serial data to a serial data interface circuit; when the current lane packet is not selected as a chip data output port, the cross-lane packet serial data is forwarded to a serial data receive repeater in the next lane packet.
Because a plurality of channel groups are added in the chip, when actual data integration is carried out, a starting point and an end point of the data need to be defined, and the accuracy of a large amount of data also needs to be ensured by adding data verification; to better implement the invention:
the total serial data structure of the chip comprises a frame head consisting of frame head data, frame data and a frame tail consisting of frame tail data which are sequentially arranged; the frame data comprises packet address bits, packet data and check data which are sequentially arranged, and the check data of the previous channel packet is connected with the packet address bits of the next channel packet.
Further, in order to better implement the large-sized chip based on serial data communication on chip of the present invention, the following setting modes are particularly adopted: the serial data interface circuit is used as an interface circuit for outputting final serial data formed by processing parallel data input by a plurality of channels in a chip in a grouping manner to the outside of the chip, so that the data output function of the chip is completed; serial data interface circuitry can cover data rates of several Gbps to hundreds of Gbps.
Further, in order to better implement the large-sized chip based on serial data communication on chip of the present invention, the following setting modes are particularly adopted: and the data clock feedback module connects the S channel packet with the 1 st channel packet, so that a full-chip feedback path of serial data and a serial clock is formed. The addition of this module enables the system (chip) to select any one of the lane packets as the start packet and its previous packet as the end packet.
A large-size chip communication method based on-chip serial data communication is realized by adopting the large-size chip based on-chip serial data communication, and comprises the following steps:
1) confirming the address of the 1 st channel packet according to the code written by SPI (short for Serial Peripheral Interface);
2) according to the frame length written in by the SPI, a local serial data encoder of the 1 st channel group encodes parallel data, and adds frame head and frame tail data to form complete frame data;
3) the 1 st channel group serially outputs data to the 2 nd channel group;
4) after the 2 nd channel group receives data, replacing the initial data of the current channel group with the received data according to the address written in by the SPI;
5) the serial data encoder of the current channel packet judges whether the current channel packet is the last channel packet according to the address written in by the SPI, if not, step 5.1) is executed, and if yes, step 5.2) is executed;
5.1) if the serial data encoder of the current channel packet judges that the current channel packet is not the last channel packet, serially outputting the data to the next channel packet, and repeating the operations from the step 2) to the step 5) by the next channel packet;
5.2) if the serial data encoder of the current channel packet judges that the current channel packet is the last channel packet, outputting the final serial data formed by the current channel packet to an output driving stage which is corresponding to the current channel packet and consists of a serial data receiving transponder and a serial data interface circuit,
the output driving stage outputs the final serial data to the outside of the chip.
Compared with the prior art, the invention has the following advantages and beneficial effects:
(1) when the invention is applied, the parallel data of each sub-channel (ADC) does not need to be transmitted through a long data line.
(2) The invention connects each channel packet through a ring-type serial data interface (serial data interface circuit) containing tokens, so that the clock required by each channel packet is from the previous channel packet, thereby avoiding the clock synchronization among each data packet.
(3) The invention can arbitrarily select the initial grouping through the annular serial data interface (serial data interface circuit), thereby improving the flexibility of the data interface.
Drawings
FIG. 1 is a schematic structural diagram of the present invention.
FIG. 2 is a general serial data structure diagram of the chip of the present invention.
The device comprises a 101-channel packet, a 102-data clock feedback module, a 201-data conversion channel, a 202-serializer, a 203-serial data encoder, a 204-serial data receiving repeater and a 205-serial data interface circuit, wherein the 101-channel packet is divided into a plurality of channels; m in fig. 1 refers to bit width of parallel data output by the ADC, and a slash line at m indicates that the ADC outputs the parallel data.
Detailed Description
The present invention will be described in further detail with reference to examples, but the embodiments of the present invention are not limited thereto.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings of the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
Example 1:
the invention designs a large-size chip based on serial data communication on a chip, which can connect a plurality of parallel data groups on the large-size chip in series through a ring-shaped serial interface containing tokens, and complete the serial of local data at each channel grouping position, as shown in figure 1, and particularly adopts the following setting mode: on a large-size chip, S channel packets 101 are arranged, wherein S is a natural number different from 0, each channel packet 101 is internally provided with a data conversion channel 201, a serializer 202, a serial data encoder 203, a serial data receiving repeater 204 and a serial data interface circuit 205, the data conversion channel 201 is connected to the serial data encoder 203 through the serializer 202, the serial data encoder 203 is connected to the serial data receiving repeater 204, and the serial data receiving repeater 204 is connected to the serial data interface circuit 205; and a data clock feedback module 102 which adopts a logic control mode to connect with the serial data receiving and forwarding devices 204 in any more than two channel groups 101 is also arranged on the large-size chip.
When setting up, the serial data receiving repeaters 204 in two adjacent channel packets 101 are connected with each other, and the serial data output and the serial clock output of one serial data receiving repeater 204 are used as the serial data input and the serial clock input of the other serial data receiving repeater 204, that is, after the data transmission sequence of the channel packet 101 is determined, the serial data output and the serial clock output of the serial data receiving repeater 204 in the 1 st channel packet 101 will be used as the serial data input and the serial clock input of the serial data receiving repeater 204 in the 2 nd channel packet 101, and the serial clock output of the serial data receiving repeater 204 in the 1 st channel packet 101 will also be used as the serial clock input of the serializer 202 of the 2 nd channel packet 101, and so on for the following channel packets 101.
Example 2:
the present embodiment is further optimized based on the above embodiment, as shown in fig. 1, the same parts as those in the foregoing technical solution will not be described again, and in order to further better implement the large-size chip based on serial data communication on chip according to the present invention, the following setting manner is particularly adopted: the data conversion channel 201 is provided with n ADCs, and the n ADCs convert an input analog signal into m-bit-wide parallel data, where n is a natural number different from 0.
The channel grouping 101 is a subset of local channels in a large-sized chip (multi-channel chip). The number of the channels is limited, and the circuit is convenient to integrate and work. The chip requires that the number of channels in each channel group is consistent and is n channels; the full chip has S lane groups.
Further, in order to better implement the large-sized chip based on serial data communication on chip of the present invention, the following setting modes are particularly adopted: the serializer 202 serially processes the n sets of parallel data output from the data conversion channel 201 to form a serial data stream with a data width of 1 bit and a data rate of m × n.
Further, in order to better implement the large-sized chip based on serial data communication on chip of the present invention, the following setting modes are particularly adopted: the serial data encoder 203 is used for verifying the serial data output by the serializer 202 and adding a verification code; the serial data encoder may also scramble the serial data.
Further, in order to better implement the large-sized chip based on serial data communication on chip of the present invention, the following setting modes are particularly adopted: the serial data receiving repeater 204 is configured to receive serial data and a serial clock transmitted from a previous lane packet 101 to the current lane packet 101, add encoded serial data of the current lane packet 101 based on the serial data and the serial clock, and form group-by-group increased cross-lane packet serial data; when the current lane packet 101 is selected as the chip data output port, the cross-lane packet serial data is forwarded to the serial data interface circuit 205; when the current lane packet 101 is not selected as a chip data output port, the cross lane packet serial data is forwarded to the serial data receive repeater 204 in the next lane packet 101.
Because a plurality of channel groups 101 are added in the chip, when actual data integration is performed, a starting point and an end point of the data need to be defined, and the accuracy of a large amount of data also needs to be ensured by adding data verification; to better implement the present invention, as shown in fig. 2, the total serial data structure of the chip includes a frame header comprising frame header data, a frame data, and a frame trailer comprising frame trailer data, which are sequentially arranged; the frame data includes packet address bits, packet data, and check data that are sequentially set, and the check data of the previous lane packet 101 is connected to the packet address bits of the next lane packet 101.
Further, in order to better implement the large-sized chip based on serial data communication on chip of the present invention, the following setting modes are particularly adopted: the serial data interface circuit 205 is used as an interface circuit for outputting final serial data, which is formed by processing parallel data input by a plurality of channel packets 101 in the chip, to the outside of the chip, thereby completing a chip data output function; serial data interface circuitry can cover data rates of several Gbps to hundreds of Gbps.
Further, in order to better implement the large-sized chip based on serial data communication on chip of the present invention, the following setting modes are particularly adopted: the data clock feedback module 102 connects the S-th lane packet 101 with the 1 st lane packet 101, thereby forming a full chip feedback path for serial data and serial clocks. The addition of this module enables the system (chip) to select any one of the lane packets 101 as the start packet and its previous packet as the end packet.
Example 3:
the present embodiment is further optimized based on any of the above embodiments, and with reference to fig. 1 and fig. 2, a large-size chip communication method based on-chip serial data communication is implemented by using the large-size chip based on-chip serial data communication, and includes the following steps:
1) confirming the address of the 1 st channel packet 101 according to the code written by the SPI;
2) according to the frame length written in by the SPI, a local serial data encoder 203 of the 1 st channel group 101 encodes parallel data, and adds frame head and frame tail data to form complete frame data;
3) the 1 st lane packet 101 serially outputs data to the 2 nd lane packet 101;
4) after the 2 nd channel group 101 receives data, replacing the initial data of the current channel group 101 with the received data according to the address written in by the SPI;
5) the serial data encoder 203 of the current channel packet 101 judges whether the current channel packet 101 is the last channel packet 101 according to the address written by the SPI, if not, step 5.1) is executed, and if yes, step 5.2) is executed;
5.1) if the serial data encoder 203 of the current channel packet 101 judges that the current channel packet 101 is not the last channel packet 101, serially outputting data to the next channel packet 101;
5.2) if the serial data encoder 203 of the current channel packet 101 judges that the current channel packet 101 is the last channel packet 101, outputting the final serial data formed by the current channel packet 101 to an output driving stage corresponding to the current channel packet 101 and consisting of a serial data receiving repeater 204 and a serial data interface circuit 205, and outputting the final serial data out of the chip by the output driving stage.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way, and all simple modifications and equivalent variations of the above embodiments according to the technical spirit of the present invention are included in the scope of the present invention.

Claims (10)

1. A large-sized chip based on-chip serial data communication, on which chip S lane packets (101) are provided, characterized in that: a data conversion channel (201), a serializer (202), a serial data encoder (203), a serial data receiving repeater (204) and a serial data interface circuit (205) are arranged in each channel packet (101), the data conversion channel (201) is connected to the serial data encoder (203) through the serializer (202), the serial data encoder (203) is connected with the serial data receiving repeater (204), and the serial data receiving repeater (204) is connected with the serial data interface circuit (205); and the large-size chip is also provided with a data clock feedback module (102) which adopts a logic control mode to connect with a serial data receiving transponder (204) in any more than two channel groups (101).
2. The large-size chip based on serial data communication on chip of claim 1, wherein: the serial data receiving repeaters (204) in two adjacent channel packets (101) are connected with each other, and the serial data output and the serial clock output of one serial data receiving repeater (204) are used as the serial data input and the serial clock input of the other serial data receiving repeater (204).
3. The large-size chip based on serial data communication on chip of claim 1, wherein: when two adjacent channel packets (101) operate, the serial clock output of the serial data receiving repeater (204) of one channel packet (101) is also used as the serial clock input of the serializer (202) of the other channel packet (101).
4. The large-size chip based on serial data communication on chip of claim 1, wherein: the data conversion channel (201) is provided with n ADCs, and the n ADCs convert input analog signals into m-bit-wide parallel data.
5. The large-size chip based on serial data communication on chip of claim 4, wherein: the serializer (202) performs serial processing on the parallel data output by the data conversion channel (201) to form a serial data stream with a data width of 1 bit and a data rate of m x n times.
6. A large-size chip based on serial data communication on chip according to any one of claims 1 to 5, characterized in that: the serial data encoder (203) is used for verifying the serial data output by the serializer (202) and adding a verification code.
7. A large-size chip based on serial data communication on chip according to any one of claims 1 to 5, characterized in that: the serial data receiving repeater (204) is used for receiving serial data and a serial clock transmitted to the current channel packet (101) by the previous channel packet (101), and adding the coded serial data of the current channel packet (101) on the basis of the serial data and the serial clock to form cross-channel packet serial data which is increased group by group; forwarding cross lane packet serial data to a serial data interface circuit (205) when a current lane packet (101) is selected as a chip data output port; when the current lane packet (101) is not selected as a chip data output port, the cross-lane packet serial data is forwarded to a serial data receive repeater (204) in the next lane packet (101).
8. A large-size chip based on serial data communication on chip according to any one of claims 1 to 5, characterized in that: the serial data interface circuit (205) is used as an interface circuit for outputting final serial data, which is formed by processing parallel data input by a plurality of channel groups (101) in the chip, to the outside of the chip.
9. A large-size chip based on serial data communication on chip according to any one of claims 1 to 5, characterized in that: the data clock feedback module (102) connects the S-th channel packet (101) with the 1 st channel packet (101), so that a full-chip feedback path of serial data and a serial clock is formed.
10. A large-size chip communication method based on serial data communication on chip, which is implemented by the large-size chip based on serial data communication on chip according to any one of claims 1 to 9, and is characterized in that: the method comprises the following steps:
1) confirming the address of the 1 st channel packet (101) according to the encoding written by the SPI;
2) according to the frame length written in by the SPI, a local serial data encoder (203) of a 1 st channel group (101) encodes parallel data, and adds frame head and frame tail data to form complete frame data;
3) the 1 st channel group (101) serially outputs data to the 2 nd channel group (101);
4) after the 2 nd channel group (101) receives data, replacing the initial data of the current channel group (101) with the received data according to the address written in by the SPI;
5) the serial data encoder (203) of the current channel packet (101) judges whether the current channel packet (101) is the last channel packet (101) according to the address written by the SPI;
5.1) if the serial data encoder (203) of the current channel packet (101) judges that the current channel packet (101) is not the last channel packet (101), serially outputting data to the next channel packet (101), and repeating the operations from the step 2) to the step 5) by the next channel packet (101);
5.2) if the serial data encoder (203) of the current channel packet (101) judges that the current channel packet (101) is the last channel packet (101), outputting the final serial data formed by the current channel packet (101) to an output driving stage which is corresponding to the current channel packet (101) and is composed of a serial data receiving transponder (204) and a serial data interface circuit (205), and outputting the final serial data out of the chip by the output driving stage.
CN202110041282.XA 2021-01-13 2021-01-13 Large-size chip based on-chip serial data communication and communication method thereof Active CN112383384B (en)

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