CN112234044A - Electronic package, conductive substrate thereof and manufacturing method thereof - Google Patents
Electronic package, conductive substrate thereof and manufacturing method thereof Download PDFInfo
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- CN112234044A CN112234044A CN201910783748.6A CN201910783748A CN112234044A CN 112234044 A CN112234044 A CN 112234044A CN 201910783748 A CN201910783748 A CN 201910783748A CN 112234044 A CN112234044 A CN 112234044A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/811—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector the bump connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/81101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector the bump connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a bump connector, e.g. provided in an insulating plate member
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
The invention relates to an electronic package, a conductive substrate and a manufacturing method thereof, which comprises a plurality of exposed conductive elements arranged in an insulating film, wherein in the packaging process, a semiconductor chip and a packaging substrate are respectively arranged on two opposite surfaces of the insulating film, so that the semiconductor chip can be electrically connected with the packaging substrate through the conductive elements to complete the packaging process, and a soldering tin bump is not required to be formed on the semiconductor chip, therefore, a machine for planting the soldering tin bump is not required to be adopted, and the cost for manufacturing the electronic package is effectively reduced.
Description
Technical Field
The present invention relates to semiconductor packaging technology, and more particularly, to an electronic package, a conductive substrate thereof, and a method for fabricating the same.
Background
With the development of electronic industry, the electronic products tend to be designed in a direction of light, thin, short, and diversified functions, and the semiconductor packaging technology develops different packaging types accordingly. In order to meet the requirements of high Integration and Miniaturization of semiconductor devices, the routing density of semiconductor devices is enhanced mainly by Flip chip (Flip chip) in addition to the conventional Wire bonding (Wire bonding) semiconductor packaging technology.
Fig. 1A to fig. 1B are schematic cross-sectional views illustrating a manufacturing method of a conventional flip chip package structure 1. As shown in fig. 1A, a semiconductor chip 11 is first bonded to an electrical contact pad 100 of a package substrate 10 via a plurality of solder bumps 13, and then the solder bumps 13 are reflowed. Next, as shown in fig. 1B, an underfill 14 is formed between the semiconductor chip 11 and the package substrate 10 to cover the solder bumps 13.
An oxide layer is usually formed on the outer surface of the solder bump 13 before bonding the solder bump 13 to the electrical contact pad 100, so that during the reflow of the solder bump 13, a flux (not shown) is used to remove the oxide layer.
However, in the conventional method for manufacturing the flip chip package 1, the plurality of solder bumps 13 need to be formed on the semiconductor chip 11 (or the package substrate 10), and the machine for implanting the plurality of solder bumps 13 is expensive, so the cost of the conventional method is difficult to be reduced.
In addition, since flux is used, a portion of the flux remains on the package structure 1 during the reflow process, and a coarse solder gap is generated, so that the joint between the solder bump 13 and the electrical contact pad 100 fails, resulting in poor reliability of the package structure 1.
In addition, if the diameter of the solder bump 13 is extremely small, there is a problem that the solder bump 13 is not completely adhered to a part of the solder bump 13 when the flux is adhered to the solder bump.
Therefore, how to overcome the above problems of the prior art has become a problem to be overcome in the industry.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention provides an electronic package, a conductive substrate thereof and a method for fabricating the same, which can effectively reduce the cost of fabricating the electronic package.
The conductive substrate of the present invention comprises: an insulating film having first and second surfaces opposite to each other; and a plurality of conductive elements disposed in the insulating film and exposed to the first surface and the second surface of the insulating film.
In the conductive substrate, the insulating film has a plurality of openings for disposing the conductive elements.
The invention also provides a preparation method of the conductive substrate, which comprises the following steps: providing an insulating film with a plurality of openings; and disposing a conductive element in the opening.
In the foregoing conductive substrate and the method for manufacturing the same, a solder assistant material is formed in the opening, so that the solder assistant material covers the conductive element, and the surface of the conductive element is covered with the solder assistant material.
In the foregoing conductive substrate and the method for fabricating the same, the conductive element is a solder structure, a metal pillar or a conductive block.
In the above-mentioned conductive substrate and the method for manufacturing the same, a support is disposed in the insulating film. For example, the material forming the supporting member is a conductive material. Alternatively, the support is of the same construction as the conductive element.
The present invention also provides an electronic package comprising: a conductive substrate as described above; a carrier structure disposed on the second surface of the insulating film; and the electronic element is arranged on the first surface of the insulating film, so that the electronic element is electrically connected with the bearing structure through the conductive element.
In view of the above, the electronic package, the conductive substrate and the manufacturing method thereof of the present invention mainly use the design of disposing the conductive element in the opening of the insulating film to form the conductive substrate, so that when the electronic component is bonded to the carrying structure, the electronic component and the carrying structure are only required to be disposed on the first surface and the second surface of the insulating film, respectively, so as to enable the electronic component to be electrically connected to the carrying structure via the conductive element, thereby completing the packaging process.
In addition, the welding aid material is arranged in the opening, so that the opening limits the arrangement range of the welding aid material, the welding aid material cannot overflow out of a preset area, and the welding aid material and the conductive element can be fused in the opening after the conductive element is reflowed, so that compared with the prior art, the welding aid material can be prevented from remaining on the electronic packaging piece, a thick welding gap cannot be generated, the problem of joint failure of the conductive element can be avoided, and the purpose of improving the reliability of the electronic packaging piece is achieved.
In addition, when the maximum width of the conductive element is very small, the soldering assistant material and the conductive element are fused in the opening after the conductive element is reflowed, so that compared with the prior art, the problem that the conductive element is not adhered completely can be avoided.
Drawings
Fig. 1A to 1B are schematic cross-sectional views illustrating a manufacturing method of a conventional flip chip package structure.
Fig. 2A to fig. 2E are schematic cross-sectional views illustrating a method for manufacturing an electronic package according to the present invention.
Fig. 2E' and 2E "are cross-sectional views of different embodiments of fig. 2E.
Description of the reference numerals
1 Package Structure 10 Package substrate
100 electrical contact pads 11 semiconductor chip
13 solder bump 14 underfill
2 electronic package 2a,2b,2c conductive substrate
20 carrying structure 200 electrical contacts
21 electronic component 21a action surface
21b non-active surface 210 electrode pad
23,23 'conductive element 23' support
24 insulating film 24a first surface
24b second surface 240 opening
25 flux d width.
Detailed Description
The following description of the embodiments of the present invention is provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein.
It should be understood that the structures, proportions, and dimensions shown in the drawings and described herein are for illustrative purposes only and are not intended to limit the scope of the present invention, which is defined by the claims, but rather by the claims. In addition, the terms "first", "second", "upper" and "a" as used herein are for the sake of clarity only, and are not intended to limit the scope of the present invention, and changes or modifications of the relative relationship may be made without substantial technical changes.
Fig. 2A to fig. 2E are schematic cross-sectional views illustrating a method for manufacturing the electronic package 2 according to the present invention.
As shown in fig. 2A, an insulating film 24 having a plurality of openings 240 is provided, which has a first surface 24a and a second surface 24b opposite to each other, so that the openings 240 penetrate through the insulating film 24 to communicate the first surface 24a with the second surface 24 b.
In the present embodiment, the insulating film 24 is a tape or other adhesive, and the opening 240 is formed by laser, mechanical drill or other methods.
As shown in fig. 2B, a conductive element 23 is disposed in each of the openings 240.
In the present embodiment, the conductive elements 23 are, for example, solder bumps or solder balls, and the conductive elements 23 are placed in the openings 240 by, for example, vacuum suction.
As shown in fig. 2C, a solder assistant material 25 is formed in each of the openings 240, so that the solder assistant material 25 covers the conductive element 23, thereby forming a conductive substrate 2 a.
As shown in fig. 2D, an electronic device 21 and a carrying structure 20 having a plurality of electrical contacts 200 are provided.
In the embodiment, the carrier structure 20 is a package substrate (substrate) having a core layer and a circuit structure or a coreless (circuit) circuit structure, such as a package substrate, and a circuit layer, such as a fan-out (fan out) Redistribution (RDL) layer, is formed on a dielectric material. Specifically, the electrical contacts 200 are disposed on the die-disposing side of the carrying structure 20. It should be understood that the supporting structure 20 may also be other supporting units for supporting electronic devices such as chips, for example, a lead-frame (lead-frame) or a silicon interposer (silicon interposer), and is not limited thereto.
In addition, the electronic component 21 is an active component, such as a semiconductor chip, a passive component, such as a resistor, a capacitor, or an inductor, or a combination thereof. In this embodiment, the electronic component 21 is a semiconductor chip, and has an active surface 21a and a non-active surface 21b opposite to the active surface 21a, and the active surface 21a has a plurality of electrode pads 210.
As shown in fig. 2E, the electronic component 21 is adhered to the first surface 24a of the insulating film 24 by the active surface 21a thereof, and the carrier structure 20 is adhered to the second surface 24b of the insulating film 24, so that the electrode pads 210 and the electrical contacts 200 are both in contact with the conductive component 23, and the electronic component 21 is flip-chip bonded to the carrier structure 20 via the conductive substrate 2 a.
In the present embodiment, the conductive element 23 and the flux material 25 are reflowed such that the conductive element 23 protrudes from the first surface 24a and the second surface 24b of the insulating film 24, thereby facilitating the conductive element 23 to electrically connect the electrode pad 210 and the electrical contact 200.
In another embodiment, as shown in fig. 2E ', the conductive element 23' of the conductive substrate 2b is a metal pillar (e.g., a copper pillar) or other conductive block (e.g., a copper core ball, which is formed by a solder bump coated copper block), and the solder assistant 25 is not used. For example, a metal material is plated or deposited in the opening 240 to form a metal pillar, thereby forming the conductive element 23'; alternatively, a copper core ball is placed in each of the openings 240 by vacuum suction.
In addition, in other embodiments, as shown in fig. 2E ", the conductive substrate 2c may be provided with at least one supporting member 23" disposed in the insulating film 24 thereof, which supports the electronic component 21 and the carrying structure 20 in a contact manner without electrically connecting the electronic component 21 (or the electrode pad 210) and the carrying structure 20 (or the electrical contact 200). Specifically, the supporting member 23 ″ is a solder structure, a metal pillar or other conductive block, which is in a cold solder state during reflow operation, and the supporting member 23 ″ contacts the electronic component 21 and the supporting structure 20, so that the problems of air remaining in the insulating film 24, glue leakage, glue overflow, etc. can be avoided. For example, the support 23 "is fabricated with the conductive element 23, i.e., the support 23" is the same construction as the conductive element 23. It should be understood that the support 23 "and the conductive element 23 may also be of different configurations.
Therefore, the manufacturing method of the present invention only needs to arrange the electronic component 21 and the supporting structure 20 on the first surface 24a and the second surface 24b of the insulating film 24 respectively when the electronic component 21 is bonded to the supporting structure 20 through the design of the conductive substrates 2a,2b,2c, so that the electronic component 21 can be electrically connected to the supporting structure 20 through the conductive components 23, 23' to complete the packaging process, and thus the conventional solder bumps are not required to be formed on the electronic component 21 (or on the supporting structure 20), and compared with the prior art, the manufacturing method of the present invention does not need to purchase a machine for implanting solder bumps, thereby effectively reducing the cost for manufacturing the electronic package 2.
In addition, the flux material 25 is disposed in the opening 240, so that the opening 240 limits the range of the flux material 25, and the flux material 25 does not overflow out of the predetermined area, and thus after reflow soldering of the conductive element 23, the flux material 25 and the conductive element 23 are fused in the opening 240, so compared with the prior art, the manufacturing method of the present invention can avoid the flux material 25 remaining on the electronic package 2, and thus, no coarse soldering gap is generated, and further, the problem of bonding failure between the conductive element 23 and the electrical contact 200 (or the electrode pad 210) can be avoided, so as to achieve the purpose of improving the reliability of the electronic package 2.
In addition, when the maximum width d (the diameter shown in fig. 2B) of the conductive element 23 is small (e.g., less than 25 μm), after the conductive element 23 is reflowed, the flux material 25 and the conductive element 23 are fused in the opening 240, so that the conductive element 23 and the electrical contact 200 (or the electrode pad 210) are completely bonded together, and thus compared with the prior art, the manufacturing method of the present invention can avoid the problem of incomplete adhesion of the conductive element 23.
The present invention provides an electronic package 2, comprising: a conductive substrate 2a,2b,2c, a carrying structure 20 and an electronic component 21.
The conductive substrate 2a,2b,2c comprises: an insulating film 24 and a plurality of conductive elements 23,23 'disposed in the insulating film 24, wherein the insulating film 24 has a first surface 24a and a second surface 24b opposite to each other, so that the conductive elements 23, 23' are exposed from the first surface 24a and the second surface 24b of the insulating film 24.
The carrier structure 20 is disposed on the second surface 24b of the insulating film 24.
The electronic component 21 is disposed on the first surface 24a of the insulating film 24, such that the electronic component 21 is electrically connected to the supporting structure 20 through the conductive elements 23, 23'.
In one embodiment, the insulating film 24 has a plurality of openings 240 for disposing the conductive elements 23, 23'.
In one embodiment, the conductive element 23 is covered with solder 25.
In one embodiment, the conductive elements 23, 23' are solder structures, metal posts or conductive blocks.
In one embodiment, the conductive substrate 2c further comprises at least one support 23 ″ disposed in the insulating film 24. For example, the material forming the supporting member 23 ″ is a conductive material. Alternatively, the support 23 "is of the same construction as the conductive elements 23, 23'.
In summary, in the electronic package, the conductive substrate and the method for fabricating the electronic package of the present invention, the conductive element is disposed in the opening of the insulating film to form the conductive substrate, so that the problem of poor bonding between the conductive element and the electrical contact of the supporting structure or the electrode pad of the electronic element can be avoided.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify the above-described embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.
Claims (14)
1. An electrically conductive substrate, comprising:
an insulating film having first and second surfaces opposite to each other; and
and a plurality of conductive elements disposed in the insulating film and exposed to the first surface and the second surface of the insulating film.
2. The conductive substrate as set forth in claim 1, wherein the insulating film is provided with a plurality of openings for disposing the plurality of conductive elements.
3. The conductive substrate of claim 1, wherein the conductive element is coated with a solder-assist material.
4. The conductive substrate of claim 1, wherein the conductive element is a solder structure, a metal post, or a conductive block.
5. The conductive substrate of claim 1, further comprising a support disposed in the insulating film.
6. The conductive substrate as set forth in claim 5, wherein the material forming the support member is a conductive material.
7. The conductive substrate of claim 5, wherein the support member and the conductive element are of the same construction.
8. An electronic package, comprising:
the conductive substrate according to any one of claims 1 to 7;
a carrier structure disposed on the second surface of the insulating film; and
and the electronic element is arranged on the first surface of the insulating film, so that the electronic element is electrically connected with the bearing structure through the plurality of conductive elements.
9. A method of making a conductive substrate, comprising:
providing an insulating film with a plurality of openings; and
a conductive element is disposed in the opening.
10. The method as claimed in claim 9, further comprising forming a solder assistant material in the opening such that the solder assistant material covers the conductive element.
11. The method of claim 9, wherein the conductive element is a solder structure, a metal pillar, or a conductive block.
12. The method of claim 9, further comprising disposing a support in the insulating film.
13. The method of claim 12, wherein the supporting member is made of a conductive material.
14. The method of claim 12, wherein the supporting member and the conductive element are identical in structure.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW108124913A TWI760629B (en) | 2019-07-15 | 2019-07-15 | Electronic package and conductive substrate and manufacturing method thereof |
| TW108124913 | 2019-07-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112234044A true CN112234044A (en) | 2021-01-15 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910783748.6A Pending CN112234044A (en) | 2019-07-15 | 2019-08-23 | Electronic package, conductive substrate thereof and manufacturing method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN112234044A (en) |
| TW (1) | TWI760629B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115133374A (en) * | 2022-06-13 | 2022-09-30 | 番禺得意精密电子工业有限公司 | A method of making a conductive element |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1079404A (en) * | 1996-09-03 | 1998-03-24 | Ngk Spark Plug Co Ltd | Wiring board having solder bump and manufacturing method thereof |
| JPH1098128A (en) * | 1996-09-25 | 1998-04-14 | Toshiba Corp | Semiconductor package and semiconductor mounting part |
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| US10529698B2 (en) * | 2017-03-15 | 2020-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor packages and methods of forming same |
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| CN115133374B (en) * | 2022-06-13 | 2024-12-24 | 番禺得意精密电子工业有限公司 | Method for manufacturing a conductive element |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI760629B (en) | 2022-04-11 |
| TW202105622A (en) | 2021-02-01 |
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