CN112199323A - Power system relay protection SoC chip - Google Patents
Power system relay protection SoC chip Download PDFInfo
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- G06F15/76—Architectures of general purpose stored program computers
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- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
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- G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
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- G06F21/76—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
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Abstract
The application relates to a relay protection SoC chip of a power system, which comprises a main inner core, a slave inner core, a front end data processing module, an internal memory and a storage management module, wherein the main inner core and the front end data processing module are connected with the internal memory, the main inner core, the slave inner core and the front end data processing module are all connected with the storage management module, the storage management module is used for being connected with an external memory, and the front end data processing module is used for being in communication connection with an external device; the front-end data processing module receives analog quantity sampling data sent by an external device and sends the analog quantity sampling data to the internal memory, and the main kernel reads the analog quantity sampling data from the internal memory to perform logic operation; the main kernel, the slave kernel and the front-end data processing module are also connected through an external memory connected with the memory management module for data exchange.
Description
Technical Field
The application relates to the technical field of electric power, in particular to a relay protection SoC chip of an electric power system.
Background
The relay protection device is a common device in the power system, and the working state of the relay protection device directly affects the whole power system, and is responsible for important mission of protecting the safe and stable operation of the power system. Therefore, ensuring the high reliable operation of the relay protection device under various working conditions is a problem that must be considered in the design of the relay protection device.
Different functions of traditional power system relay protection device such as protection sampling, calculation, communication are responsible for by different integrated circuit boards, and the inside components and parts of device are many, and information transfer link is many, data interaction is inefficient to data reliability is low, in case intermediate link produces data processing deviation under complicated operation site work environment, will lead to the inside work of device unusual, influences power system's safety and stability.
Disclosure of Invention
In view of the above, it is necessary to provide a power system relay protection SoC chip capable of improving data reliability in order to solve the above technical problems.
A power system relay protection SoC chip comprises: the system comprises a main kernel, a slave kernel, a front-end data processing module, an internal memory and a storage management module, wherein the main kernel and the front-end data processing module are connected with the internal memory, the main kernel, the slave kernel and the front-end data processing module are all connected with the storage management module, the storage management module is used for connecting with an external memory, and the front-end data processing module is used for being in communication connection with an external device;
the front-end data processing module receives analog quantity sampling data sent by an external device and sends the analog quantity sampling data to the internal memory, and the main kernel reads the analog quantity sampling data from the internal memory to perform logic operation; and the main kernel, the slave kernel and the front-end data processing module exchange data through an external memory connected with the storage management module.
In one embodiment, the main kernel reads key data from the connected external read-only memory and stores the key data in the internal memory after starting.
In one embodiment, the front-end data processing module receives a message, performs exception identification on the received message, and sends exception information obtained through identification to the main kernel.
In one embodiment, the front-end data processing module identifies an abnormal message in an ethernet message sent by the external device; identifying messages which do not accord with preset standards in SV messages and GOOSE messages sent by the external device; and for the subscription message sent by the external device, checking and calculating when the transmission of the corresponding data packet is finished, and identifying the incomplete data packet according to the calculation result.
In one embodiment, the front-end data processing module further performs frame counter check and CRC check on the packet sent by the main core, and identifies a packet that fails to pass the check.
In one embodiment, the master core is connected with an external hardware watchdog, and the master core receives a reset level sent by the external hardware watchdog when the master core works abnormally to reset.
In one embodiment, the master core is internally provided with a timer interrupt function, the slave core updates a timing register of the slave core at regular time according to a preset period, and the timer interrupt function resets the slave core when the timing register of the slave core is not updated in the preset period.
In one embodiment, the front-end data processing module periodically updates a timing register of the front-end data processing module according to the preset period, and the timer interrupt function resets the front-end data processing module when the timing register of the front-end data processing module is not updated in the preset period.
In one embodiment, the task state variable corresponding to each task module in the main core is changed according to the execution times of the corresponding task module, and the timer interrupt function restarts the main core when the task state variable is not changed in the preset period.
In one embodiment, the master core operates in bare core mode.
The power system relay protection SoC chip adopts a dual-core architecture comprising a main core and a slave core, analog quantity sampling data are collected by a front end data processing module and then stored in an internal memory, the main core can be read from the internal memory for use, the main core and the slave core can also be connected with an external memory through a storage management module between the front end data processing module and the slave core, data exchange is carried out by accessing the external memory, and data sampling, calculation and interaction functions finished by a plurality of board cards of a traditional power system relay protection device are integrated in one chip through on-chip interaction between the dual-core and the front end data processing module, so that the data interaction efficiency between the modules is effectively improved, the information transmission link is reduced, the reliability of data management is improved, and the safety and stability of a power system are further improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an SoC chip for relay protection of a power system in one embodiment;
fig. 2 is a schematic structural diagram of a relay protection SoC chip of the power system in another embodiment;
fig. 3 is a schematic diagram illustrating software and hardware resetting conditions of a relay protection SoC chip of the power system in one embodiment.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Embodiments of the present application are set forth in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or be connected to the other element through intervening elements. Further, "connection" in the following embodiments is understood to mean "electrical connection", "communication connection", or the like, if there is a transfer of electrical signals or data between the connected objects.
As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising," "includes" or "including," etc., specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.
In one embodiment, referring to fig. 1, there is provided a power system relay protection SoC chip, including: the system comprises a main kernel 110, a slave kernel 120, a front-end data processing module 130, an internal memory 140 and a memory management module 150, wherein the main kernel 110 and the front-end data processing module 130 are connected with the internal memory 140, the main kernel 110, the slave kernel 120 and the front-end data processing module 130 are all connected with the memory management module 150, the memory management module 150 is used for connecting with an external memory 200, and the front-end data processing module 130 is used for being in communication connection with an external device.
The front-end data processing module 130 receives analog sampling data transmitted from an external device and transmits the analog sampling data to the internal memory 140, and the main core 110 reads the analog sampling data from the internal memory 140 and performs a logic operation. Specifically, the front-end data processing module 130 may receive a data packet sent by an external device through a network interface, process the data packet to obtain analog sampling data, and then directly store the analog sampling data in the internal memory 140, and the main core 110 obtains the analog sampling data from the internal memory 140 and performs a logic operation in the secondary cache, where the logic operation includes processing of the analog sampling data in the relay protection.
The master core 110, the slave core 120 and the front-end data processing module 130 also exchange data with each other through the external memory 200 connected to the memory management module 150. Specifically, the master kernel 110, the slave kernel 120 and the front-end data processing module 130 can read and write data from and in the external memory 200 through the storage management module 150, so that the master kernel 110, the slave kernel 120 and the front-end data processing module 130 can exchange data through the external memory 200. For example, data read from the internal memory 140 or data obtained through logical operations by the main core 110 may be sent to the external memory 200 through the storage management module 150, and data read from the external memory 200 by the core 120 or the front-end data processing module 130 may be read through the storage management module 150.
The SoC chip for relay protection of the power system adopts a dual-core architecture including a main core 110 and a slave core 120, analog quantity sampling data is collected by a front-end data processing module 130 and then stored in an internal memory 140, the main core 110 can be read from the internal memory 140 for use, and the master kernel 110, the slave kernel 120 and the front-end data processing module 130 may be connected with an external memory 200 through a memory management module 150, data exchange is carried out by accessing the external memory 200, and data sampling, calculation and interaction functions finished by a plurality of board cards of the traditional relay protection device of the power system are integrated on one chip by in-chip interaction between the dual cores and the front-end data processing module 130, so that the data interaction efficiency between the modules is effectively improved, information transmission links are reduced, the reliability of data management is improved, and the safety and stability of the power system are further improved.
The power system relay protection SoC chip manages the multi-core system in a one-master-multi-slave mode, wherein the master core 110 masters the highest authority, and the master core 120 and the front-end data processing module 130 are supervised and controlled. Wherein, the master core 110 and the slave core 120 may be hardware ARM cores; the front-end data processing module 130 may be an FPGA (Field Programmable Gate Array); the internal Memory 140 may be a RAM (Random Access Memory). The external memory 200 may be a DDR (Double Data Rate) memory. Specifically, the FPGA can process switching value input and output and analog sampling data.
Specifically, each link of data transmission in the SoC chip for relay protection of the power system is checked by CRC (Cyclic Redundancy Check). For example, master core 110 performs a CRC check on the read data. The data transmission process is carried out in the relay protection SoC chip of the power system, the physical safety is high, when the external temperature changes, the physical unit in the chip changes simultaneously, and the positive and negative deviation of the parameter is consistent, so that the data processing can not generate deviation.
Specifically, the front-end data processing module 130 and the master kernel 110 may exchange data through an AXI (Advanced eXtensible Interface) bus. The address space of the internal memory 140 is 256KB, the data bandwidth can reach 1Gbps by adopting a 16-bit bus mode. The data sampling rate of the relay protection device is generally 1200Hz, the sampling period is 833us, the time for completing functions such as FFT (fast Fourier transform) algorithm, protection logic calculation and the like in each sampling period is 100us, the reading time of analog quantity sampling data is 0.5us, and the operation processing performance is not influenced.
In one embodiment, the host core 110 reads critical data from the attached external read-only memory and stores the critical data in the internal memory 140 after booting.
The key data can comprise four types of data of protection fixed value, soft pressing plate data, protection starting and alarm mark. After the SoC chip for power system relay protection is powered on, the four types of data, i.e., the protection setting value, the soft pressing plate data, the protection start and the alarm flag, are loaded into the external rom, and the main core 110 reads the key data from the external rom and puts the protection setting value and the soft pressing plate data into the internal memory 140. By storing the critical data of the relay protection device during operation in the internal memory 140, the relay protection critical data can not be output from the chip.
For example, as shown in fig. 2, CORE1 represents the master CORE 110, COR2 represents the slave CORE 120, after the power system relay protection SoC chip is powered on, the program is automatically loaded into the external memory 200 (DDR in fig. 2), and then the master CORE 110 is started first, and the protection setting value and the soft pressing plate data are put into the internal memory 140 from the external read only memory (EEPROM in fig. 2); the analog sampling data is generated by an external device, specifically, an external merging unit, and is sent to the internal front-end data processing module 130 through a gigabit network interface; the front-end data processing module 130 directly stores the analog quantity sampling data obtained by processing into the internal memory 140 after message distribution, SV decoding, low-pass filtering and interpolation synchronization processing, and the main core 110 obtains the analog quantity sampling data from the internal memory 140 to perform logical operation in the secondary cache.
In one embodiment, the front-end data processing module 130 receives the message, performs exception identification on the received message, and sends the identified exception information to the main core 110.
The abnormal information is information generated according to the result of the abnormal recognition, and may include, for example, an abnormal message, an abnormal position of the abnormal message, and the like. By performing exception identification on the received message and sending exception information to the main kernel 110, the main kernel 110 can record data through the received exception information and analyze whether the exception of the whole data stream in each link meets the logical relationship, so that the location where the exception occurs can be accurately positioned; therefore, the main kernel 110 can manage and monitor the abnormal information of the data stream, and can timely find and analyze the abnormality of the processing process of the front-end data processing module 130, thereby avoiding the problems of incapability of monitoring the abnormality, delayed failure alarm, and the like caused by the black box operation of the front-end data processing module 130 and system breakdown caused thereby.
Specifically, the front-end data processing module 130 performs exception identification and statistics on the service flow at the entry and exit positions of each key processing module, and delivers the exception identification and statistics to the main kernel 110, and the main kernel 110 can identify a problem point and give an alarm message in time based on comparison of the exception information.
In one embodiment, the operation of the front-end data processing module for performing exception identification on the received message includes: identifying abnormal messages in Ethernet messages sent by an external device; identifying messages which do not accord with preset standards in SV messages and GOOSE messages sent by an external device; and for the subscription message sent by the external device, checking and calculating when the transmission of the corresponding data packet is finished, and identifying the incomplete data packet according to the calculation result.
Specifically, data frame analysis may be performed on the ethernet packet to determine whether the ethernet packet is abnormal. Wherein the preset specification refers to the 61850 specification; by detecting whether the SV message and the GOOSE message meet the preset specification, it can be determined whether the SV message and the GOOSE message are abnormal, such as an MAC (Media Access Control) Address is abnormal. Carrying out checksum calculation on the identified subscription message, wherein the checksum, namely checksum, identifies an incomplete data packet according to a calculation result; specifically, the subscription packet may be identified in a normal ethernet packet, an SV packet and a GOOSE packet that meet the specification, or may be identified in all received packets. By identifying the abnormality of the Ethernet message, SV message, GOOSE message and subscription message, the abnormality analysis can be performed on the message sent by the external device.
In one embodiment, the operation of the front-end data processing module for performing exception identification on the received message further includes: and performing frame counter check and CRC check on the message sent by the main kernel 110, and identifying the message which fails in the check.
The messages which fail to pass the check comprise messages which fail to pass the check of the frame counter and messages which fail to pass the check of the CRC. Furthermore, after the message which is not checked is identified, whether overflow errors occur in all levels of caches can be checked. The anomaly detection can be performed comprehensively by further identifying the message which fails to pass the verification in the message sent by the main core 110 on the basis of performing anomaly identification on the message sent by the external device.
In one embodiment, the master core 110 is connected to an external hardware watchdog (not shown), and the master core 110 receives a reset level sent by the external hardware watchdog when the master core 110 operates abnormally to reset. When the master core 110 is abnormal, the external hardware watchdog sends a reset level, and the master core 110 receives the reset level to reset.
Specifically, in hardware, an external hardware watchdog is connected to the main core 110, a reset period of the external hardware watchdog is 1.6 seconds (seconds), and when the main core 110 is abnormal, the external hardware watchdog may reset the main core 110 within 1.6 seconds, so that the main core 110 reloads the program. By monitoring the main core 110 for an exception using an external hardware watchdog, the main core 110 may be self-restored in an exception state.
In one embodiment, the master core 110 has a timer interrupt function built therein, the slave core 120 updates the timing register of the slave core 120 periodically according to a preset period, and the timer interrupt function resets the slave core 120 when the timing register of the slave core 120 is not updated in the preset period.
The preset period can be set according to actual needs. Specifically, the preset period may be 1 s; the slave core 120 regularly updates a timing register within a period of 1s, and the master core 110 monitors the state of the timing register of the slave core 120 through a timer interrupt function having the highest software priority, and controls the slave core 120 to be reset individually when the timing register is not refreshed within 1 s. By monitoring the slave kernel 120 by the master kernel 110, the master kernel 110 can control the slave kernel 120 to perform self-recovery in an abnormal state.
In one embodiment, the front-end data processing module 130 periodically updates the timing register of the front-end data processing module 130 according to a preset period, and the timer interrupt function resets the front-end data processing module 130 when the timing register of the front-end data processing module 130 is not updated in the preset period.
By monitoring the front-end data processing module 130 by the master kernel 110, the master kernel 110 can control the slave kernel 120 to perform self-recovery in an abnormal state.
In one embodiment, the task state variables corresponding to the task modules in the main kernel 110 are changed according to the execution times of the corresponding task modules, and the timer interrupt function restarts the main kernel 110 when the task state variables are not changed in a preset period.
Each task module corresponds to one task state variable, and if the task module is executed once, the task state variable is updated; for example, each time the protection algorithm module is executed, the corresponding task state variable is incremented by 1. Taking the preset period as 1s as an example, the timer interrupt function monitors each task module, the soft watchdog module monitors the task state variable in real time, when the task state variable does not change within 1s, the task state variable is regarded as a software fault, the main kernel 110 restarts the software, and such a safety mechanism ensures that all kernel tasks reliably run, and self-recovery from an abnormal state is realized through safety reset. Specifically, the slave core 120 may also monitor the status of each internal task module.
Referring to fig. 3, in particular, the external hardware watchdog may reset the reset level controlling master core 110 when the master core 110 is abnormally operated. The highest software priority timer interrupt function of the CORE1 is responsible for monitoring the CORE2 and FPGAs, as well as monitoring the task modules within the CORE 1. The CORE2 updates a timing register periodically within 1s period, the CORE1 can monitor the status of the timing register in real time, and when the timing register is not refreshed within 1s, the CORE1 resets the CORE2 alone and re-executes from the program entry. Similarly, the FPGA also has a timing register, and the timing register is refreshed periodically, when the CORE1 finds that the timing register is not updated, a reset logic signal is given to the FPGA, and all FPGA logic modules are reset or even reloaded. The soft watchdog module of the timer interrupt function monitors the task state variable of the task module inside the CORE1 in real time, and when the task state variable is not changed within 1s, it is considered as a software fault, and the main kernel 110 restarts the software.
In one embodiment, master core 110 operates in bare core mode. By adopting the main kernel 110 to run in the bare-core mode, the main kernel 110 has no operating system and runs fast.
Specifically, the main core 110 in the bare core mode is responsible for modules such as fixed value management, a sampling module, a protection algorithm, trip logic, and configuration management, and is also responsible for management of dual-core shared hardware resources and management of shared memory addresses for inter-core communication.
Specifically, the front-end data processing module 130 accesses the external memory 200 through the storage management module 150 via the ACP bus, and the front-end data processing module 130, the master kernel 110, and the slave kernel 120 can exchange data among the kernels through the external memory 200. The main kernel 110 allocates interactive memory addresses from the front-end data processing module 130 to the dual cores and the dual cores respectively, and the addresses between the front-end data processing module 130 and the dual cores are different according to application customization; 32MB space, a read area and a write area are allocated between the two cores, and each occupies half. Through unified management, the common fatal problems such as memory leakage can be avoided, and system breakdown is prevented.
The SoC chip for power system relay protection may include an AES-256 decryption engine and an HMAC (Hash-based Message Authentication Code) Authentication engine, and support a Secure Boot start mode, which may be executed by the slave core 120. The design software for protection includes binary executable code of the software, data, and the bitstream programming files of the front-end data processing module 130 are not stolen and used. After the software is designed, a 256-bit check code for authentication is added to the design, and then encryption is carried out by using a 256-bit secret key AES algorithm. The 256-bit key can be freely set, is stored in the front-end data processing module and cannot be read from the outside. At start-up, the BOOTROM code first decrypts the protected software via the AES-256 decryption engine, then authenticates integrity via the HMAC engine, and only authenticated software can be loaded and executed.
In the description herein, references to the description of "some embodiments," "other embodiments," "desired embodiments," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, a schematic description of the above terminology may not necessarily refer to the same embodiment or example.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. The utility model provides a power system relay protection SoC chip which characterized in that includes: the system comprises a main kernel, a slave kernel, a front-end data processing module, an internal memory and a storage management module, wherein the main kernel and the front-end data processing module are connected with the internal memory, the main kernel, the slave kernel and the front-end data processing module are all connected with the storage management module, the storage management module is used for connecting with an external memory, and the front-end data processing module is used for being in communication connection with an external device;
the front-end data processing module receives analog quantity sampling data sent by an external device and sends the analog quantity sampling data to the internal memory, and the main kernel reads the analog quantity sampling data from the internal memory to perform logic operation; and the main kernel, the slave kernel and the front-end data processing module exchange data through an external memory connected with the storage management module.
2. The relay protection SoC chip for power system according to claim 1, wherein the main core reads key data from a connected external read-only memory and stores the key data in the internal memory after being started.
3. The SoC chip for relay protection in an electric power system according to claim 1, wherein the front-end data processing module receives a message, performs exception identification on the received message, and sends the identified exception information to the main core.
4. The SoC chip for relay protection in electric power system according to claim 3, wherein said front end data processing module identifies an abnormal packet in an ethernet packet sent by said external device; identifying messages which do not accord with preset standards in SV messages and GOOSE messages sent by the external device; and for the subscription message sent by the external device, checking and calculating when the transmission of the corresponding data packet is finished, and identifying the incomplete data packet according to the calculation result.
5. The SoC chip for relay protection in power system according to claim 4, wherein the front-end data processing module further performs frame counter check and CRC check on the packet sent by the main core, and identifies a packet that fails to pass the check.
6. The SoC chip for relay protection of power system according to claim 1, wherein the main core is connected to an external hardware watchdog, and the main core receives a reset level sent by the external hardware watchdog when the main core is abnormal in operation and resets the reset level.
7. The power system relay protection SoC chip according to any one of claims 1-6, wherein a timer interrupt function is built in the master core, the slave core updates a timing register of the slave core periodically according to a preset period, and the timer interrupt function resets the slave core when the timing register of the slave core is not updated in the preset period.
8. The relay protection SoC chip of claim 7, wherein the front-end data processing module periodically updates a timing register of the front-end data processing module according to the preset period, and the timer interrupt function resets the front-end data processing module when the timing register of the front-end data processing module is not updated in the preset period.
9. The relay protection SoC chip for the power system according to claim 7, wherein a task state variable corresponding to each task module in the main core is changed according to the execution times of the corresponding task module, and the timer interrupt function restarts the main core when the task state variable is not changed in the preset period.
10. The relay protection SoC chip for power system according to claim 1, wherein said main core operates in a bare core mode.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN113258546A (en) * | 2021-07-01 | 2021-08-13 | 南方电网数字电网研究院有限公司 | Chip-level software and hardware cooperative relay protection device |
| CN113258547A (en) * | 2021-07-01 | 2021-08-13 | 南方电网数字电网研究院有限公司 | Chip-level relay protection device and system |
| CN113258547B (en) * | 2021-07-01 | 2021-09-24 | 南方电网数字电网研究院有限公司 | Chip-level relay protection device and system |
| CN113258546B (en) * | 2021-07-01 | 2021-10-22 | 南方电网数字电网研究院有限公司 | Chip-level software and hardware cooperative relay protection device |
| WO2023273404A1 (en) * | 2021-07-01 | 2023-01-05 | 南方电网数字电网研究院有限公司 | Chip-level software/hardware co-operative relay protection apparatus |
| US11973338B2 (en) | 2021-07-01 | 2024-04-30 | Digital Grid Res. Inst., China Southern Pwr. Grid | Chip-level software and hardware cooperative relay protection device |
| CN114706708A (en) * | 2022-05-24 | 2022-07-05 | 北京拓林思软件有限公司 | Fault analysis method and system for Linux operating system |
| CN114706708B (en) * | 2022-05-24 | 2022-08-30 | 北京拓林思软件有限公司 | Fault analysis method and system for Linux operating system |
| CN117318173A (en) * | 2023-09-27 | 2023-12-29 | 南方电网数字电网研究院有限公司 | Multi-core heterogeneous chip applied to high-power cascading inverter |
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