CN112185821A - Design method of value-adjustable LTCC substrate embedded resistor - Google Patents
Design method of value-adjustable LTCC substrate embedded resistor Download PDFInfo
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- CN112185821A CN112185821A CN202011054827.2A CN202011054827A CN112185821A CN 112185821 A CN112185821 A CN 112185821A CN 202011054827 A CN202011054827 A CN 202011054827A CN 112185821 A CN112185821 A CN 112185821A
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- 239000000758 substrate Substances 0.000 title claims abstract description 30
- 238000000034 method Methods 0.000 title claims abstract description 29
- 239000002344 surface layer Substances 0.000 claims abstract description 27
- 239000010410 layer Substances 0.000 claims description 19
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 239000004020 conductor Substances 0.000 claims description 4
- 230000010354 integration Effects 0.000 abstract description 6
- 239000011229 interlayer Substances 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 2
- 230000001737 promoting effect Effects 0.000 abstract description 2
- 238000005245 sintering Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000007639 printing Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000010344 co-firing Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 229910052573 porcelain Inorganic materials 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/485—Adaptation of interconnections, e.g. engineering charges, repair techniques
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
The invention discloses a design method of a value-adjustable LTCC substrate embedded resistor, which designs the embedded resistor into a series resistor network by optimizing the design of the embedded resistor, presents the interconnection relationship among the resistors on a surface layer by adopting interlayer interconnection, namely a substrate bottom surface layer or a substrate top surface layer, and finally selectively breaks the interconnection of the surface layer through laser, thereby realizing the value adjustment of the embedded resistor and further improving the precision of the embedded resistor and the yield of the substrate. Under the condition that a process platform is not changed, the method for optimizing the design of the embedded resistor is adopted, the embedded resistor is designed into a resistor network connected in series, the interconnection relation between the resistors is presented on the surface layer by adopting interlayer interconnection, and finally, the interconnection of the surface layer is selectively interrupted by laser, so that the value adjustment of the embedded resistor is realized, and the precision of the embedded resistor and the yield of the substrate are improved. The method has remarkable effects of promoting the use of the embedded resistor and improving the integration level and the yield of the LTCC substrate.
Description
Technical Field
The invention relates to a design method of an LTCC substrate, in particular to a design method of an adjustable and high-precision LTCC substrate embedded resistor.
Background
LTCC (low temperature co-fired ceramic) substrates have the characteristics of high three-dimensional wiring density, small wiring sheet resistance, low sintering temperature, and good high-frequency transmission performance, and can embed elements such as resistors, capacitors, and the like, and have become an ideal mainstream substrate for multi-chip modules. Particularly, the embedded integration of passive devices such as resistors, capacitors, inductors and the like is easy to realize, so that the design flexibility and the integration level of a system are improved, the volume of the system is reduced, and the embedded integration of passive devices is a remarkable characteristic superior to that of a common thick film substrate.
For fabricating resistors on LTCC substrates, there are three ways: co-firing the top layer, post-firing the top layer and embedding the resistor. The top layer post-sintering is similar to a thick film process, the precision can be ensured through laser value adjustment, but the process is complicated, the shrinkage which is difficult to control accurately after the substrate is co-fired makes it difficult to obtain a printed resistor with better consistency, the discrete degree of the resistance value after sintering is often larger, the laser value adjustment can only adjust the resistance value greatly, and the yield is difficult to ensure. The co-firing of the top layer can better ensure the consistency of resistor printing, the discreteness of resistance value after sintering is small, but the resistance test cannot be carried out, and the problem of low yield also exists. The embedded resistor can reduce the printing area of the top layer, the integration level of the LTCC substrate is further improved, but the resistance precision is difficult to control because the embedded resistor cannot be directly adjusted by laser like a surface layer resistor, the general resistance precision is only +/-30%, and the wide application of the embedded resistor is greatly limited. In order to solve the problem, related researchers carry out a large amount of research, mostly start from optimization technology, and research reports exist, and the accuracy of the resistance value of the embedded resistor is improved to +/-18% by means of optimizing rheological characteristics of resistor paste, a printing technology, a sintering curve and the like. But the requirement on the whole process control is higher, and the precision of the laser value adjustment is still lower compared with the laser value adjustment, so that the use requirement is difficult to meet.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, and adopts a method for optimizing the design of the embedded resistor under the condition that a process platform is not changed, the embedded resistor is designed into a resistor network connected in series, the interconnection relationship among the resistors is presented on the surface layer by adopting interlayer interconnection, and finally the interconnection of the surface layer is selectively interrupted by laser, so that the value adjustment of the embedded resistor is realized, and the precision of the embedded resistor and the yield of the substrate are improved.
The technical scheme of the invention is realized as follows:
in order to achieve the above object, the method for designing an LTCC embedded resistor provided by the present invention comprises:
the method comprises the following steps: according to the historical production big data condition of the existing process, counting the resistance value precision range of the existing process embedded resistor +/-;
step two: according to the resistance value R0 which is designed as required, the actually designed resistance value R is calculated, and the relation between R0 and R is as follows: r0 ═ R (1 +);
step three: the difference between 2 times of R0 and R is divided into n1 parts, namely R1 is 2R/n 1. At this time, if R0 is designed as a resistor network of R and n 1R 1 in series, the precision range is + -22/(1+) or (2+ 2)2-2n12) N1(1+) (the larger of the two). If the precision range of the resistors needs to be further increased, the resistors R2-Rn can be connected in series on the basis of connecting n1 resistors R1 in series;
step four: as shown in fig. 2, the embedded resistors R are disposed on the k-th layer, and n 1R 1 in series with the embedded resistors R are disposed on the k-th layer or the remaining layers to form a resistor network. The resistor network is not directly connected into a circuit, but is led out to a surface layer through a conductor and a through hole in a connection relation, and the surface layer can be an upper surface layer and a bottom surface layer of a substrate;
step five: the method comprises the steps of designing and manufacturing a substrate of the embedded resistor according to the method, confirming the actual resistance value of the embedded resistor through a binding test point, selectively breaking a conduction band of short-circuit R1-Rn by adopting laser when the resistance value is out of a precision range so as to change the number of resistors connected in series to R, and adjusting the resistance value of the embedded resistor until the resistance value of the embedded resistor is in the precision range.
According to the method, the embedded resistor is designed into a series resistor network by optimizing the design of the LTCC embedded resistor under the condition that a process platform is not changed, the interconnection relation among the resistors is presented on the surface layer by adopting interlayer interconnection, and finally the interconnection of the surface layer is selectively broken by laser, so that the value adjustment of the embedded resistor is realized, and the precision of the embedded resistor and the yield of the substrate are improved. The method has remarkable effects of promoting the use of the embedded resistor and improving the integration level and the yield of the LTCC substrate. According to the invention, through optimizing the design of the embedded resistors, the embedded resistors are designed into a resistor network connected in series, the interconnection relationship among the resistors is presented on the surface layer by adopting interlayer interconnection, namely the bottom surface layer or the top surface layer of the substrate, and finally, the interconnection of the surface layers is selectively broken through laser, so that the value adjustment of the embedded resistors is realized, and the precision of the embedded resistors and the yield of the substrate are improved.
Drawings
FIG. 1 is a simplified schematic diagram of the value adjustment of the embedded resistor according to the present invention
FIG. 2 is a schematic diagram of an embedded resistor design according to an embodiment of the present invention
1. A resistance test point; 2. cutting a conduction band by laser; 3. a buried resistor; 4. LTCC green porcelain; 5. a via hole; 6. and a conduction band is embedded inside.
Detailed Description
The technical solution in the embodiments of the present invention is described in further detail below with reference to the accompanying drawings in the embodiments of the present invention:
referring to fig. 1, a simplified schematic diagram of the present invention is shown, in which resistors R, R1 … … Rn are designed as resistor networks connected in series, and a short-circuit line is disposed on each Rx, so that the resistors connected to the resistor networks can be controlled by selectively breaking the short-circuit lines.
Referring to fig. 2, which is a schematic diagram of a design of an embedded resistor according to a first embodiment of the present invention, in a design process, an embedded resistor R0 is designed on a k-th layer, and resistors to be connected in series are designed on k +1, k +2, and k + 3-th layers, a series relation and a short-circuit line are led out to a surface layer through wiring interconnection, and two ends of a resistor network are also led out to the surface layer to serve as test points of resistance values of the resistors.
In the first circuit design of the embodiment, a 130 Ω resistor needs to be embedded in the LTCC substrate, and the precision of the resistance value is required to be controlled within ± 15% after the value adjustment.
The specific steps of this example are as follows:
step one, according to the historical production big data condition of the existing process, the accuracy range of the resistance value of the embedded resistor of a certain LTCC production line is calculated to be +/-30%;
step two, calculating an actually designed resistance value R of 100 omega according to a resistance value R0 of 130 omega which is designed as required;
and step three, dividing the difference between 2 times of R0 and R into 3 parts, namely, R1 is 20 omega. The accuracy range is calculated to be +/-13.8 percent, and the design requirement can be met;
step four, as shown in the attached figure 2, laying R on the kth layer, laying 3R 1 on the kth +1 layer, the kth +2 layer and the kth +3 layer respectively, and leading out the serial relation between R and R1 and the test point of the resistance value of the resistor network to the surface layer through a conductor and a through hole;
and fifthly, manufacturing the LTCC substrate according to the design of the fourth step, confirming the actual resistance value of the embedded resistor through pricking the test points of the 2 resistors, and when the resistance value precision is beyond +/-15%, breaking the conduction band of the short-circuit R1 by adopting laser to adjust the resistance value of the embedded resistor until the resistance value precision range is within +/-15%.
In the second circuit design, a 130 Ω resistor needs to be embedded in the LTCC substrate, and the precision of the resistance value is required to be controlled within ± 10%.
The specific steps of this example are as follows:
step one, according to the historical production big data condition of the existing process, the accuracy range of the resistance value of the embedded resistor of a certain LTCC production line is calculated to be +/-30%;
step two, calculating an actually designed resistance value R of 100 omega according to a resistance value R0 of 130 omega which is designed as required;
and step three, dividing the difference between 2 times of R0 and R into 3 parts, namely, R1 is 20 omega. Therefore, the accuracy range is calculated to be only +/-13.8%, and the design requirement is not met, so that the series resistance is required to be continuously connected. Through calculation, on the basis of connecting 3R 1 in series, one R2 is connected in series to 12 omega, and the accuracy range can be +/-10%;
step four, laying R on a kth layer, laying 3R 1 and 1R 2 on kth +1, k +2, k +3 and k +4 layers respectively, and leading out the series relation of R, R1 and R2 and the test point of the resistance value of the resistor network to the surface layer through a conductor and a through hole;
and fifthly, manufacturing the LTCC substrate according to the design of the fourth step, confirming the actual resistance value of the embedded resistor through pricking the resistor test point, when the resistance value precision is beyond +/-13.8%, breaking the conduction band of the short-circuit R1 by adopting laser, and after adjustment, once the resistance value precision is within +/-13.8%, but beyond +/-10%, breaking the conduction band of the short-circuit R2 until the resistance value precision range is within +/-10%.
Claims (1)
1. A design method of a value-adjustable LTCC substrate embedded resistor is characterized by comprising the following steps:
the method comprises the following steps: according to the historical production big data condition of the existing process, counting the resistance value precision range of the existing process embedded resistor +/-;
step two: according to the resistance value R0 which is designed as required, the actually designed resistance value R is calculated, and the relation between R0 and R is as follows: r0 ═ R (1 +);
step three: the difference between 2 times of R0 and R is divided into n1 parts, namely R1 is 2R/n 1. At this time, if R0 is designed as a resistor network of R and n 1R 1 in series, the precision range is + -22/(1+) or (2+ 2)2-2n12) The larger of the two is selected from/n 1(1+), and if the precision range of the resistor needs to be further increased, the resistor R2-Rn is connected in series on the basis of connecting n 1R 1 in series;
step four: the embedded resistors R are distributed on the kth layer, and n 1R 1 which are in series connection with the embedded resistors R are distributed on the kth layer or other layers to form a resistor network, the resistor network is not directly connected into a circuit, but the connection relation of the resistor network is led out to the surface layer through a conductor and a through hole, and the surface layer can be an upper surface layer and a bottom surface layer of the substrate;
step five: the method comprises the steps of designing and manufacturing a substrate of the embedded resistor according to the method, confirming the actual resistance value of the embedded resistor through a binding test point, selectively breaking a conduction band of short-circuit R1-Rn by adopting laser when the resistance value is out of a precision range so as to change the number of resistors connected in series to R, and adjusting the resistance value of the embedded resistor until the resistance value of the embedded resistor is in the precision range.
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| CN202011054827.2A CN112185821B (en) | 2020-09-28 | 2020-09-28 | Design method of value-adjustable LTCC substrate embedded resistor |
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| CN202011054827.2A CN112185821B (en) | 2020-09-28 | 2020-09-28 | Design method of value-adjustable LTCC substrate embedded resistor |
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| CN112185821B CN112185821B (en) | 2023-03-07 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080131980A1 (en) * | 2006-12-05 | 2008-06-05 | International Business Machines Corporation | Method of adjusting buried resistor resistance |
| CN202149825U (en) * | 2011-07-26 | 2012-02-22 | 西安创联电气科技（集团）有限责任公司 | Bridge circuit balancer for thick film ceramic piezoresistive type pressure sensor |
| CN102915818A (en) * | 2012-10-08 | 2013-02-06 | 华东光电集成器件研究所 | Method for controlling resistance of thick-film resistor |
| CN109859919A (en) * | 2019-03-04 | 2019-06-07 | 电子科技大学 | A method of reducing potting formula resistance error |
| CN109905970A (en) * | 2019-01-23 | 2019-06-18 | 西安微电子技术研究所 | A kind of ltcc substrate production method based on ultrafast laser etching |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080131980A1 (en) * | 2006-12-05 | 2008-06-05 | International Business Machines Corporation | Method of adjusting buried resistor resistance |
| CN202149825U (en) * | 2011-07-26 | 2012-02-22 | 西安创联电气科技（集团）有限责任公司 | Bridge circuit balancer for thick film ceramic piezoresistive type pressure sensor |
| CN102915818A (en) * | 2012-10-08 | 2013-02-06 | 华东光电集成器件研究所 | Method for controlling resistance of thick-film resistor |
| CN109905970A (en) * | 2019-01-23 | 2019-06-18 | 西安微电子技术研究所 | A kind of ltcc substrate production method based on ultrafast laser etching |
| CN109859919A (en) * | 2019-03-04 | 2019-06-07 | 电子科技大学 | A method of reducing potting formula resistance error |
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