CN112136212A - 芯片互联装置、集成桥结构的基板及其制备方法 - Google Patents

芯片互联装置、集成桥结构的基板及其制备方法 Download PDF

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Publication number
CN112136212A
CN112136212A CN201980000565.0A CN201980000565A CN112136212A CN 112136212 A CN112136212 A CN 112136212A CN 201980000565 A CN201980000565 A CN 201980000565A CN 112136212 A CN112136212 A CN 112136212A
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China
Prior art keywords
chip
bump
bridge structure
welding point
substrate
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Granted
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CN201980000565.0A
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English (en)
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CN112136212B (zh
Inventor
王红超
沈健
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Shenzhen Goodix Technology Co Ltd
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Shenzhen Goodix Technology Co Ltd
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Publication of CN112136212A publication Critical patent/CN112136212A/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1701—Structure
    • H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Combinations Of Printed Boards (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

本申请部分实施例提供了一种芯片互联装置及其制备方法。芯片互联装置包括：第一芯片102、第二芯片103、基板101桥结构；桥结构包括绝缘本体104、位于绝缘本体内的导电件111、位于绝缘本体的表面的第一焊点109和第二焊点110，导电件111的第一端与第一焊点109连接，且第二端与第二焊点110连接；第一芯片102与第一焊点109连接，第二芯片103与第二焊点110连接；第一芯片和第二芯片均与基板连接，使得在实现芯片与芯片之间电气互联的同时工艺流程更加简单，降低了组装难度。

Description

PCT国内申请，说明书已公开。

Claims (21)

  1. PCT国内申请，权利要求书已公开。
CN201980000565.0A 2019-04-24 2019-04-24 芯片互联装置、集成桥结构的基板及其制备方法 Active CN112136212B (zh)

Applications Claiming Priority (1)

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PCT/CN2019/084082 WO2020215249A1 (zh) 2019-04-24 2019-04-24 芯片互联装置、集成桥结构的基板及其制备方法

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CN112136212B CN112136212B (zh) 2022-07-29

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WO (1) WO2020215249A1 (zh)

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Publication number Priority date Publication date Assignee Title
CN116093046A (zh) * 2023-04-10 2023-05-09 北京华封集芯电子有限公司 单颗芯片的制备方法及芯片结构
CN116798961B (zh) * 2023-06-21 2024-03-15 上海韬润半导体有限公司 一种减少热应力影响的芯片封装结构及方法

Citations (9)

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CN101276765A (zh) * 2007-03-30 2008-10-01 施乐公司 喷墨印刷引线键合,密封剂和屏蔽
CN103187377A (zh) * 2011-12-28 2013-07-03 美国博通公司 具有桥型中介片的半导体封装
US20150201500A1 (en) * 2014-01-12 2015-07-16 Zohar SHINAR System, device, and method of three-dimensional printing
CN105161432A (zh) * 2015-09-17 2015-12-16 中芯长电半导体（江阴）有限公司 一种芯片封装方法
US20160056125A1 (en) * 2014-08-20 2016-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid Interconnect for Chip Stacking
CN105408095A (zh) * 2013-06-24 2016-03-16 哈佛学院院长等 打印的三维(3d)功能部件及其制造方法
CN106206409A (zh) * 2015-05-08 2016-12-07 华邦电子股份有限公司 堆叠电子装置及其制造方法
CN107405826A (zh) * 2015-03-17 2017-11-28 飞利浦照明控股有限公司 制作具有互连和嵌入式部件的3d打印形状
US20190115319A1 (en) * 2016-01-27 2019-04-18 Amkor Technology, Inc. Semiconductor package and fabricating method thereof

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CN106206331B (zh) * 2015-05-08 2019-02-01 华邦电子股份有限公司 堆叠封装装置及其制造方法
US10438881B2 (en) * 2015-10-29 2019-10-08 Marvell World Trade Ltd. Packaging arrangements including high density interconnect bridge

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101276765A (zh) * 2007-03-30 2008-10-01 施乐公司 喷墨印刷引线键合,密封剂和屏蔽
CN103187377A (zh) * 2011-12-28 2013-07-03 美国博通公司 具有桥型中介片的半导体封装
CN105408095A (zh) * 2013-06-24 2016-03-16 哈佛学院院长等 打印的三维(3d)功能部件及其制造方法
US20150201500A1 (en) * 2014-01-12 2015-07-16 Zohar SHINAR System, device, and method of three-dimensional printing
US20160056125A1 (en) * 2014-08-20 2016-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid Interconnect for Chip Stacking
CN107405826A (zh) * 2015-03-17 2017-11-28 飞利浦照明控股有限公司 制作具有互连和嵌入式部件的3d打印形状
CN106206409A (zh) * 2015-05-08 2016-12-07 华邦电子股份有限公司 堆叠电子装置及其制造方法
CN105161432A (zh) * 2015-09-17 2015-12-16 中芯长电半导体（江阴）有限公司 一种芯片封装方法
US20190115319A1 (en) * 2016-01-27 2019-04-18 Amkor Technology, Inc. Semiconductor package and fabricating method thereof

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CN112136212B (zh) 2022-07-29

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