CN112086533A - Intermediate series layer of laminated cell, laminated cell and photovoltaic module - Google Patents

Intermediate series layer of laminated cell, laminated cell and photovoltaic module Download PDF

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CN112086533A
CN112086533A CN202010850733.XA CN202010850733A CN112086533A CN 112086533 A CN112086533 A CN 112086533A CN 202010850733 A CN202010850733 A CN 202010850733A CN 112086533 A CN112086533 A CN 112086533A
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徐琛
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Longi Green Energy Technology Co Ltd
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Abstract

The invention provides an intermediate series layer of a laminated cell, the laminated cell and a photovoltaic module, and relates to the technical field of solar photovoltaics. The middle series layer is of a tunneling junction structure and comprises a heavily doped n-type silicon layer, a heavily doped p-type silicon layer and a transparent conducting layer positioned between the heavily doped n-type silicon layer and the heavily doped p-type silicon layer. Due to the high conductivity and the carrier exchange capacity of the transparent oxide layer, the carrier exchange rate is improved, so that the conversion efficiency of the cell is improved, the photoelectric loss is reduced, the transparent oxide layer, the heavily doped n-type silicon layer and the heavily doped p-type silicon layer have good contact characteristics, the high defect state density treatment of an interface is not required, and the requirement of a preparation process is reduced; in addition, due to the fact that the transverse conductivity of the heavily-doped n-type silicon layer and the heavily-doped p-type silicon layer is poor, the probability that current carriers pass through a leakage point of the top battery is reduced, the risk that the top battery is short-circuited is reduced, large-area preparation of the solar battery is facilitated, and the yield of finished products of the battery is improved.

Description

Intermediate series layer of laminated cell, laminated cell and photovoltaic module
Technical Field
The invention relates to the technical field of solar photovoltaics, in particular to an intermediate series layer of a laminated cell, the laminated cell and a photovoltaic module.
Background
The laminated cell is a solar cell with high photoelectric conversion efficiency, and the photoelectric conversion efficiency can reach more than 30 percent (> 29.4 percent of silicon cell ultimate efficiency). The laminated cell can be obtained by sequentially preparing an intermediate series layer and a top cell on a bottom cell, wherein the intermediate series layer can exchange carriers between the top cell and the bottom cell, and therefore, the photoelectric performance of the laminated cell directly influences the photoelectric conversion efficiency of the laminated cell.
In the conventional solar cell, an n/p type silicon-based tunneling junction is used as an intermediate series layer and is limited by process conditions, the tunneling barrier of the n/p type silicon-based tunneling junction is higher, so that the tunneling probability of current carriers is low, the density of defect states at an interface is low, the exchange rate of the current carriers is low, the recombination loss of photon-generated current carriers is increased, and the electrical loss at the tunneling junction in the solar cell is high; the TCO composite junction is used as the middle series layer, the TCO film has strong optical parasitic absorption, short-circuit current of the solar cell is reduced, current mismatch between the top cell and the bottom cell is caused, and due to the excellent transverse conductivity of the TCO film, current carriers can easily penetrate through a leakage point, so that the top cell is short-circuited and fails.
Therefore, how to adjust the structure of the intermediate series layer to make the solar cell carrier transmission efficient, have low photoelectric loss and simple process, and be easy to prepare in a large area is the key point of research in the field.
Disclosure of Invention
The invention provides an intermediate series layer of a laminated cell, the laminated cell and a photovoltaic module, and aims to improve the conversion efficiency of the cell, improve the yield of a prepared finished product and reduce the photoelectric loss.
In a first aspect, an embodiment of the present invention provides an intermediate series layer of a stacked cell, where the intermediate series layer is a tunnel junction structure, and the intermediate series layer includes a heavily doped n-type silicon layer, a heavily doped p-type silicon layer, and a transparent conductive layer located between the heavily doped n-type silicon layer and the heavily doped p-type silicon layer;
the doping concentration of the heavily doped n-type silicon layer and the heavily doped p-type silicon layer are both 1018cm-3The above;
the heavily doped n-type silicon layer is a heavily doped n-type amorphous silicon layer, a heavily doped n-type microcrystalline silicon layer or a heavily doped n-type nanocrystalline silicon layer;
the heavily doped p-type silicon layer is a heavily doped p-type amorphous silicon layer, a heavily doped p-type microcrystalline silicon layer or a heavily doped p-type nanocrystalline silicon layer.
Optionally, the doping concentration of the heavily doped n-type silicon layer is 1019～1020cm-3。
Optionally, the doping concentration of the heavily doped p-type silicon layer is 1018～1019cm-3。
Optionally, the thickness of the heavily doped n-type silicon layer is 1nm to 10 nm.
Optionally, the thickness of the heavily doped p-type silicon layer is 1nm to 10 nm.
Optionally, the transparent conductive layer is selected from any one of an indium tin oxide layer, a tungsten-doped indium oxide layer, a titanium-doped indium oxide layer and a hydrogen-doped indium oxide layer.
Optionally, the thickness of the transparent conductive layer is 1nm to 20 nm.
In a second aspect, embodiments of the present invention provide a stacked battery, which includes a top battery cell, a bottom battery cell, and the intermediate series layer of the first aspect;
the intermediate series layer is located between the top cell unit and the bottom cell unit.
Optionally, the top cell unit is a perovskite cell, and the bottom cell unit is a crystalline silicon cell.
In a third aspect, embodiments of the present invention provide a photovoltaic module, which includes the tandem cell of the second aspect.
In the embodiment of the invention, the laminated cell comprises a middle series layer of a tunneling junction structure, wherein the middle series layer comprises a heavily doped n-type silicon layer, a heavily doped p-type silicon layer and a transparent oxide layer positioned between the heavily doped n-type silicon layer and the heavily doped p-type silicon layer, and the carrier exchange rate is improved due to the high conductivity and the carrier exchange capacity of the transparent oxide layer, so that the conversion efficiency of the cell is improved, the photoelectric loss is reduced, the transparent oxide layer, the heavily doped n-type silicon layer and the heavily doped p-type silicon layer have good contact characteristics, the high defect state density processing of interfaces is not required, and the preparation process requirement is reduced; in addition, due to the fact that the transverse conductivity of the heavily-doped n-type silicon layer and the heavily-doped p-type silicon layer is poor, the probability that current carriers pass through a leakage point of the top battery is reduced, the risk that the top battery is short-circuited is reduced, large-area preparation of the solar battery is facilitated, and the yield of finished products of the battery is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.
Fig. 1 shows a schematic diagram of an intermediate series layer structure of a stacked cell in an embodiment of the invention;
fig. 2 shows a schematic view of a stacked cell structure in an embodiment of the invention;
fig. 3 shows a schematic structural diagram of another stacked cell in the embodiment of the invention.
Description of reference numerals:
FIG. 1: 101-heavily doped n-type silicon layer; 102-a transparent conductive layer; 103-heavily doped p-type silicon layer;
FIG. 2 and FIG. 3: 201-top cell unit; 202-intermediate series layer; 203-bottom cell; 2011-hole transport layer; 2012-perovskite absorption layer; 2013-electron transport layer; 2014-a first external electrode structure; 2021-heavily doped n-type silicon layer; 2022-transparent conductive layer; 2023-heavily doped p-type silicon layer; 2031-a second external electrode configuration; 2032-back field; 2033-a monocrystalline silicon substrate; 2034-emitter.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 shows a schematic diagram of a middle series layer structure of a stacked cell in an embodiment of the present invention, as shown in fig. 1, the middle series layer 10 is a tunnel junction structure, and the middle series layer 10 includes a heavily doped n-type silicon layer 101, a heavily doped p-type silicon layer 103, and a transparent conductive layer 102 located between the heavily doped n-type silicon layer 101 and the heavily doped p-type silicon layer 103.
In an embodiment of the invention, the intermediate series layer 10 is applied in a stacked cell. Optionally, the stacked cell may be obtained by connecting at least two subcells through an intermediate series layer 10, wherein the intermediate series layer 10 adds a transparent conductive layer 102 between the heavily doped n-type silicon layer 101 and the heavily doped p-type silicon layer 103, so that high-efficiency carrier exchange can be realized by utilizing high conductivity of the transparent conductive layer 102, the doping rate requirements on the heavily doped n-type silicon layer 101 and the heavily doped p-type silicon layer 103 are reduced, and the transparent conductive layer 102 can be in good contact with the heavily doped n-type silicon layer 101 and the heavily doped p-type silicon layer 103 respectively, so that photogenerated carriers are exchanged rapidly, and the requirement on an interface defect state is reduced; meanwhile, the parasitic absorption of the transparent conducting layer 102 is reduced by the heavily doped n-type silicon layer 101 and the heavily doped p-type silicon layer 103, the risk of short circuit of the battery is reduced by the poor conducting rate, and the agglomeration problem caused by annealing of a hole transmission layer when the laminated battery is prepared is avoided due to the rough surface, so that the yield of the finished laminated battery can be improved, and the large-area preparation is easy.
In the invention, the doping concentrations of the heavily doped n-type silicon layer 101 and the heavily doped p-type silicon layer 103 are both 1018cm-3The above.
In the invention, heavily doped means that more impurities are doped in a silicon layer, and the conductivity types of the silicon layer are different according to the different doped impurity types, for example, the silicon layer doped with more donor impurities is a heavily doped n-type silicon layer, and the silicon layer doped with more acceptor impurities is a heavily doped p-type silicon layer, wherein the donor impurities are impurities which are ionized to generate free electrons after doping and form positive electric centers, such as phosphorus, arsenic and the like; acceptor impurities are impurities that, when doped, abstract electrons from silicon atoms and form holes and electronegative centers, such as boron. Optionally, in the embodiment of the invention, more impurities may be dopedSo as to dope 10 in the silicon layer18cm-3The above donor impurity or acceptor impurity, thereby obtaining a heavily doped n-type silicon layer or the heavily doped p-type silicon layer.
Optionally, the heavily doped n-type silicon layer 101 is a heavily doped n-type amorphous silicon layer, a heavily doped n-type microcrystalline silicon layer, or a heavily doped n-type nanocrystalline silicon layer.
Optionally, the heavily doped p-type silicon layer 103 is a heavily doped p-type amorphous silicon layer, a heavily doped p-type microcrystalline silicon layer, or a heavily doped p-type nanocrystalline silicon layer.
In the embodiment of the present invention, the heavily doped n-type silicon layer 101 and the heavily doped p-type silicon layer 103 may be obtained by doping an amorphous silicon layer, a crystalline silicon layer, or a nanocrystalline silicon layer, and according to different process conditions and application requirements, a person skilled in the art may select different silicon layers for doping, which is not specifically limited in the embodiment of the present invention.
Optionally, the doping concentration of the heavily doped n-type silicon layer 101 is 1019～1020cm-3。
Optionally, the thickness of the heavily doped n-type silicon layer 101 is 1nm to 10 nm.
In the embodiment of the present invention, when the donor impurity is doped into the silicon layer, the doping concentration is 1019～1020cm-3In an arbitrary number of concentrations. E.g., the heavily doped n-type silicon layer 101 may have a doping concentration of 1019、1020And the like. Optionally, the thickness of the heavily doped n-type silicon layer 101 may be any value between 1nm and 10nm, and in the case of meeting the process conditions, it is avoided that the efficiency of carrier transmission is affected by the excessive thickness of the heavily doped n-type silicon layer 101, for example, the thickness of the heavily doped n-type silicon layer 101 may be 1nm, 3nm, 5nm, 6nm, 8nm, 10nm, or the like. The doping concentration and thickness of the heavily doped n-type silicon layer 101 according to the embodiment of the present invention are not particularly limited.
Optionally, the doping concentration of the heavily doped p-type silicon layer 103 is 1018～1019cm-3。
Optionally, the thickness of the heavily doped p-type silicon layer 103 is 1nm to 10 nm.
In the embodiment of the invention, when the acceptor impurity is doped into the silicon layer, the doping concentration is carried outDegree of 1018cm-3While keeping the above at 1019cm-3In the following, to avoid too high doping concentration, for example, the doping concentration of the heavily doped p-type silicon layer 103 may be 1018、1019cm-3And the like. Optionally, the thickness of the heavily doped p-type silicon layer 103 may be any value between 1nm and 10nm, and reference may be specifically made to the description of the heavily doped n-type silicon layer 101, which is not repeated herein to avoid repetition.
Optionally, the transparent conductive layer 102 is selected from any one of an indium tin oxide layer, a tungsten-doped indium oxide layer, a titanium-doped indium oxide layer, and a hydrogen-doped indium oxide layer.
Optionally, the thickness of the transparent conductive layer 102 is 1nm to 20 nm.
In the embodiment of the present invention, the transparent conductive layer 102 is used to efficiently transmit carriers between the heavily doped n-type silicon layer and the heavily doped p-type silicon layer, and therefore, the material of the transparent conductive layer 102 needs to have good conductivity to meet the requirement of the battery under the condition that the material is transparent to reduce the parasitic absorption of light. Optionally, the transparent conductive layer 102 may be any one selected from an indium tin oxide layer, a tungsten-doped indium oxide layer, a titanium-doped indium oxide layer, and a hydrogen-doped indium oxide layer, and the requirements of transparency and conductivity are met. Optionally, the thickness of the transparent conductive layer 102 may be any value from 1nm to 20nm, so as to avoid that the carrier transmission efficiency is affected by the excessive thickness of the transparent conductive layer 102, and under the condition that the process conditions allow, a person skilled in the art may select the thickness of the transparent conductive layer 102 according to actual requirements, such as 1nm, 5nm, 10nm, 15nm, 20nm, and the like, which is not specifically limited by the implementation of the present invention.
Referring to fig. 2, fig. 2 shows a schematic structural diagram of a stacked battery 20 in an embodiment of the present invention, and as shown in fig. 2, the stacked battery 20 includes a top battery cell 201, a bottom battery cell 203, and an intermediate series layer 202 as shown in fig. 1.
The middle series layer 202 is located between the top cell 201 and the bottom cell 203.
In the embodiment of the present invention, the top cell 201 and the bottom cell 203 may be connected in series through the middle series layer 202, so as to perform carrier transmission between the top cell 201 and the bottom cell 202, thereby obtaining a high efficiency stacked cell, wherein the middle series layer 202 includes a heavily doped n-type silicon layer 2021, a heavily doped p-type silicon layer 2023, and a transparent conductive layer 2022 located between the heavily doped n-type silicon layer 2021 and the heavily doped p-type silicon layer 2023. The battery types of the top battery cell 201 and the bottom battery cell 203 are not particularly limited in the embodiment of the present invention.
It will be appreciated that the heavily doped n-type silicon layer 2021 in the intermediate series layer 202 interfaces with the electron extraction side (e.g., electron transport layer or n-type layer) in the top cell 201 or bottom cell 203, while the heavily doped p-type silicon layer 2022 in the intermediate series layer 202 interfaces with the hole extraction side (e.g., hole transport layer or p-type layer) in the bottom cell 203 or top cell 201.
Optionally, the top cell unit 201 is a perovskite cell, and the bottom cell unit 203 is a crystalline silicon cell.
In an embodiment of the present invention, the top cell 201 may be a perovskite cell, and as shown in fig. 2, the top cell 201 may include a hole transport layer 2011, an electron transport layer 2013, a perovskite absorption layer 2012 located between the hole transport layer 2011 and the electron transport layer 2013, and a first external electrode structure 2014 located at a side away from the intermediate series layer 202. The bottom cell 203 may be a crystalline silicon cell, and as shown in fig. 2, the bottom cell 203 may include a back field 2032 on one side of a monocrystalline silicon base 2033, an emitter 2034 on the other side, and a second external electrode structure 2031 on the side away from the intermediate series layer 202.
Optionally, the top cell unit 201 and the bottom cell unit 202 may further include other functional layers, such as a passivation layer, and the like, which is not particularly limited in this embodiment of the present invention.
In the embodiment of the present invention, as shown in fig. 2, the middle series layer 202 may be connected to the emitter 2034 of the bottom cell 203 through the heavily doped n-type silicon layer 2021, and the heavily doped p-type silicon layer 2023 is connected to the hole transport layer 2011 of the top cell 201 to connect the top cell 201 and the bottom cell 203 in series.
Fig. 3 shows a schematic structural diagram of another stacked cell 20 in the embodiment of the invention, as shown in fig. 3, on the basis of fig. 2, the middle series layer 202 may further be connected to the back field 2032 of the bottom cell 203 through a heavily doped p-type silicon layer 2023, and the top cell 201 and the bottom cell 203 are connected in series in a manner that the heavily doped n-type silicon layer 2021 is connected to the electron transport layer 2013 of the top cell 201, at this time, the hole transport layer 2011 in the top cell 201 is connected to the first external electrode structure 2014, and the emitter 2034 in the bottom cell 203 is connected to the second external electrode structure 2031.
In the embodiment of the invention, the laminated cell comprises a middle series layer of a tunneling junction structure, wherein the middle series layer comprises a heavily doped n-type silicon layer, a heavily doped p-type silicon layer and a transparent oxide layer positioned between the heavily doped n-type silicon layer and the heavily doped p-type silicon layer, and the carrier exchange rate is improved due to the high conductivity and the carrier exchange capacity of the transparent oxide layer, so that the conversion efficiency of the cell is improved, the photoelectric loss is reduced, the transparent oxide layer, the heavily doped n-type silicon layer and the heavily doped p-type silicon layer have good contact characteristics, the high defect state density processing of interfaces is not required, and the preparation process requirement is reduced; in addition, due to the fact that the transverse conductivity of the heavily-doped n-type silicon layer and the heavily-doped p-type silicon layer is poor, the probability that current carriers pass through a leakage point of the top battery is reduced, the risk that the top battery is short-circuited is reduced, large-area preparation of the solar battery is facilitated, and the yield of finished products of the battery is improved.
Embodiments of the present invention also provide a photovoltaic module, which includes the tandem cell shown in fig. 2 or fig. 3.
The embodiment of the invention provides a method for preparing a laminated battery, taking a laminated battery 20 as an example, the method can comprise the following steps:
step S11, polishing, texturing, and cleaning the single crystal silicon substrate 2033.
In the embodiment of the present invention, the monocrystalline silicon substrate 2033 may be a commercial-grade (working temperature is 0 to 70 ℃) M2(156.75mm) silicon wafer, the resistivity may be 1 Ω · cm to 10 Ω · cm, and the thickness is 150um to 200 um.
For example, a commercial grade M2 silicon wafer having a thickness of 180um and a resistivity of 5 Ω · cm is polished with an alkaline solution, textured, and cleaned to obtain a single crystal silicon substrate 2033 having a pyramidal texture.
Step S12, an intrinsic amorphous silicon passivation layer and a p-type amorphous silicon layer are sequentially prepared on one side of the single crystal silicon substrate 2033, and a back surface field 2032 is obtained.
In the embodiment of the invention, the thickness of the intrinsic amorphous silicon passivation layer on the side of the monocrystalline silicon substrate 2033 can be 5nm to 10nm, and the doping concentration of the p-type amorphous silicon layer can be 1019-20cm-3The thickness may be 5nm to 15 nm.
For example, a back surface field 2032 is obtained by depositing a 10nm intrinsic amorphous silicon passivation layer on the side of the single crystal silicon substrate 2033 by PECVD (Plasma Enhanced Chemical Vapor Deposition), and then depositing a 15nm thick, boron-doped p-type amorphous silicon layer on the intrinsic amorphous silicon passivation layer by a hydrogen-diluted diborane and silane mixed gas.
Step S13, an intrinsic amorphous silicon passivation layer and an n-type amorphous silicon layer, or an intrinsic amorphous silicon passivation layer and an n-type silicon oxide layer, are sequentially prepared on the other side of the single crystal silicon substrate 2033 to obtain the emitter 2034.
In the embodiment of the invention, the intrinsic amorphous silicon passivation layer on the other side of the monocrystalline silicon substrate 2033 can be an n-type amorphous silicon layer or an n-type silicon-oxygen (SiO) layer with a thickness of 5 nm-10 nmx) The thickness of the layer is 5 nm-15 nm, and the doping concentration of the n-type amorphous silicon layer may be 1019 -20cm-3。
For example, an intrinsic amorphous silicon passivation layer of 10nm is deposited on the other side of the single crystal silicon substrate 2033 by PECVD, and an n-type amorphous silicon layer of 10nm thickness is deposited on the intrinsic amorphous silicon passivation layer by a phosphine and silane mixed gas diluted by hydrogen, to obtain the emitter 2034.
Step S14, a heavily doped n-type silicon layer 2021 is prepared on the emitter 2034.
In the embodiment of the invention, the heavily doped n-type silicon layer 2021 has a doping concentration of 1019～1020cm-3The thickness is 1nm to 10 nm.
For example, a 5nm heavily doped n-type microcrystalline silicon layer may be formed on emitter 2034 by mixing phosphine with a gas mixture having a hydrogen to silane flow ratio of 250.
Step S15, a transparent conductive layer 2022 is prepared on the heavily doped n-type silicon layer 2021.
In the embodiment of the present invention, the transparent conductive layer 2022 may be any one of ITO (indium tin oxide layer), IWO (tungsten-doped indium oxide layer), ITiO (titanium-doped indium oxide layer), IOH (hydrogen-doped indium oxide layer), and the like, and has a thickness of 1nm to 20 nm.
For example, an ITO film layer of 10nm is prepared as the transparent conductive layer 2022 by a magnetron sputtering device using an ITO target material, wherein the sputtering power density is 1.5W/cm2The flow ratio of oxygen to argon was 2%, and the bombardment damage to the amorphous silicon layer was reduced by low power density.
Step S16, a heavily doped p-type silicon layer 2023 is prepared on the transparent conductive layer 2022.
In the embodiment of the invention, the doping concentration of the heavily doped p-type silicon layer 2023 is 1018～1019cm-3The thickness is 1nm to 10 nm.
For example, a heavily doped p-type microcrystalline silicon layer is formed as the heavily doped p-type silicon layer 2023 on the transparent conductive layer 2022 using silane (hydrogen gas to silane flow ratio of 250) and diborane mixed gas at a hydrogen dilution ratio.
Step S17, a hole transport layer 2011 is prepared on the heavily doped p-type silicon layer 2023.
In the embodiment of the present invention, the thickness of the hole transport layer 2011 may be 10nm to 15nm, and the hole transport layer 2011 may be made of an organic material such as Spiro-OMeTAD (2,2',7,7' -tetrakis [ N, N-bis (4-methoxyphenyl) amino group]-9,9 '-spirobifluorene), Sprio-TTB (tetrakis (di-p-tolylamino) spiro-9, 9' -bifluorene), PTAA (poly [ bis (4-phenyl) (2,4, 6-trimethylphenyl) amine]) TATM (mannose triflate), and the like, and may also be an inorganic material such as MoOx(molybdenum oxide), NiOx(Nickel oxide), Cu2O (cuprous oxide), etc., and this is not particularly limited by the embodiments of the present invention.
For example, on the heavily doped p-type silicon layer 2023, a Sprio-TTB hole transport layer 2011 with a thickness of 10nm is prepared by an evaporation method through Sprio-TTB material, and the evaporation speed is highA rate of
Figure BDA0002644640700000091
Step S18 is to prepare a perovskite absorption layer 2012 on the hole transport layer 2011.
In embodiments of the present invention, the perovskite absorption layer 2012 is used to absorb incident light and generate corresponding photogenerated carriers, and the component of the perovskite absorption layer 2012 may be MAPbI3、FAPbI3、(Cs0.15FA0.85)Pb(I0.7Br0.3)3Etc., and the thickness may be 350nm to 500 nm.
For example, a double-source co-evaporation method is adopted to prepare a perovskite precursor layer on the hole transport layer 2011, and specifically, the evaporation rate of cesium bromide is firstly adjusted to
Figure BDA0002644640700000092
The evaporation rate of lead iodide is
Figure BDA0002644640700000093
Thereby depositing to obtain a mixed layer of lead iodide and cesium bromide with the thickness of 400nm, and dripping 90uL of FAI (formamidine hydroiodide) and FABr (formamidine hydrobromide) solution (the molar concentration ratio of FAI to FABr is 3:1) on PbI2And (3) immediately spin-coating the mixed layer of lead iodide and CsBr to obtain a perovskite precursor layer, and annealing at 150 ℃ for 30min to form a perovskite absorption layer 2012.
Step S19, preparing an electron transport layer 2013 on the perovskite absorption layer 2012.
In the embodiment of the invention, the electron transport layer 2013 can be formed by preparing an organic layer on the perovskite thin film by an evaporation method and then preparing an inorganic electron transport layer with the thickness of 10 nm-20 nm by Atomic Layer Deposition (ALD), so that the longitudinal transport of carriers is realized. Alternatively, the material of the organic layer may be C60 (carbon 60), PCBM (fullerene derivative), or the like, and the material of the inorganic electron transport layer may be SnO2(tin oxide), TiO2(titanium oxide), and the like.
For example, the perovskite absorption layer 20 is first coated by a vacuum coating device12 to adopt
Figure BDA0002644640700000094
Evaporating C60 with the thickness of 10nm at the evaporation rate, and preparing SnO with the thickness of 10nm by using atomic layer deposition equipment2An electron transport layer 2013 is obtained.
In the embodiment of the present invention, the top battery unit 201 further includes a first external electrode structure 2014, specifically, a transparent conductive film with a thickness of 110nm is deposited on one side of the electron transport layer 2013 away from the perovskite absorption layer 2012 by magnetron sputtering, a silver gate line electrode with a thickness of 200nm is evaporated on the transparent conductive film by a mask method, and MgF with a thickness of 70nm is prepared by electron beam evaporation2(magnesium fluoride) antireflection film, thereby obtaining a transparent conductive film comprising a transparent conductive film, a silver grid electrode and MgF2The first external electrode structure 2014 of the anti-reflective film. Since the top cell 201 is on the light receiving side, it passes through the MgF2The antireflection film can effectively reduce the light reflection on the surface of the battery and improve the photoelectric conversion efficiency of the battery.
In the embodiment of the present invention, the bottom cell unit 203 further includes a second external electrode structure 2031, specifically, a transparent conductive film with a thickness of 110nm is deposited on one side of the back surface field 2032 away from the monocrystalline silicon substrate 2033 by magnetron sputtering, and a silver grid line electrode with a thickness of 200nm is evaporated on the transparent conductive film by a mask method, so as to obtain the second external electrode structure 2031 including the transparent conductive film and the silver grid line electrode.
In the embodiment of the present invention, the stacked cell 30 may also be prepared by the above method, and only the preparation sequence of different functional layers needs to be adjusted correspondingly according to the structural pair of the stacked cell 30, so that the repetition is avoided, and no further description is given here.
The invention is further illustrated with reference to the following specific examples:
examples
And polishing, texturing and cleaning a commercial-grade M2 silicon wafer with the thickness of 180 mu M and the resistivity of 5 omega-cm by using an alkaline solution to obtain the monocrystalline silicon substrate containing the pyramid textured surface.
A10 nm intrinsic amorphous silicon passivation layer is deposited on one side of a monocrystalline silicon substrate through PECVD (Plasma Enhanced Chemical Vapor Deposition), and a boron-doped p-type amorphous silicon layer with the thickness of 15nm is deposited on the intrinsic amorphous silicon passivation layer through hydrogen diluted diborane and silane mixed gas to obtain a back surface field.
And depositing a 10nm intrinsic amorphous silicon passivation layer on the other side of the monocrystalline silicon substrate through PECVD, and depositing a 10nm n-type amorphous silicon layer on the intrinsic amorphous silicon passivation layer through phosphine and silane mixed gas diluted by hydrogen to obtain the emitter.
And preparing a 5nm heavily-doped n-type microcrystalline silicon layer on the emitter by mixing a mixed gas with 250 flow ratio of hydrogen to silane and phosphane.
Preparing a 10nm ITO film layer serving as a transparent conducting layer by adopting an ITO target through magnetron sputtering equipment, wherein the sputtering power density is 1.5W/cm2The flow ratio of oxygen to argon was 2%, and the bombardment damage to the amorphous silicon layer was reduced by low power density.
And preparing a heavily-doped p-type microcrystalline silicon layer as a heavily-doped p-type silicon layer on the transparent conducting layer by using silane with a hydrogen dilution ratio (the flow ratio of hydrogen to silane is 250) and diborane mixed gas.
Preparing a Sprio-TTB hole transport layer with the thickness of 10nm on the heavily doped p-type silicon layer by adopting an evaporation method, wherein the evaporation rate is
Figure BDA0002644640700000103
Preparing a perovskite precursor layer on the hole transport layer by adopting a double-source co-evaporation method, specifically firstly adjusting the evaporation rate of cesium bromide
Figure BDA0002644640700000101
The evaporation rate of lead iodide is
Figure BDA0002644640700000102
Thereby depositing to obtain a mixed layer of lead iodide and cesium bromide with the thickness of 400nm, and dripping 90uL of FAI (formamidine hydroiodide) and FABr (formamidine hydrobromide) solution (the molar concentration ratio of FAI to FABr is 3:1) on PbI2The perovskite precursor is obtained by immediately spin-coating on the mixed layer of lead iodide and CsBrAnd annealing the layer at 150 ℃ for 30min to form a perovskite absorption layer.
Firstly, vacuum coating equipment is adopted on the perovskite absorption layer
Figure BDA0002644640700000111
Evaporating C60 with the thickness of 10nm at the evaporation rate, and preparing SnO with the thickness of 10nm by using atomic layer deposition equipment2An electron transport layer is obtained.
Depositing a transparent conductive film with the thickness of 110nm on one side of the electron transmission layer far away from the perovskite absorption layer through magnetron sputtering, evaporating a silver grid line electrode with the thickness of 200nm on the transparent conductive film through a mask method, and preparing MgF with the thickness of 70nm through electron beam evaporation2(magnesium fluoride) antireflection film, thereby obtaining a transparent conductive film comprising a transparent conductive film, a silver grid electrode and MgF2And the first external electrode structure of the antireflection film. Since the top cell is on the light receiving side, it passes through the MgF2The antireflection film can effectively reduce the light reflection on the surface of the battery and improve the photoelectric conversion efficiency of the battery.
And depositing a transparent conductive film with the thickness of 110nm on the side of the back field far away from the monocrystalline silicon substrate by magnetron sputtering, and evaporating a silver grid line electrode with the thickness of 200nm on the transparent conductive film by a mask method, thereby obtaining a second external electrode structure comprising the transparent conductive film and the silver grid line electrode.
Comparative example
And polishing, texturing and cleaning a commercial-grade M2 silicon wafer with the thickness of 180 mu M and the resistivity of 5 omega-cm by using an alkaline solution to obtain the monocrystalline silicon substrate containing the pyramid textured surface.
A10 nm intrinsic amorphous silicon passivation layer is deposited on one side of a monocrystalline silicon substrate through PECVD (Plasma Enhanced Chemical Vapor Deposition), and a boron-doped p-type amorphous silicon layer with the thickness of 15nm is deposited on the intrinsic amorphous silicon passivation layer through hydrogen diluted diborane and silane mixed gas to obtain a back surface field.
And depositing a 10nm intrinsic amorphous silicon passivation layer on the other side of the monocrystalline silicon substrate through PECVD, and depositing a 10nm n-type amorphous silicon layer on the intrinsic amorphous silicon passivation layer through phosphine and silane mixed gas diluted by hydrogen to obtain the emitter.
And preparing a 5nm heavily-doped n-type microcrystalline silicon layer on the emitter by mixing a mixed gas with 250 flow ratio of hydrogen to silane and phosphane.
And preparing a heavily doped p-type microcrystalline silicon layer as a heavily doped p-type silicon layer on the heavily doped n-type microcrystalline silicon layer by using silane with a hydrogen dilution ratio (the flow ratio of hydrogen to silane is 250) and diborane mixed gas.
Preparing a Sprio-TTB hole transport layer with the thickness of 10nm on the heavily doped p-type silicon layer by adopting an evaporation method, wherein the evaporation rate is
Figure BDA0002644640700000121
Preparing a perovskite precursor layer on the hole transport layer by adopting a double-source co-evaporation method, specifically firstly adjusting the evaporation rate of cesium bromide
Figure BDA0002644640700000122
The evaporation rate of lead iodide is
Figure BDA0002644640700000123
Thereby depositing to obtain a mixed layer of lead iodide and cesium bromide with the thickness of 400nm, and dripping 90uL of FAI (formamidine hydroiodide) and FABr (formamidine hydrobromide) solution (the molar concentration ratio of FAI to FABr is 3:1) on PbI2And (3) immediately spin-coating the mixed layer of lead iodide and CsBr to obtain a perovskite precursor layer, and annealing at 150 ℃ for 30min to form a perovskite absorption layer.
Firstly, vacuum coating equipment is adopted on the perovskite absorption layer
Figure BDA0002644640700000124
Evaporating C60 with the thickness of 10nm at the evaporation rate, and preparing SnO with the thickness of 10nm by using atomic layer deposition equipment2An electron transport layer is obtained.
Depositing a transparent conductive film with the thickness of 110nm on one side of the electron transmission layer far away from the perovskite absorption layer by magnetron sputtering, evaporating a silver grid line electrode with the thickness of 200nm on the transparent conductive film by a mask method, and preparing the silver grid line electrode by electron beam evaporationPreparation of 70nm MgF2(magnesium fluoride) antireflection film, thereby obtaining a transparent conductive film comprising a transparent conductive film, a silver grid electrode and MgF2And the first external electrode structure of the antireflection film.
And depositing a transparent conductive film with the thickness of 110nm on the side of the back field far away from the monocrystalline silicon substrate by magnetron sputtering, and evaporating a silver grid line electrode with the thickness of 200nm on the transparent conductive film by a mask method, thereby obtaining a second external electrode structure comprising the transparent conductive film and the silver grid line electrode.
Performance testing
The laminate batteries prepared in examples and the laminate batteries prepared in comparative examples were tested for parameters such as conversion efficiency, open circuit voltage, short circuit current density, and fill factor, and the results are shown in table 1 below:
TABLE 1
Figure BDA0002644640700000125
As can be seen from table 1 above, compared with the stacked cell prepared by the comparative example, the stacked cell prepared by the embodiment of the present invention improves the exchange recombination capability of the photon-generated carrier, enhances the photon-generated carrier collection capability of the stacked cell, and reduces the photon-generated carrier photoelectric loss caused by tunneling junction and the probability of top cell short circuit. As shown in table 1 above, the open-circuit voltage and the fill factor of the stacked cell prepared in the embodiment of the present invention are significantly improved, where the open-circuit voltage is up to 1.7V or more, the fill factor is improved by 2% or more, the cell efficiency is improved from 23.49% to 25.12%, and the conversion efficiency of the cell is significantly improved.
It should be noted that, for simplicity of description, the method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the embodiments are not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the embodiments. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no particular act is required to implement the embodiments of the application.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (10)

1. The middle series layer of the laminated cell is characterized in that the middle series layer is of a tunneling junction structure and comprises a heavily doped n-type silicon layer, a heavily doped p-type silicon layer and a transparent conducting layer positioned between the heavily doped n-type silicon layer and the heavily doped p-type silicon layer;
the doping concentration of the heavily doped n-type silicon layer and the heavily doped p-type silicon layer are both 1018cm-3The above;
the heavily doped n-type silicon layer is a heavily doped n-type amorphous silicon layer, a heavily doped n-type microcrystalline silicon layer or a heavily doped n-type nanocrystalline silicon layer;
the heavily doped p-type silicon layer is a heavily doped p-type amorphous silicon layer, a heavily doped p-type microcrystalline silicon layer or a heavily doped p-type nanocrystalline silicon layer.
2. The intermediate series layer of claim 1 wherein said heavily doped n-type siliconThe doping concentration of the layer is 1019～1020cm-3。
3. The intermediate series layer of claim 1 wherein the heavily doped p-type silicon layer has a doping concentration of 1018～1019cm-3。
4. The intermediate series layer of claim 1, wherein the heavily doped n-type silicon layer has a thickness of 1nm to 10 nm.
5. The intermediate series layer of claim 1, wherein the heavily doped p-type silicon layer has a thickness of 1nm to 10 nm.
6. The intermediate series layer of claim 1 wherein said transparent conductive layer is selected from any one of an indium tin oxide layer, a tungsten doped indium oxide layer, a titanium doped indium oxide layer and a hydrogen doped indium oxide layer.
7. The intermediate series layer according to claim 1, characterized in that the thickness of the transparent conductive layer is between 1nm and 20 nm.
8. A laminated battery comprising a top cell, a bottom cell, and an intermediate series layer according to any one of claims 1 to 7;
the intermediate series layer is located between the top cell unit and the bottom cell unit.
9. The laminate battery as claimed in claim 8, wherein the top cell is a perovskite cell and the bottom cell is a crystalline silicon cell.
10. A photovoltaic module comprising a laminate cell according to any of claims 8 to 9.
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