CN111988002A - Digital predistortion method, device, equipment and storage medium for MIMO power amplifier - Google Patents
Digital predistortion method, device, equipment and storage medium for MIMO power amplifier Download PDFInfo
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Abstract
The embodiment of the invention discloses a digital predistortion method, a device, equipment and a storage medium for an MIMO power amplifier, relating to the technical field of wireless communication and relieving the digital predistortion to solve the contradiction between the efficiency and the linearity of a power amplifier. The invention comprises the following steps: respectively inputting the digital baseband input signals of each sub-channel into corresponding digital predistorters, and acquiring predistortion output signals output by each digital predistorter; further obtaining a coupled sub-channel signal; injecting the obtained coupled sub-channel signals into a power amplifier for amplification, inputting the amplified signals into an attenuation coupler, and sequentially filtering and demodulating the coupled signals output by the attenuation coupler to obtain digital baseband output signals of each sub-channel; and inputting the digital baseband input signals and the digital baseband output signals of each sub-channel into a predistortion training module for training and then updating the parameters of each digital predistorter. The invention is suitable for digital predistortion of the MIMO power amplifier.
Description
Technical Field
The invention relates to the technical field of wireless communication, in particular to a digital predistortion technical direction of an MIMO power amplifier, and particularly relates to a digital predistortion method, a device, equipment and a storage medium for the MIMO power amplifier.
Background
With the rapid development of scientific technology and the continuous improvement of communication demand of people, a high-speed and large-capacity communication system becomes a necessary trend of the development of modern mobile communication technology. MIMO (Multiple Input Multiple Output) can effectively improve the spectrum utilization of a wireless system, and is one of the key technologies of modern mobile communication. Among them, the design and research of the power amplifier as a core device in the transmitter has been a hot spot in the microwave field.
In order to improve the transmission efficiency of the power amplifier, the power amplifier needs to operate in a saturation region. However, the Power amplifier has strong non-linear characteristics and memory effect, and when the Power amplifier inputs a signal with a non-constant envelope, the output signal of the Power amplifier may generate severe non-linear distortion due to a wide signal bandwidth and a high PAPR (Peak to Average Power Ratio). The nonlinear distortion is embodied as out-of-band spectrum expansion, high-order intermodulation generated by the nonlinear characteristic of a power amplifier falls in the range of an adjacent band to influence the communication quality of an adjacent channel, and the nonlinear distortion is embodied as in-band bit error rate increase and strong intersymbol interference is introduced during signal transmission to generate in-band distortion.
This problem is reflected in MIMO systems, where inter-channel crosstalk may be introduced due to the close distance between the rf channels, and when such crosstalk passes through the power amplifier, new nonlinear distortion may be generated.
Disclosure of Invention
Embodiments of the present invention provide a digital predistortion method, apparatus, device and storage medium for MIMO power amplifier, which can mitigate the contradiction between the efficiency and linearity of a power amplifier by a digital predistortion technique.
In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:
in a first aspect, an embodiment of the present application provides a digital predistortion method for a MIMO power amplifier, including:
step one, inputting digital baseband input signals of each subchannel into corresponding digital predistorters respectively, and acquiring predistortion output signals output by each digital predistorter;
step two, after carrying out digital-to-analog conversion on the acquired predistortion output signals, respectively inputting the predistortion output signals into corresponding low-pass filters, and coupling the signals output by each modulator to obtain coupled sub-channel signals, wherein each low-pass filter is connected with one modulator;
step three, injecting the obtained coupled sub-channel signals into a power amplifier for amplification, inputting the amplified signals into an attenuation coupler, and filtering and demodulating the coupled signals output by the attenuation coupler in sequence to obtain digital baseband output signals of each sub-channel;
and step four, inputting the digital baseband input signals and the digital baseband output signals of each sub-channel into a predistortion training module, and then updating the parameters of each digital predistorter through the parameter results obtained by training.
Specifically, for each subchannel, inputting a digital baseband input signal of a subchannel n into an nth digital predistorter, wherein k is more than or equal to n and is more than or equal to 1, k is 2, and n and k are positive integers; and the nth digital predistorter obtains an nth predistortion output signal by using the digital baseband input signal of the subchannel n through the loaded predistortion model, and the nth predistortion output signal is used as the output signal of the nth digital predistorter.
The second step comprises the following steps: carrying out digital-to-analog conversion on the nth predistortion output signal through an nth digital-to-analog converter, and respectively passing the converted signal through an nth low-pass filter and an nth modulator; and coupling signals output by the first modulator to the k-th modulator with each other and introducing nonlinear crosstalk.
The third step comprises the following steps: amplifying the coupled signal of the subchannel n through an nth power amplifier, and inputting the amplified signal into an nth attenuation coupler; the coupled signal output by the nth attenuation coupler is filtered by an nth band-pass filter, and the signal output by the nth band-pass filter is demodulated by an nth demodulator; the signal output by the nth demodulator is filtered by an n + k bandpass filter; and performing analog-to-digital conversion on the signal output by the (n + k) th band-pass filter through an n analog-to-digital converter to obtain a digital baseband output signal of the subchannel n.
And loading a predistortion model of the SOMP-PHEC in the first to k-th digital predistorters. The predistortion training is to train model parameters of the first to k-th digital predistorters by utilizing an SOMP (sequence-on-demand) compressive sensing algorithm to obtain normalized mean square errors of digital baseband input signals and digital baseband output signals under different sparsity degrees; and obtaining model parameters of the trained first to k-th digital predistorters under the optimal sparsity by utilizing the normalized mean square error.
The 2 × 2MIMO predistortion model of the SOMP-PHEC loaded in the first to k-th digital predistorters comprises:
wherein x is1Denotes the subchannel 1, x2Denotes the subchannel 2, x1(n) and x2(n) digital baseband input signals for subchannel 1 and subchannel 2, respectively, y (n) digital baseband output signals for subchannel n, P and M are the non-linear order and memory depth of the alignment term, respectively, P1And M1The non-linear order and the memory depth, M, of the memory time envelope power series and the product term of the input signal at the current time2For memory depth of memory cross terms, m1≠m2，h1,p,q,m、h2,p,q,m、h3,p,q,m、h4,p,q,m、
And
each representing 6 different model coefficients.
In a second aspect, an embodiment of the present application provides a digital predistortion apparatus for a MIMO power amplifier, including:
the predistortion module is used for respectively inputting the digital baseband input signals of each subchannel into the corresponding digital predistorters and acquiring predistortion output signals output by each digital predistorter;
the signal coupling module is used for performing digital-to-analog conversion on the acquired predistortion output signals, then respectively inputting the predistortion output signals into corresponding low-pass filters, and coupling the signals output by each modulator to obtain coupled sub-channel signals, wherein each low-pass filter is connected with one modulator;
the signal processing module is used for respectively injecting the obtained coupled subchannel signals into a power amplifier for amplification, inputting the amplified signals into the attenuation couplers, and sequentially filtering and demodulating the coupled signals output by the attenuation couplers to obtain digital baseband output signals of each subchannel;
and the feedback updating module is used for inputting the digital baseband input signals and the digital baseband output signals of all the sub-channels into the predistortion training module, and then updating the parameters of all the digital predistorters according to parameter results obtained by training.
In a third aspect, an embodiment of the present application provides a digital predistortion device for a MIMO power amplifier, where the digital predistortion device at least includes a processor and a memory, where the memory stores a computer execution instruction, and the processor executes the computer execution instruction stored in the memory, so that the communication key exchange device executes the method flow in the foregoing embodiment.
In a fourth aspect, the present application provides a storage medium storing a computer program or instructions, and when the computer program or instructions are executed, the method flow in the foregoing embodiments is implemented.
According to the digital predistortion method, device, equipment and storage medium for the MIMO power amplifier, provided by the embodiment of the invention, on one hand, a PHEC (Parallel Hammerstein-Envelope memory polynomial-memory Cross term) model is provided to remarkably improve the modeling precision of an MP model, and on the other hand, the complexity of the PHEC model is reduced through an SOMP (subspace orthogonal Matching Pursuit) compressed sensing algorithm, and the operation resources consumed when a 2 x 2MIMO power amplifier digital predistortion system is realized are reduced. Compared with the prior art, the power amplifier modeling precision of the 2 x 2MIMO system is obviously improved by the PHEC power amplifier digital predistortion model; and the complexity of the PHEC model is reduced through the SOMP algorithm, so that the operation resources consumed when the model is realized on an FPGA (Field Programmable Gate Array) are reduced. Therefore, the contradiction between the efficiency and the linearity of the power amplifier solved by the digital predistortion technology is effectively relieved.
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In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a diagram of a digital predistortion apparatus in an embodiment of the present invention;
FIG. 2 is a graph of a learning curve of the SOMP compressive sensing algorithm according to the embodiment of the present invention;
fig. 3 is a comparison graph of power spectra of two sub-channels before and after pre-distortion in the embodiment of the present invention, where fig. 3(a) is a comparison graph of power spectra of sub-channel 1, and fig. 3(b) is a comparison graph of power spectra of sub-channel 2.
Detailed Description
In order to make the technical solutions of the present invention better understood, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention. As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or coupled. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The embodiment of the invention provides a digital predistortion method for an MIMO power amplifier, which comprises the following steps:
step one, inputting the digital baseband input signals of each sub-channel into corresponding digital predistorters respectively, and acquiring predistortion output signals output by each digital predistorter.
And step two, after the acquired predistortion output signals are subjected to digital-to-analog conversion, the predistortion output signals are respectively input into corresponding low-pass filters, and signals output by all the modulators are coupled to obtain coupled sub-channel signals, wherein each low-pass filter is connected with one modulator.
And step three, injecting the obtained coupled sub-channel signals into a power amplifier for amplification, inputting the amplified signals into an attenuation coupler, and filtering and demodulating the coupled signals output by the attenuation coupler in sequence to obtain digital baseband output signals of each sub-channel.
And step four, inputting the digital baseband input signals and the digital baseband output signals of each sub-channel into a predistortion training module, and then updating the parameters of each digital predistorter through the parameter results obtained by training.
In this embodiment, the first step includes: for each subchannel, the digital baseband input signal for subchannel n is input to an nth digital predistorter. And the nth digital predistorter obtains an nth predistortion output signal by using the digital baseband input signal of the subchannel n through the loaded predistortion model, and the nth predistortion output signal is used as the output signal of the nth digital predistorter, wherein k is more than or equal to n and is more than or equal to 1, k is 2, and n and k are positive integers.
For example: as shown in fig. 1, S1: the first digital predistorter comprises a predistortion model based on SOMP-PHEC, and a digital baseband input signal x of a subchannel 11(n) inputting into a first digital predistorter which combines its own model parameters with the digital baseband input signal x for subchannel 11(n) input into its own predistortion model, which outputs a first predistortion output signal x1-pre(n), the first predistorted output signal x1-pre(n) also as the output signal of the first digital predistorter; the second digital predistorter comprises a predistortion model based on SOMP-PHEC, a digital baseband input signal x of a sub-channel 22(n) inputting a second digital predistorter which combines its own model parameters with the digital baseband input signal x for subchannel 22(n) input into its own predistortion model, which outputs a second predistortion output signal x2-pre(n), second predistorted output signal x2-pre(n)Also as the output signal of the second digital predistorter.
In this embodiment, the second step includes: and D/A conversion is carried out on the nth predistortion output signal through an nth D/A converter, and the converted signal respectively passes through an nth low-pass filter and an nth modulator. And coupling signals output by the first modulator to the k-th modulator with each other and introducing nonlinear crosstalk.
For example: as shown in fig. 1, S2: first predistortion output signal x1-pre(n) performing digital-to-analog conversion by using a first digital-to-analog converter, wherein the converted signals respectively pass through a first low-pass filter and a first modulator; second predistorted output signal x2-pre(n) performing digital-to-analog conversion by a second digital-to-analog converter, wherein the converted signals respectively pass through a second low-pass filter and a second modulator; s3: the signal output by the first modulator is coupled with the signal output by the second modulator to introduce nonlinear crosstalk.
Further, the third step includes:
and amplifying the coupled signal of the subchannel n through an nth power amplifier, and inputting the amplified signal into an nth attenuation coupler. And the coupled signal output by the nth attenuation coupler is filtered by an nth band-pass filter, and the signal output by the nth band-pass filter is demodulated by an nth demodulator. The signal output by the nth demodulator is filtered by an n + k bandpass filter; and performing analog-to-digital conversion on the signal output by the (n + k) th band-pass filter through an n analog-to-digital converter to obtain a digital baseband output signal of the subchannel n.
For example: as shown in fig. 1, S4: amplifying the coupled sub-channel 1 signal through a first power amplifier; amplifying the coupled signals of the sub-channel 2 through a second power amplifier; s5: the signal amplified by the first power amplifier is input into a first attenuation coupler; the signal amplified by the second power amplifier is input into a second attenuation coupler; s6: the coupled signal output by the first attenuation coupler is filtered by a first band-pass filter; the coupled signal output by the second attenuation coupler is filtered by a second band-pass filter; s7: signal output from the first band-pass filterDemodulating by a first demodulator; the signal output by the second band-pass filter is demodulated by a second demodulator; s8: filtering the signal output by the first demodulator through a third band-pass filter; the signal output by the second demodulator is filtered by a fourth band-pass filter; s9: the signal output by the third band-pass filter is subjected to analog-to-digital conversion by the first analog-to-digital converter to obtain a digital baseband output signal y of the subchannel 11(n); the signal output by the fourth band-pass filter is subjected to analog-to-digital conversion by the second analog-to-digital converter to obtain a digital baseband output signal y of the subchannel 22(n); s10: digital baseband input signal x for subchannel 11(n), digital baseband input signal x for subchannel 22(n), digital baseband output signal y of subchannel 11(n) and the digital baseband output signal y of subchannel 22And (n) the model parameters of the first digital predistorter and the model parameters of the second predistorter are input into a predistortion training module, the predistortion training module trains the model parameters of the first digital predistorter and the model parameters of the second predistorter, the trained model parameters of the first digital predistorter are copied to the first digital predistorter, and the trained model parameters of the second predistorter are copied to the second digital predistorter.
In a preferred embodiment of this embodiment, a predistortion model of SOMP-PHEC is loaded in the first to k-th digital predistorters.
The method specifically comprises the following steps: and in the predistortion training, the module trains the model parameters of the first to k-th digital predistorters by using an SOMP compressive sensing algorithm to obtain the normalized mean square error of the digital baseband input signal and the digital baseband output signal under different sparsity degrees. And obtaining model parameters of the trained first to k-th digital predistorters under the optimal sparsity by utilizing the normalized mean square error.
For example: as shown in fig. 1, in step S10, the predistortion training module trains the model parameters of the first digital predistorter and the model parameters of the second digital predistorter by using an SOMP (subspace orthogonal matching pursuit) compressive sensing algorithm, calculates normalized mean square errors of the digital baseband input signal and the digital baseband output signal at different sparsity, and obtains the model parameters of the trained first digital predistorter and the trained second digital predistorter at the optimal sparsity by comprehensively considering modeling accuracy and model complexity.
The 2 × 2MIMO predistortion models of the SOMP-PHEC are loaded in the first to k-th digital predistorters, for example, in the step S10, the predistortion training module includes a 2 × 2MIMO predistortion model based on the SOMP-PHEC, and the 2 × 2MIMO predistortion model based on the SOMP-PHEC in the subchannel is represented by the following formula (1):
wherein x is1Denotes the subchannel 1, x2Denotes the subchannel 2, x1(n) and x2(n) digital baseband input signals for subchannel 1 and subchannel 2, respectively, y (n) digital baseband output signals for subchannel n, P and M are the non-linear order and memory depth of the alignment term, respectively, P1And M1The non-linear order and the memory depth, M, of the memory time envelope power series and the product term of the input signal at the current time2For memory depth of memory cross terms, m1≠m2，h1,p,q,m、h2,p,q,m、h3,p,q,m、h4,p,q,m、
And
the model coefficients are respectively 6 different models, and it should be noted that the value ranges of the parameters in the above formula may be determined according to specific application scenarios.
Note that the lower case letters p, q, m1And m2Represented, each represents an accumulation variable in the accumulation process, where P corresponds to the accumulation plus the limit P or P1Q is cumulative plus a limit of P-P +1 or P1-p +1, M for accumulation plus a limit of M or M1，m1、m2The corresponding accumulation upper limits are all M2. p andq represents a positive integer and x1(n) or x2(n) order of magnitude.
It should be noted that equation (1) is written in a vector form of z ═ Ua, where z is the digital baseband output signal, U is a matrix with respect to the digital baseband input signal x (n), and a is a model coefficient. And comprehensively considering modeling precision and model complexity, and finding out the optimal sparsity in the interval of [5,45] by adopting an SOMP compressed sensing algorithm. The specific method comprises the following steps:
1) inputting an algorithm: the measurement matrix U, the measurement vector z, the number of iterations time is from 5 to 45.
2) Initializing variables: coefficient matrix
Support set
Atomic index
Residual r0Z, current iteration number t 1, current test matrix U0Constant matrix Uc＝U。
3) Computing
Find the maximum index position.
4) Updating the support set and the atomic index: t ist＝Tt-1∪Ut-1(position)，indext＝indext-1U position and entering into sub SP algorithm.
5) Updating: replacing the supporting set and the atomic index Tt＝Tsp，indext＝indexsp，s＝(Tt TTt)-1Tt Tz，Ut＝Uc，Ut(indext) Update residual r as 0t＝z-Tts＝z-Tt(Tt TTt)-1Tt Tz。
6) Updating the iteration times: and t is t +1, when t is less than or equal to time, the step 3-5 is repeatedly executed, and when t is more than time, the iteration is terminated.
7) And (3) outputting an algorithm: model coefficient s, support atomic index in set.
The sub SP algorithm:
1) inputting an algorithm: inputting a measurement vector z and a support set T by an outer algorithmtAtomic indextThe iteration number t of the current outer layer algorithm and the current test matrix U ═ Ut-1。
2) Initializing variables: initial support set T of sub SP algorithm0＝TtThe maximum iteration number I equals t, the current iteration number I equals 1, and the initial residual r0＝z-T0s＝z-T0(T0 TT0)-1T0 Tz, initial atom index0＝indext。
3) Finding I optimal atoms: u-abs (U)Tri-1) Selecting I maximum values in u to obtain indextemp。
4) Updating the total support set and the total atom index: t isi＝Ti-1∪U(indextemp)，indexi＝indexi-1∪indextemp。
5) Backtracking and updating: calculating x ═ Ti TTi)-1Ti Tz, selecting I maximum values from x to obtain indexspUpdating the support set Ti＝Ti(indexsp) Update indexi＝indexi(indexsp) Update U (index)i)＝0。
6) And (3) residual error updating: s ═ T (T)i TTi)-1Ti Tz，ri＝z-Tis＝z-Ti(Ti TTi)-1Ti Tz。
7) And (3) iterative updating: and I is equal to I +1, and when I is less than or equal to I, the steps 3-6 are repeatedly executed. When I > I or | | | ri||2When equal to 0, the iteration is terminated, let Tsp＝Ti，indexsp＝indexiWhen | | | ri||2＞||ri-1||2Then, the iteration is terminated, let Tsp＝Ti-1And indexsp＝indexi-1。
8) And (3) outputting an algorithm: outputting new supporting set TspAnd a corresponding new atomic indexspTo the outer layer algorithm.
And comprehensively considering modeling precision and model complexity, finding the optimal sparsity in the [5,45] interval, reconstructing a test vector z, namely Ua, namely U (index) s, and determining the number of model parameters as the optimal sparsity at the moment.
In a preferred scheme of this embodiment, a value range of sparsity of the SOMP compressive sensing algorithm is [5,45 ]. For example, the establishing process of the 2 × 2MIMO predistortion model based on the SOMP-PHEC includes the following steps:
1) obtaining a digital baseband input signal x for subchannel 11(n), digital baseband input signal x for subchannel 22(n), digital baseband output signal y of subchannel 11(n) and the digital baseband output signal y of subchannel 22(n) carrying out normalization treatment;
2) the model parameters were selected according to the following ranges: p is less than or equal to 5, M is less than or equal to 3, P1≤3,M1≤2,M2≤2；
3) According to the nonlinear order P and the memory depth M of the model alignment term, the nonlinear order P of the memory moment envelope power series and the current moment input signal product term1And memory depth M1Memory depth M of memory cross term2In the range of sparsity [5,45]]Searching is carried out, each searching utilizes the SOMP compressed sensing algorithm to input the signal x according to the digital baseband of the subchannel 11(n), digital baseband input signal x for subchannel 22(n), digital baseband output signal y of subchannel 11(n) and the digital baseband output signal y of subchannel 22(n) training the model parameters of the first digital predistorter and the model parameters of the second digital predistorter, and calculating the normalized mean square error of the digital baseband input signal and the digital baseband output signal under different sparsity degreesAnd comprehensively considering the modeling precision and the model complexity to obtain model parameters of the trained first digital predistorter and model parameters of the trained second digital predistorter under the optimal sparsity.
This embodiment still provides a digital predistortion device for MIMO power amplifier, its characterized in that includes:
and the predistortion module is used for respectively inputting the digital baseband input signals of each subchannel into the corresponding digital predistorters and acquiring predistortion output signals output by each digital predistorter.
And the signal coupling module is used for performing digital-to-analog conversion on the acquired predistortion output signals, then respectively inputting the predistortion output signals into corresponding low-pass filters, and coupling the signals output by each modulator to obtain coupled sub-channel signals, wherein each low-pass filter is connected with one modulator.
And the signal processing module is used for respectively injecting the obtained coupled subchannel signals into the power amplifier for amplification, then inputting the amplified signals into the attenuation couplers, and then sequentially filtering and demodulating the coupled signals output by the attenuation couplers to obtain the digital baseband output signals of each subchannel.
And the feedback updating module is used for inputting the digital baseband input signals and the digital baseband output signals of all the sub-channels into the predistortion training module, and then updating the parameters of all the digital predistorters according to parameter results obtained by training.
Specifically, the predistortion module includes:
a first digital predistorter comprising a SOMP-PHEC based predistortion model, the first digital predistorter for inputting a digital baseband input signal of subchannel 1 to the SOMP-PHEC based predistortion model and outputting a first predistorted output signal.
A second digital predistorter also comprising the SOMP-PHEC based predistortion model, the second digital predistorter for inputting the digital baseband input signal of subchannel 2 to the SOMP-PHEC based predistortion model and outputting a second predistorted output signal.
The signal coupling module comprises:
and the first digital-to-analog converter is used for performing digital-to-analog conversion on the first predistortion output signal and inputting the converted signal into the first low-pass filter for filtering.
And the second digital-to-analog converter is used for performing digital-to-analog conversion on the second predistortion output signal and inputting the converted signal into a second low-pass filter for filtering.
The first low-pass filter is used for filtering the signal output by the first digital-to-analog converter.
And the second low-pass filter is used for filtering the signal output by the second digital-to-analog converter.
The first modulator is used for modulating the signal output by the first low-pass filter.
And the second modulator is used for modulating the signal output by the second low-pass filter.
And the sub-channel coupling unit is used for coupling the signal output by the first modulator and the signal output by the second modulator to each other to introduce nonlinear crosstalk.
The signal processing module comprises:
and the first power amplifier is used for amplifying the coupled sub-channel 1 signals and inputting the signals into the first attenuation coupler.
And the second power amplifier is used for amplifying the coupled sub-channel 2 signal and inputting the amplified signal into the second attenuation coupler.
A first band pass filter for filtering the coupled signal output by the first attenuating coupler.
And the second band-pass filter is used for filtering the coupling signal output by the second attenuation coupler.
A first demodulator for demodulating the signal output by the first band-pass filter.
And the second demodulator is used for demodulating the signal output by the second band-pass filter.
And the third band-pass filter is used for filtering the signal output by the first demodulator.
A fourth band-pass filter for filtering the signal output by the second demodulator.
And the first analog-to-digital converter is used for performing analog-to-digital conversion on the signal output by the third band-pass filter and obtaining a digital baseband output signal of the subchannel 1.
And the second analog-to-digital converter is used for performing analog-to-digital conversion on the signal output by the fourth band-pass filter and obtaining a digital baseband output signal of the subchannel 2.
The feedback update module includes:
a predistortion training module, configured to train model parameters of the first digital predistorter and model parameters of the second digital predistorter according to the digital baseband input signal of the subchannel 1, the digital baseband input signal of the subchannel 2, the digital baseband output signal of the subchannel 1, and the digital baseband output signal of the subchannel 2, copy the trained model parameters of the first digital predistorter to the first digital predistorter, and copy the trained model parameters of the second digital predistorter to the second digital predistorter.
For example, as shown in fig. 1, the first digital predistorter: the first digital predistorter comprises a predistortion model based on SOMP-PHEC, and a digital baseband input signal x of a subchannel 11(n) inputting into a first digital predistorter which combines its own model parameters with the digital baseband input signal x for subchannel 11(n) input into its own predistortion model, which outputs a first predistortion output signal x1-pre(n), the first predistorted output signal x1-pre(n) also as the output signal of the first digital predistorter; a second digital predistorter: the second digital predistorter comprises a predistortion model based on SOMP-PHEC, a digital baseband input signal x of a sub-channel 22(n) inputting a second digital predistorter, and enabling the second digital predistorter to use model parameters and sub-channels of the second digital predistorterDigital baseband input signal x for channel 22(n) input into its own predistortion model, which outputs a second predistortion output signal x2-pre(n), second predistorted output signal x2-pre(n) also as the output signal of the second digital predistorter.
A first digital-to-analog converter: first predistortion output signal x1-pre(n) performing digital-to-analog conversion through a first digital-to-analog converter, and inputting the converted signal into a first low-pass filter for filtering; a second digital-to-analog converter: second predistorted output signal x2-preAnd (n) performing digital-to-analog conversion through a second digital-to-analog converter, and inputting the converted signal into a second low-pass filter for filtering.
A first low-pass filter: filtering the signal output by the first digital-to-analog converter; a second low-pass filter: and filtering the signal output by the second digital-to-analog converter.
A first modulator: the signal output by the first low-pass filter is modulated by a first modulator; a second modulator: the signal output by the second low-pass filter is modulated by a second modulator.
Sub-channel coupling: the signal output by the first modulator is coupled with the signal output by the second modulator to introduce nonlinear crosstalk.
A first power amplifier: amplifying the coupled sub-channel 1 signal through a first power amplifier; a second power amplifier: the coupled subchannel 2 signals are amplified by a second power amplifier.
First attenuating coupler: the signal amplified by the first power amplifier is input into a first attenuation coupler; a second attenuating coupler: the signal amplified by the second power amplifier is input into the second attenuation coupler.
A first band-pass filter: the coupled signal output by the first attenuation coupler is filtered by a first band-pass filter; a second band-pass filter: the coupled signal output by the second attenuating coupler is filtered by a second band-pass filter.
A first demodulator: the signal output by the first band-pass filter is demodulated by a first demodulator; a second demodulator: the signal output by the second band-pass filter is demodulated by a second demodulator.
A third band-pass filter: filtering the signal output by the first demodulator through a third band-pass filter; fourth bandpass filter: the signal output by the second demodulator is filtered by a fourth band-pass filter.
A first analog-to-digital converter: the signal output by the third band-pass filter is subjected to analog-to-digital conversion by the first analog-to-digital converter to obtain a digital baseband output signal y of the subchannel 11(n); a second analog-to-digital converter: the signal output by the fourth band-pass filter is subjected to analog-to-digital conversion by the second analog-to-digital converter to obtain a digital baseband output signal y of the subchannel 22(n)。
A predistortion training module: digital baseband input signal x for subchannel 11(n), digital baseband input signal x for subchannel 22(n), digital baseband output signal y of subchannel 11(n) and the digital baseband output signal y of subchannel 22And (n) the model parameters of the first digital predistorter and the model parameters of the second digital predistorter are input into a predistortion training module, the predistortion training module trains the model parameters of the first digital predistorter and the model parameters of the second digital predistorter, the trained model parameters of the first digital predistorter are copied to the first digital predistorter, and the trained model parameters of the second predistorter are copied to the second digital predistorter.
Since an efficient digital predistortion scheme requires a suitable power amplifier model. Most of the existing power amplifier models adopt Volterra series with memory. For a dual-channel or multi-channel communication system, new nonlinear distortion is caused by crosstalk between channels, an original single-channel power amplifier model needs to be improved, and a cross term capable of describing the nonlinear distortion is introduced to accurately describe the behavior of a power amplifier. The existing 2 x 2MIMO power amplifier model is mostly based on a simplified Volterra polynomial-Memory Polynomial (MP), and the model has good modeling precision and can improve the power leakage of adjacent channels of the power amplifier of each subchannel in the 2 x 2MIMO system. However, this model describes intermodulation distortion with fewer cross-terms between channels. Therefore, how to improve modeling accuracy and reduce model complexity is an important content of current research. Compared with a 2 x 2MP model, the PHEC model has more various cross terms and can represent the memory effect more flexibly and accurately. The SOMP compressed sensing algorithm is an OMP algorithm improved by an SP algorithm, and can perform sparse decomposition and accurate reconstruction on a matrix.
The design objective of this embodiment is to provide a PHEC (Parallel Hammerstein-Envelope memory polynomial-memory Cross term) model to significantly improve the modeling accuracy of the MP model, and reduce the complexity of the PHEC model and reduce the computation resources consumed in implementing a 2 × 2MIMO power amplifier digital predistortion system through an SOMP (subspace orthogonal Matching Pursuit) compressed sensing algorithm. Compared with the prior art, the embodiment has the following advantages: 1) the PHEC power amplifier digital predistortion model is provided, and the power amplifier modeling precision of a 2 x 2MIMO system is obviously improved. 2) By adopting the SOMP algorithm, the complexity of the PHEC model is reduced, and the operation resources consumed when the model is realized on an FPGA (Field Programmable Gate Array) are reduced.
The advantages of this embodiment are understood by specific examples: the baseband signals respectively select 20MHz single-tone OFDM signals and 20MHz double-tone OFDM signals as input signals of two channels, PAPR values are respectively 6.2dB and 7.2dB, and signal carrier frequency is set to be 3.6 GHz. And a directional coupler is adopted to simulate the coupling degree between the sub-channels to be-15 dB. And carrying out normalization processing after the input and output data of the power amplifier are synchronously acquired. The ACPR of the output of the power amplifier before predistortion is compared to the ACPR of the upper and lower sidebands of the two subchannels after passing through the 2 × 2MIMO predistortion model based on SOMP-PHEC as shown in table 1 and fig. 3 below:
TABLE 1
As can be seen from fig. 2, the SOMP compressive sensing algorithm approaches convergence when the sparsity is 25. In addition, by comparing the upper and lower sidebands ACPR of the signals before and after predistortion, the ACPR improvement effect of more than 23dB can be obtained when the model is used for modeling the power amplifier in a 2 x 2MIMO system. This effect is significantly better than the conventional MP model, and for the MP model employed in current 2 × 2MIMO predistortion:
compared with the model of the present embodiment in terms of performance. Firstly, in terms of the number of parameters: when an MP model is selected for modeling, when the memory depth is selected to be M, the nonlinear order of the model is P, and the number of model parameters at the moment is 2 x (M +1) x (1+ P) x P/2; when the 2 x 2MIMO predistortion model based on the SOMP-PHEC is selected, the number of model parameters can be obviously reduced by an SOMP compressed sensing algorithm, and the calculation resources consumed when the model is realized on an FPGA are reduced. Second, in terms of modeling accuracy of the model: for the MP model, only the cross terms of the alignment terms exist; in the SOMP-PHEC power amplifier model, a cross term between the signal envelope at the memory time and the current input signal and a cross product term between the signal envelope at the memory time and the input signal at the memory time are added, so that the strong memory effect of the broadband power amplifier can be more accurately described.
Therefore, the digital predistortion model of the PHEC power amplifier provided by the embodiment obviously improves the power amplifier modeling precision of a 2 x 2MIMO system, reduces the number of parameters in the PHEC model through an SOMP compressed sensing algorithm, reduces the operation resources consumed when the PHEC model is realized on an FPGA, and accelerates the calculation time of the optimal model parameters.
The present embodiment also provides a digital predistortion device for a MIMO power amplifier, where the digital predistortion device at least includes a processor and a memory, where the memory stores a computer execution instruction, and the processor executes the computer execution instruction stored in the memory, so that the communication key exchange device executes the method flow in the foregoing embodiments.
The present embodiment also provides a storage medium, which stores a computer program or instructions, and when the computer program or instructions are executed, the method flows in the above embodiments are implemented.
The steps of a method or algorithm described in connection with the disclosure herein may be embodied in hardware or in software instructions executed by a processor. The software instructions may be comprised of corresponding software modules that may be stored in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Erasable Programmable Read Only Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM), registers, a hard disk, a removable hard disk, a compact disc read only memory (CD-ROM), or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. Of course, the storage medium may also be integral to the processor. The processor and the storage medium may reside in an ASIC. Additionally, the ASIC may reside in a core network interface device. Of course, the processor and the storage medium may reside as discrete components in a core network interface device.
Those skilled in the art will recognize that in one or more of the examples described above, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.
The above-mentioned embodiments, objects, technical solutions and advantages of the present application are further described in detail, it should be understood that the above-mentioned embodiments are only examples of the present application, and are not intended to limit the scope of the present application, and any modifications, equivalent substitutions, improvements and the like made on the basis of the technical solutions of the present application should be included in the scope of the present application.
Claims (10)
1. A digital predistortion method for MIMO power amplifier is characterized by comprising the following steps:
step one, inputting digital baseband input signals of each subchannel into corresponding digital predistorters respectively, and acquiring predistortion output signals output by each digital predistorter;
step two, after carrying out digital-to-analog conversion on the acquired predistortion output signals, respectively inputting the predistortion output signals into corresponding low-pass filters, and coupling the signals output by each modulator to obtain coupled sub-channel signals, wherein each low-pass filter is connected with one modulator;
step three, injecting the obtained coupled sub-channel signals into a power amplifier for amplification, inputting the amplified signals into an attenuation coupler, and filtering and demodulating the coupled signals output by the attenuation coupler in sequence to obtain digital baseband output signals of each sub-channel;
and step four, inputting the digital baseband input signals and the digital baseband output signals of each sub-channel into a predistortion training module, and then updating the parameters of each digital predistorter through the parameter results obtained by training.
2. The method of claim 1, wherein the first step comprises:
inputting a digital baseband input signal of a subchannel n into an nth digital predistorter aiming at each subchannel, wherein k is more than or equal to n and is more than or equal to 1, k is 2, and n and k are positive integers;
and the nth digital predistorter obtains an nth predistortion output signal by using the digital baseband input signal of the subchannel n through the loaded predistortion model, and the nth predistortion output signal is used as the output signal of the nth digital predistorter.
3. The method according to claim 2, wherein the step two comprises:
carrying out digital-to-analog conversion on the nth predistortion output signal through an nth digital-to-analog converter, and respectively passing the converted signal through an nth low-pass filter and an nth modulator;
and coupling signals output by the first modulator to the k-th modulator with each other and introducing nonlinear crosstalk.
4. The method of claim 3, wherein the third step comprises:
amplifying the coupled signal of the subchannel n through an nth power amplifier, and inputting the amplified signal into an nth attenuation coupler;
the coupled signal output by the nth attenuation coupler is filtered by an nth band-pass filter, and the signal output by the nth band-pass filter is demodulated by an nth demodulator;
the signal output by the nth demodulator is filtered by an n + k bandpass filter;
and performing analog-to-digital conversion on the signal output by the (n + k) th band-pass filter through an n analog-to-digital converter to obtain a digital baseband output signal of the subchannel n.
5. The method as claimed in claim 2, characterized in that a predistortion model of SOMP-PHEC is loaded in the first to k-th digital predistorters.
6. The method of claim 5, further comprising:
the predistortion training is to train model parameters of the first to k-th digital predistorters by utilizing an SOMP (sequence-on-demand) compressive sensing algorithm to obtain normalized mean square errors of digital baseband input signals and digital baseband output signals under different sparsity degrees;
and obtaining model parameters of the trained first to k-th digital predistorters under the optimal sparsity by utilizing the normalized mean square error.
7. The method as claimed in claim 5, wherein the 2 x 2MIMO predistortion model loaded in the first to k-th digital predistorters is SOMP-PHEC, comprising:
wherein x is1Denotes the subchannel 1, x2Denotes the subchannel 2, x1(n) and x2(n) digital baseband input signals for subchannel 1 and subchannel 2, respectively, y (n) digital baseband output signals for subchannel n, P and M are the non-linear order and memory depth of the alignment term, respectively, P1And M1The non-linear order and the memory depth, M, of the memory time envelope power series and the product term of the input signal at the current time2For memory depth of memory cross terms, m1≠m2，h1,p,q,m、h2,p,q,m、h3,p,q,m、h4,p,q,m、
And
each representing 6 different model coefficients.
8. A digital predistortion device for MIMO power amplifier, characterized by that, comprising:
the predistortion module is used for respectively inputting the digital baseband input signals of each subchannel into the corresponding digital predistorters and acquiring predistortion output signals output by each digital predistorter;
the signal coupling module is used for performing digital-to-analog conversion on the acquired predistortion output signals, then respectively inputting the predistortion output signals into corresponding low-pass filters, and coupling the signals output by each modulator to obtain coupled sub-channel signals, wherein each low-pass filter is connected with one modulator;
the signal processing module is used for respectively injecting the obtained coupled subchannel signals into a power amplifier for amplification, inputting the amplified signals into the attenuation couplers, and sequentially filtering and demodulating the coupled signals output by the attenuation couplers to obtain digital baseband output signals of each subchannel;
and the feedback updating module is used for inputting the digital baseband input signals and the digital baseband output signals of all the sub-channels into the predistortion training module, and then updating the parameters of all the digital predistorters according to parameter results obtained by training.
9. A digital predistortion device for a MIMO power amplifier, characterized in that the digital predistortion device comprises at least a processor and a memory, the memory storing computer executable instructions, the processor executing the computer executable instructions stored by the memory, causing the communication key exchange device to perform the method of any of claims 1 to 7.
10. A storage medium, storing a computer program or instructions which, when executed, implement the method of any one of claims 1 to 7.
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