CN111953991A - Video CPU + GPU hardware decoding acceleration system and method based on window platform - Google Patents
Video CPU + GPU hardware decoding acceleration system and method based on window platform Download PDFInfo
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/436—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
- H04N19/156—Availability of hardware or computational resources, e.g. encoding based on power-saving criteria
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/44—Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
Abstract
A video CPU + GPU hardware decoding acceleration system and method based on a window platform relates to the technical field of video processing, and comprises the following steps: the video data are processed in parallel through the GPU and the CPU, the video data stored in the storage module are read through the allocation module, the video decoder data are selected, the working instructions are respectively sent to the first decoding module and the second decoding module, the working modes of the first decoding module and the second decoding module are allocated to decode the video data, and the problem that the video watching experience is reduced due to the fact that the video is easy to block in the existing video playing process is solved.
Description
Technical Field
The invention relates to the technical field of video processing, in particular to a system and a method for accelerating decoding of video CPU + GPU hardware based on a window platform.
Background
Video is a continuous sequence of images, consisting of successive frames, a frame being an image. Because of the persistence of vision effect of human eyes, when a frame sequence is played at a certain speed, a video with continuous action is seen, because the similarity between continuous frames is extremely high, in order to facilitate storage and transmission, an original video needs to be coded and compressed to remove redundancy of space and time dimensions, and the data bandwidth is reduced to 1-10 MB/s by adopting a compression technology, so that a video signal can be stored in a computer and correspondingly processed, along with the continuous progress of the prior art, the compression ratio of the video is higher and higher, similarly, in the process of decoding and playing the video, the performance of hardware equipment is poor, particularly when some blue lights and 4K and 8K high-compression-ratio videos are played, the video is easy to be jammed, and simultaneously, when the video is dragged and played, the video is easy to be jammed, the experience of video viewing is reduced.
Disclosure of Invention
The embodiment of the invention provides a video CPU + GPU hardware decoding acceleration system and method based on a window platform, video data are processed in parallel through a GPU and the CPU, the video data stored in a storage module are read through a deployment module, video decoder data are selected, working instructions are respectively sent to a first decoding module and a second decoding module, the working modes of the first decoding module and the second decoding module are distributed to decode the video data, and the problem that the video watching experience is reduced due to the fact that jamming easily occurs in the current video playing is solved.
Video CPU + GPU hardware decoding acceleration system based on window platform includes: the device comprises a storage module, a deployment module, a first decoding module, a second decoding module, a modulation module and a display module;
the storage module is used for storing video data and video decoder data;
the playing module is used for playing the video data stored in the storage module and sending a playing instruction to the allocating module and the modulating module;
the allocation module is used for receiving the playing instruction sent by the playing module, reading the video data stored in the storage module, selecting video decoder data, respectively sending working instructions to the first decoding module and the second decoding module, and allocating the working modes of the first decoding module and the second decoding module;
the first decoding module is used for receiving the working instruction sent by the allocation module, decoding the video data according to the working instruction and caching the decoded video data;
the second decoding module is used for receiving the working instruction sent by the allocation module, decoding the video data according to the working instruction and caching the decoded video data;
the modulation module is used for receiving and processing the playing instruction sent by the playing module, communicating with the display module interface and outputting a video signal to the display module;
and the display module is used for receiving the video signal sent by the modulation module and displaying the video signal.
Furthermore, the playing module is provided with a human-computer interaction interface for interacting with a user.
Further, the storage module includes a memory unit and a decoder storage unit, the memory unit is used for storing video data, and the decoder storage unit is used for storing video decoder data to form a video decoder set.
Further, the allocation module includes a cache unit, a calculation unit, a search unit, and an allocation unit, where the cache unit is configured to cache the video data stored in the storage module, the calculation unit is configured to read the video data cached in the cache unit and read information of the video data, and send the information of the video data to the search unit and the allocation unit, the search unit is configured to select corresponding video decoder data in the storage module according to the video information, and the allocation unit is configured to allocate working modes to the first decoding module and the second decoding module according to the selected video decoder data, the information of the video data, and a play instruction sent by the play module.
Further, the information of the video data includes a playing time length of the video data, encoding information of the video data, and a resolution of the video data.
Further, the first decoding module includes a first decoding unit and a first decoding cache, the first decoding unit is configured to decode the video data stored in the storage module according to the video decoding data stored in the storage module according to the work instruction sent by the deployment module, and cache the decoded data in the first decoding cache, and the first decoding unit is a CPU.
Further, the second decoding module includes a second decoding unit and a second decoding buffer, the second decoding unit is configured to decode the video data stored in the storage module according to the video decoding data stored in the storage module according to the work instruction sent by the deployment module, and buffer the decoded data in the second decoding buffer, and the second decoding unit is a GPU.
Furthermore, the modulation module comprises a calling unit, an interface adaptation unit and an output end, wherein the calling unit is used for receiving the playing instruction sent by the playing module, processing the instruction, respectively reading the video data decoded by the first decoding module and the video data decoded by the second decoding module, processing the decoded video data, and sending the processed decoded video data to the output end, the interface adaptation unit is used for adapting to the interface of the display module to complete the communication between the output end and the interface of the display module, and the output end is used for sending the decoded video data to the display module.
Further, the operation of processing the decoded video data by the retrieval unit includes video data merging and selecting an output video.
In a second aspect, an embodiment of the present invention provides a video CPU + GPU hardware decoding acceleration method based on a window platform, including the following steps:
s1, reading video data, wherein a user selects video data to be played from a memory unit through a human-computer interaction interface arranged in a playing module and sends a playing instruction, a cache unit caches the video data stored in a storage module, a calculation unit reads the video data cached in the cache unit and reads information of the video data, the information of the video data is sent to a search unit and a distribution unit, and the search unit selects corresponding video decoder data in the storage module according to the video information;
s2, decoding the video data, distributing the working mode of the first decoding module and the second decoding module according to the selected video decoder data, the information of the video data and the playing instruction sent by the playing module, decoding the video data stored in the memory unit according to the video decoding data stored in the decoder storage unit by the first decoding unit according to the working instruction sent by the distributing unit, caching the decoded data in a first decoding cache, decoding the video data stored in the memory unit according to the video decoding data stored in the decoder storage unit by the second decoding unit according to the working instruction sent by the distributing unit, and caching the decoded data in a second decoding cache;
and S3, the video output and retrieval unit receives the playing instruction sent by the playing module, processes the instruction, respectively reads the video data decoded by the first decoding module and the video data decoded by the second decoding module, processes the decoded video data, and sends the processed decoded video data to the output end, the interface adaptation unit adapts to the interface of the display module, and the output end sends the decoded video data to the display module.
The technical scheme provided by the embodiment of the invention has the beneficial effects that at least:
according to the invention, the allocation module reads the video data stored in the storage module and selects the video decoder data, the working instructions are respectively sent to the first decoding module and the second decoding module, and the working modes of the first decoding module and the second decoding module are allocated to decode the video data, so that the problem that the video watching experience is reduced due to easy occurrence of blocking in the current video playing process is solved.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic structural diagram of a video CPU + GPU hardware decoding acceleration system based on a window platform according to an embodiment of the present invention;
FIG. 2 is a flowchart of a video CPU + GPU hardware decoding acceleration method based on a window platform according to an embodiment of the present invention.
Reference numerals:
100-a memory module; 101-a memory cell; 102-a decoder memory unit; 200-a playing module; 300-a blending module; 301-a buffer unit; 302-a computing unit; 303-a lookup unit; 304-a dispensing unit; 400-a first decoding module; 401-a first decoding unit; 402-a first decode buffer; 500-a second decoding module; 501-a second decoding unit; 502-second decode buffer; 600-a modulation module; 601-a retrieval unit; 602-an interface adaptation unit; 602-an output terminal; 700-display module.
DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
Example one
As shown in fig. 1, an embodiment of the present invention provides a video CPU + GPU hardware decoding acceleration system based on a window platform, including: the device comprises a storage module 100, a deployment module 300, a first decoding module 400, a second decoding module 500, a modulation module 600 and a display module 700;
the storage module 100 is configured to store video data and video decoder data, where the storage module 100 includes a memory unit 101 and a decoder storage unit 102, the memory unit 101 is configured to store the video data, and the decoder storage unit 102 is configured to store the video decoder data to form a video decoder set;
specifically, video data is stored in the memory unit 101, and a plurality of video decoder data is stored in the decoder storage unit 102, for example, VPx, h.26x and AVS decoders, to form a video decoder set.
A playing module 200, configured to play the video data stored in the storage module 100, and send a playing instruction to the allocating module 300 and the modulating module 600, where the playing module 200 is provided with a human-computer interaction interface, and is used for interacting with a user;
specifically, a user interacts with the system through the human-computer interface, selects video data stored in the memory unit 101, performs a play operation, for example, selects a video, sends an instruction to start, pause, fast forward, and drag to a designated time for playing, and sends the play instruction to the deployment module 300 and the modulation module 600, respectively.
A deployment module 300, configured to receive a play instruction sent by the play module 200, read video data stored in the storage module 100 and select video decoder data, send a work instruction to the first decoding module 400 and the second decoding module 500 respectively, and allocate work modes of the first decoding module 400 and the second decoding module 500, where the deployment module 300 includes a buffer unit 301, a calculation unit 302, a lookup unit 303, and an allocation unit 304, the buffer unit 301 is configured to buffer the video data stored in the storage module 100, the calculation unit 302 is configured to read the video data buffered in the buffer unit 301 and read information of the video data, the information of the video data includes a play time length of the video data, encoding information of the video data, and a resolution of the video data, and send the information of the video data to the lookup unit 303 and the allocation unit 304, the searching unit 303 is configured to select corresponding video decoder data in the storage module 100 according to video information, and the allocating unit 304 is configured to allocate working modes to the first decoding module 400 and the second decoding module 500 according to the selected video decoder data, the video data information, and a playing instruction sent by the playing module 200;
specifically, the caching unit 301 caches video data stored in the memory unit 101 according to a playing instruction sent by the playing module 200, the computing unit 302 reads an index file of the video data to obtain information of the video data, such as encoding information, the searching unit 303 selects a corresponding video decoder according to the obtained information, and the allocating unit 304 allocates working modes to the first decoding module 400 and the second decoding module 500 according to the video decoder data, the video data information, and the playing instruction sent by the playing module 200;
in embodiment a, when the second decoding module 500 is capable of implementing hard decoding after the index file of the video data is read by the computing unit 302 to obtain the information of the video data, the second decoding module 500 is a main decoding platform, the first decoding module 400 is an auxiliary decoding platform, the first decoding module 400 stores the video decoder data according to the decoder storage unit 102 for soft decoding, when the second decoding module 500 decodes the video, the second decoding module 500 decodes 5min before and after the video time point and buffers the video into the first decoding buffer 402, for example, a section of h.265 coded video with a length of 30min, the second decoding module 500 decodes from 10min0s, the first decoding module 400 decodes from 5min before 10min0s and 5min after 10min0s and pre-buffers the video into the first decoding buffer 402, when the user performs a dragging operation through the playing module 200, the decoded video buffer 402 is read from the inside of the first decoding module, the effect of no jamming is realized;
in embodiment b, when the second decoding module 500 is capable of implementing hard decoding after the index file of the video data is read by the computing unit 302 to obtain the information of the video data, the second decoding module 500 is a main decoding platform, the first decoding module 400 is an auxiliary decoding platform, the first decoding module 400 stores the video decoder data according to the decoder storage unit 102 for soft decoding, when the user performs a skip specified time playing operation through the playing module 200, for example, a segment of h.265 coded video with a length of 30min, jumps from 0min0s to 20min3s, because there is no pre-buffering time, it is necessary to perform fast decoding to achieve non-blocking of the video, the first decoding module 400 and the second decoding module 500 perform merging calculation to decode the data at the position point of 20min3s to accelerate the decoding speed, buffer the decoded data in the first decoding buffer 402, read the decoded video data from the first decoding buffer 402, the effect of no jamming is realized;
in embodiment c, when the second decoding module 500 is obtained after the index file of the video data is read by the computing unit 302 to obtain the information of the video data, and hard decoding cannot be implemented by the second decoding module 500, the first decoding module 400 is a main decoding platform, the second decoding module 500 is an auxiliary decoding platform, the first decoding module 400 stores video decoder data according to the decoder storage unit 102 for soft decoding, when a user plays through the playing module 200, for example, a segment of h.265 coded video, the first decoding module 400 and the second decoding module 500 perform combination calculation to decode the h.265 coded video, and buffer the decoded data in the first decoding buffer 402, so as to implement the effect of playing without stuttering by enhancing the calculation capability.
A first decoding module 400, configured to receive a work instruction sent by the deployment module 300, perform decoding work on video data according to the work instruction, and buffer the decoded video data, where the first decoding module 400 includes a first decoding unit 401 and a first decoding buffer 402, the first decoding unit 401 is configured to decode the video data stored in the storage module 100 according to the video decoding data stored in the storage module 100 according to the work instruction sent by the deployment module 300, and buffer the decoded data in the first decoding buffer 402, and the first decoding unit 401 is a CPU;
specifically, the first decoding unit 401 performs soft decoding according to the video decoder data stored in the decoder storage unit 102, and buffers the decoded video data into the first decoding buffer 402.
A second decoding module 500, configured to receive a work instruction sent by the deployment module 300, perform decoding work on video data according to the work instruction, and buffer the decoded video data, where the second decoding module 500 includes a second decoding unit 501 and a second decoding buffer 502, the second decoding unit 501 is configured to decode the video data stored in the storage module 100 according to the video decoding data stored in the storage module 100 according to the work instruction sent by the deployment module 300, and buffer the decoded data in the second decoding buffer 502, and the second decoding unit 501 is a GPU;
specifically, the second decoding unit 501 performs soft decoding according to the video decoder data stored in the decoder storage unit 102, performs hard decoding by an internal decoding circuit when hard decoding is possible, buffers the decoded video data into the second decoding buffer 502, performs soft decoding according to the merging operation of the video decoder data and the first decoding unit 401 when hard decoding is not possible, and buffers the decoded video data into the first decoding buffer 402.
A modulation module 600, configured to receive and process the playing command sent by the playing module 200, communicate with the display module 700 interface, and output a video signal to the display module 700, the modulation module 600 comprises a retrieving unit 601, an interface adaptation unit 602 and an output 603, the retrieving unit 601 is configured to receive a playing instruction sent by the playing module 200, processes the instructions to read the video data decoded by the first decoding module 400 and the video data decoded by the second decoding module 500 respectively, and processes the decoded video data, the operation of the fetch unit 601 processing the decoded video data includes video data merging and selecting an output video, and send the decoded video data that is processed to the output end 603, the interface adaptation unit 602 is configured to adapt to the interface of the display module 700, and the output end 603 is configured to send the decoded video data to the display module 700;
specifically, according to a play instruction sent by a user, when a video is dragged, the retrieval unit 601 retrieves the cached decoded video data from the first decoding cache 402 for playing, when the video jumps to be played within a specified time, the cached decoded video data is retrieved from the first decoding cache 402 for playing, when the video is played within a specified time, the cached decoded video data is retrieved from the second decoding cache 502 for playing, the interface adaptation unit 602 adapts to the display module 700, communication adaptation between the output terminal 603 and the display module 700 is completed, and the retrieval unit 601 sends the retrieved video data to the display module 700 through the output terminal 603.
And a display module 700, configured to receive the video signal sent by the modulation module 600 and display the video signal.
According to the invention, the storage module 100 is used for presetting the video decoder, a user sends a playing instruction to the allocation module 300 through the playing module 200, the allocation module 300 reads the video data stored in the storage module 100 and selects the video decoder data, respectively sends the working instruction to the first decoding module 400 and the second decoding module 500, allocates the working modes of the first decoding module 400 and the second decoding module 500 to decode the video data, and the modulation module 600 respectively reads the data cached in the first decoding module 400 and the second decoding module 500 to play, so that the problem that the video watching experience is reduced due to easy occurrence of blocking in the current video playing is solved.
Example two
The embodiment of the invention also discloses a video CPU + GPU hardware decoding acceleration method based on the window platform, and as shown in figure 2, the method comprises the following steps:
s1, reading video data, selecting video data to be played from the memory unit 101 and sending a play instruction through a human-computer interface arranged in the play module 200 by a user, caching the video data stored in the storage module 100 in the cache unit 301, reading the video data cached in the cache unit 301 and reading information of the video data by the computing unit 302, sending the information of the video data to the searching unit 303 and the allocating unit 304, and selecting corresponding video decoder data in the storage module 100 by the searching unit 303 according to the video information;
specifically, the video data is stored in the memory unit 101, and a plurality of video decoder data is stored in the decoder storage unit 102 to form a video decoder set.
S2, the allocating unit 304 allocates the working modes of the first decoding module 400 and the second decoding module 500 according to the selected video decoder data, the information of the video data, and the playing instruction sent by the playing module 200, the first decoding unit 401 decodes the video data stored in the memory unit 101 according to the working instruction sent by the allocating unit 304 and the video decoding data stored in the decoder storage unit 102, and caches the decoded data in the first decoding buffer 402, the second decoding unit 501 decodes the video data stored in the memory unit 101 according to the working instruction sent by the allocating unit 304 and the video decoding data stored in the decoder storage unit 102, and caches the decoded data in the second decoding buffer 502;
specifically, the caching unit 301 caches video data stored in the memory unit 101 according to a playing instruction sent by the playing module 200, the computing unit 302 reads an index file of the video data to obtain information of the video data, such as encoding information, the searching unit 303 selects a corresponding video decoder according to the obtained information, the allocating unit 304 allocates operating modes of the first decoding module 400 and the second decoding module 500 according to the video decoder data, the video data information and the playing instruction sent by the playing module 200, the first decoding unit 401 stores video decoder data according to the decoder storage unit 102 for soft decoding, caches the decoded video data into the first decoding cache 402, the second decoding unit 501 stores video decoder data according to the decoder storage unit 102 for soft decoding, and performs hard decoding through an internal decoding circuit when hard decoding is possible, the decoded video data is buffered in the second decoding buffer 502, and when the hard decoding cannot be performed, the soft decoding is performed according to the merging operation of the video decoder data and the first decoding unit 401, and the decoded video data is buffered in the first decoding buffer 402.
S3, the video output and retrieval unit 601 receives the playing instruction sent by the playing module 200, processes the instruction to respectively read the video data decoded by the first decoding module 400 and the video data decoded by the second decoding module 500, processes the decoded video data, and sends the processed decoded video data to the output terminal 603, the interface adaptation unit 602 adapts to the interface of the display module 700, and the output terminal 603 sends the decoded video data to the display module 700;
the retrieval unit 601 retrieves the cached decoded video data from the first decoding cache 402 for playing when the video is dragged according to a playing instruction sent by a user, retrieves the cached decoded video data from the first decoding cache 402 for playing when the video is played at a skip specified time, selects to retrieve the cached decoded video data from the second decoding cache 502 for playing when the video is played normally, the interface adaptation unit 602 adapts to the display module 700 to complete communication adaptation of the output terminal 603 and the display module 700, and the retrieval unit 601 sends the retrieved video data to the display module 700 through the output terminal 603.
In the video CPU + GPU hardware decoding acceleration method based on the window platform disclosed in this embodiment, a video decoder is preset in the storage module 100, a user sends a play instruction to the deployment module 300 through the play module 200, the deployment module 300 reads video data stored in the storage module 100 and selects video decoder data, and sends a work instruction to the first decoding module 400 and the second decoding module 500 respectively, and allocates work modes of the first decoding module 400 and the second decoding module 500 to decode the video data, and the modulation module 600 reads data cached in the first decoding module 400 and the second decoding module 500 respectively to play, thereby solving the problem that the video viewing experience is reduced due to easy occurrence of jammers in the current video playing.
It should be understood that the specific order or hierarchy of steps in the processes disclosed is an example of exemplary approaches. Based upon design preferences, it is understood that the specific order or hierarchy of steps in the processes may be rearranged without departing from the scope of the present disclosure. The accompanying method claims present elements of the various steps in a sample order, and are not intended to be limited to the specific order or hierarchy presented.
In the foregoing detailed description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments of the subject matter require more features than are expressly recited in each claim. Rather, as the following claims reflect, invention lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby expressly incorporated into the detailed description, with each claim standing on its own as a separate preferred embodiment of the invention.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. Of course, the storage medium may also be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. Of course, the processor and the storage medium may reside as discrete components in a user terminal.
For a software implementation, the techniques described herein may be implemented with modules (e.g., procedures, functions, and so on) that perform the functions described herein. The software codes may be stored in memory units and executed by processors. The memory unit may be implemented within the processor or external to the processor, in which case it can be communicatively coupled to the processor via various means as is known in the art.
What has been described above includes examples of one or more embodiments. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the aforementioned embodiments, but one of ordinary skill in the art may recognize that many further combinations and permutations of various embodiments are possible. Accordingly, the embodiments described herein are intended to embrace all such alterations, modifications and variations that fall within the scope of the appended claims. Furthermore, to the extent that the term "includes" is used in either the detailed description or the claims, such term is intended to be inclusive in a manner similar to the term "comprising" as "comprising" is interpreted when employed as a transitional word in a claim. Furthermore, any use of the term "or" in the specification of the claims is intended to mean a "non-exclusive or".
Claims (10)
1. Video CPU + GPU hardware decoding acceleration system based on window platform, characterized by comprising: the device comprises a storage module, a deployment module, a first decoding module, a second decoding module, a modulation module and a display module;
the storage module is used for storing video data and video decoder data;
the playing module is used for playing the video data stored in the storage module and sending a playing instruction to the allocating module and the modulating module;
the allocation module is used for receiving the playing instruction sent by the playing module, reading the video data stored in the storage module, selecting video decoder data, respectively sending working instructions to the first decoding module and the second decoding module, and allocating the working modes of the first decoding module and the second decoding module;
the first decoding module is used for receiving the working instruction sent by the allocation module, decoding the video data according to the working instruction and caching the decoded video data;
the second decoding module is used for receiving the working instruction sent by the allocation module, decoding the video data according to the working instruction and caching the decoded video data;
the modulation module is used for receiving and processing the playing instruction sent by the playing module, communicating with the display module interface and outputting a video signal to the display module;
and the display module is used for receiving the video signal sent by the modulation module and displaying the video signal.
2. The window platform video CPU + GPU hardware decoding acceleration system based on claim 1, characterized in that the playing module is provided with a human-computer interaction interface for interacting with a user.
3. The window platform video CPU + GPU hardware decode acceleration system of claim 1, wherein the memory module comprises a memory unit for storing video data and a decoder memory unit for storing video decoder data to form a video decoder set.
4. The window platform video CPU + GPU hardware decoding acceleration system of claim 1, wherein the deployment module comprises a cache unit, a calculation unit, a search unit, and an allocation unit, the cache unit is configured to cache the video data stored in the storage module, the calculation unit is configured to read the video data cached in the cache unit and read information of the video data, and send the information of the video data to the search unit and the allocation unit, the search unit is configured to select corresponding video decoder data in the storage module according to the information of the video, and the allocation unit is configured to allocate the working modes to the first decoding module and the second decoding module according to the selected video decoder data, the information of the video data, and the play instruction sent by the play module.
5. The window platform video CPU + GPU hardware decode acceleration system of claim 4, wherein the information of the video data comprises a playback time length of the video data, encoding information of the video data, and a resolution of the video data.
6. The window platform video CPU + GPU hardware decode acceleration system of claim 1, wherein the first decode module comprises a first decode unit and a first decode buffer, the first decode unit is configured to decode the video data stored in the storage module according to the video decode data stored in the storage module according to the work instruction sent by the deployment module, and buffer the decoded data in the first decode buffer, and the first decode unit is a CPU.
7. The window platform video CPU + GPU hardware decode acceleration system of claim 1, wherein the second decode module comprises a second decode unit and a second decode buffer, the second decode unit is configured to decode the video data stored in the storage module according to the video decode data stored in the storage module according to the work instruction sent by the deployment module, and buffer the decoded data in the second decode buffer, and the second decode unit is a GPU.
8. The window platform video CPU + GPU hardware decode acceleration system of claim 1, wherein the modulation module comprises a fetch unit, an interface adaptation unit, and an output, the fetch unit is configured to receive a play instruction sent by the play module, process the instruction to read video data decoded by the first decoding module and video data decoded by the second decoding module, respectively, and process the decoded video data and send the processed decoded video data to the output, the interface adaptation unit is configured to adapt with the interface of the display module to complete the output to communicate with the interface of the display module, and the output is configured to send the decoded video data to the display module.
9. The window platform video CPU + GPU hardware decode acceleration system of claim 8, wherein the operations of the fetch unit to process decoded video data include video data merging and selecting the output video.
10. The window platform video CPU + GPU hardware decoding acceleration method is applied to the window platform video CPU + GPU hardware decoding acceleration system according to claims 1-9, and is characterized by comprising the following steps:
s1, reading video data, wherein a user selects video data to be played from a memory unit through a human-computer interaction interface arranged in a playing module and sends a playing instruction, a cache unit caches the video data stored in a storage module, a calculation unit reads the video data cached in the cache unit and reads information of the video data, the information of the video data is sent to a search unit and a distribution unit, and the search unit selects corresponding video decoder data in the storage module according to the video information;
s2, decoding the video data, distributing the working mode of the first decoding module and the second decoding module according to the selected video decoder data, the information of the video data and the playing instruction sent by the playing module, decoding the video data stored in the memory unit according to the video decoding data stored in the decoder storage unit by the first decoding unit according to the working instruction sent by the distributing unit, caching the decoded data in a first decoding cache, decoding the video data stored in the memory unit according to the video decoding data stored in the decoder storage unit by the second decoding unit according to the working instruction sent by the distributing unit, and caching the decoded data in a second decoding cache;
and S3, the video output and retrieval unit receives the playing instruction sent by the playing module, processes the instruction, respectively reads the video data decoded by the first decoding module and the video data decoded by the second decoding module, processes the decoded video data, and sends the processed decoded video data to the output end, the interface adaptation unit adapts to the interface of the display module, and the output end sends the decoded video data to the display module.
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