CN111935564B

CN111935564B - Line card, optical module and optical line terminal

Info

Publication number: CN111935564B
Application number: CN202010631167.3A
Authority: CN
Inventors: 张迎; 周丁; 毛灿城
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-07-03
Filing date: 2020-07-03
Publication date: 2022-08-19
Anticipated expiration: 2040-07-03
Also published as: CN111935564A

Abstract

The present application provides a line card, an optical module and an optical line terminal, which can realize wavelength division multiplexing of two uplink and downlink signals, and is beneficial to improve the signal transmission performance. The line card includes: a control module for controlling a first transceiver circuit and a second transceiver circuit, the first transceiver circuit is used to transmit the signal corresponding to the channel of the first rate, and the second transceiver circuit is used to transmit the corresponding signal of the channel of the second rate The connector is used for correspondingly connecting with the pins of the optical module through a plurality of pins, the plurality of pins including pins corresponding to the channels of the first rate and pins corresponding to the channels of the second rate; There are in-phase transmission pins and in-phase transmission pins of differential signals, the in-phase transmission pins are not adjacent to the in-phase transmission pins, and a first capacitor is provided on the first pins adjacent to the in-phase transmission pins , and a second capacitor is arranged on the second pin adjacent to the inverting transmission pin.

Description

Line card, optical module and optical line terminal

Technical Field

The present application relates to the field of communications technologies, and in particular, to an optical line card, an optical module, and an Optical Line Terminal (OLT).

Background

The demand of people for access bandwidth is increasing, and the development of access technology to higher bandwidth is continuously promoted. Passive Optical Network (PON) OLTs have experienced a transition from gigabit-capable passive optical networks (GPONs) at 2.5Gbps downstream and 1.25Gbps upstream to 10gigabit-capable passive optical networks (XG-PONs) at 10Gbps downstream and 2.5Gbps upstream to 10gigabit-capable symmetric passive optical networks (XGs-PONs) at 10Gbps upstream and 10Gbps downstream. In order to further improve the access bandwidth of the PON, the number of the upper and lower channels may also be increased in the same optical fiber in a wavelength division multiplexing manner.

Because the optical module is inserted into the line card through a mechanical structure, it is urgently needed to provide a new line card, which can implement wavelength division multiplexing of two paths of uplink and downlink signals and guarantee the transmission performance of the signals at the same time.

Disclosure of Invention

The application provides a ply-yarn drill, optical module and optical line terminal OLT, can realize the wavelength division multiplexing of two way uplink and downlink signals, and reduced the insertion loss and the return loss of the in-phase transmission pin and the anti-phase transmission pin of nonadjacent differential signal, be favorable to promoting the transmission performance of signal.

In a first aspect, a line card is provided, which includes: the control module is used for controlling a first transceiving circuit and a second transceiving circuit, wherein the first transceiving circuit is used for transmitting signals corresponding to a channel with a first rate, and the second transceiving circuit is used for transmitting signals corresponding to a channel with a second rate; the connector is provided with a plurality of pins and is used for being correspondingly connected with pins of an optical module through the plurality of pins, and the plurality of pins comprise pins corresponding to the channels with the first speed and pins corresponding to the channels with the second speed; in the plurality of pins, there are an in-phase transmission pin of a differential signal and an opposite-phase transmission pin of the differential signal, the in-phase transmission pin and the opposite-phase transmission pin are not adjacent, and there is no ground pin adjacent to the in-phase transmission pin and the opposite-phase transmission pin, a first capacitor is arranged on a first pin adjacent to the in-phase transmission pin, and a second capacitor is arranged on a second pin adjacent to the opposite-phase transmission pin, wherein the capacity of the first capacitor is less than or equal to a first threshold, and the capacity of the second capacitor is less than or equal to a second threshold.

Because the same-phase transmission pin and the opposite-phase transmission pin are not adjacent and have no grounding pin adjacent to the same-phase transmission pin and the opposite-phase transmission pin, if high-speed signals are transmitted on the two pins, a high-speed signal backflow path at the connector is pulled far, and therefore the insertion loss of the signals is increased. The first capacitor is added on the first pin adjacent to the same-phase transmission pin, the second capacitor is added on the second pin adjacent to the opposite-phase transmission pin, and the first capacitor and the second capacitor can play the role of a reflux ground at high speed, so that the insertion loss of high-speed signals can be reduced.

Therefore, this application embodiment is through increasing first electric capacity and second electric capacity for first pin and second pin respectively, optimizes the signal backward flow that these two pins correspond the passageway, has reduced the insertion loss and the return loss of the same phase transmission pin and the anti-phase transmission pin of nonadjacent differential signal, is favorable to promoting the transmission performance of signal.

In addition, the line card of the embodiment of the application can not only realize wavelength division multiplexing of two paths of uplink and downlink signals by connecting a new optical module, but also be compatible with the existing optical module, and ensure that the line card can normally cooperate with the optical module to work when different types of optical modules are butted.

The first rate and the second rate may be equal or unequal, and this is not limited in this embodiment of the application. Illustratively, the first rate may be 10G downstream, 10G/2.5G upstream, or 25G downstream, 25G/10G upstream, etc.; the second rate may be 2.5G downstream, 1.25G upstream, or 10G downstream, 10G/2.5G upstream, or 25G downstream, 25G/10G upstream, etc.

With reference to the first aspect, in some implementations of the first aspect, the first rate is a downstream 10G and an upstream 10G/2.5G, the channel of the first rate is a first 10gigabit symmetric passive optical network XGS-PON channel, the second rate is a downstream 10G and an upstream 10G/2.5G, the channel of the second rate is a second XGS-PON channel, and the type of the optical module that is docked with the line card is a dual 10G PON optical module.

It should be understood that, the non-adjacent in-phase transmission pin and the non-adjacent out-of-phase transmission pin means that one or more other pins exist between the in-phase transmission pin and the non-adjacent-phase transmission pin, and the application does not limit the number of the pins existing between the in-phase transmission pin and the non-adjacent-phase transmission pin.

Specifically, the capacitors are added on the optical module golden fingers and the wire card bottom plate of the first pin and the second pin, so that signal backflow of a transmission channel (for example, a first XGS-PON channel or a second XGS-PON channel) corresponding to the first pin and the second pin at a high frequency (more than 1 GHz) is optimized, and the insertion loss and return loss performance of the XGS-PON channel at the high frequency is improved.

Optionally, the first capacitor and the second capacitor may be a small-package capacitor, or may be a buried capacitor inside a PCB, or may be a parasitic capacitor between a copper-clad small plane inside a Printed Circuit Board (PCB) and an adjacent ground, which is not limited in this embodiment of the present application.

With reference to the first aspect, in certain implementations of the first aspect, the in-phase transmission pin is a transmit part data input pin of the channel at the second rate, and the anti-phase transmission pin is a transmit part inverted data input pin of the channel at the second rate; or, the in-phase transmission pin is a receiving part data input pin of the channel with the second rate, and the reverse phase transmission pin is a receiving part reverse phase data input pin of the channel with the second rate.

With reference to the first aspect, in some implementations of the first aspect, among the pins of the channel corresponding to the first rate, a transmitting portion data input pin of the channel of the first rate is adjacent to a transmitting portion inverted data input pin of the channel of the first rate, and a receiving portion data output pin of the channel of the first rate is adjacent to a receiving portion inverted data output pin of the channel of the first rate.

With reference to the first aspect, in some implementations of the first aspect, among the pins corresponding to the channel at the second rate, a transmitting portion data input pin of the channel at the second rate and a transmitting portion inverse data input pin of the channel at the second rate are adjacent, and a receiving portion data output pin of the channel at the second rate and a receiving portion inverse data output pin of the channel at the second rate are not adjacent. In other words, in the present embodiment, the in-phase transmission pin is a reception part data input pin of the channel of the second rate, and the inverted transmission pin is a reception part inverted data input pin of the channel of the second rate.

With reference to the first aspect, in certain implementations of the first aspect, the in-phase transmission pin and the anti-phase transmission pin include the following pins therebetween: the reset pin of the channel with the first rate, the signal detection pin of the channel with the first rate and the trigger signal pin for receiving the signal strength indication function; the first pin is a reset pin of the channel with the first rate, and the second pin is a trigger signal pin of the received signal strength indication function. Therefore, the line card is minimally changed, and the compatibility is higher.

With reference to the first aspect, in certain implementations of the first aspect, the pins of the channel corresponding to the first rate further include: a reset pin of the first rate channel and/or a rate selection pin of the first rate channel.

With reference to the first aspect, in certain implementations of the first aspect, the pins of the channel corresponding to the first rate further include: resetting of the channel of the first rate and selecting a pin for the rate of the channel of the first rate. It should be understood that, if only one function needs to be reset or rate-selected, the above-mentioned one pin may provide only one function, which is not limited in the embodiment of the present application.

With reference to the first aspect, in some implementation manners of the first aspect, if the type of the optical module is a first type of optical module, the reset pin of the channel at the first rate and the rate selection pin of the channel at the first rate are the same pin; if the type of the optical module is not the first type of optical module, the reset pin of the channel with the first speed and the speed selection pin of the channel with the first speed are two independent pins; the control module is further configured to: and querying the type of the optical module through a two-wire serial bus I2C interface.

Since the OLT may interface with a plurality of different types of optical modules through the line card, the line card is required to distinguish the types of the optical modules in this embodiment, and when interfacing with different types of optical modules, the line card can normally cooperate with the optical modules to work, thereby realizing compatibility with other PON optical modules. The first type of optical module is illustratively a dual 10G PON optical module, and an existing optical module may be referred to as a non-dual 10G PON optical module.

With reference to the first aspect, in certain implementations of the first aspect, the pins corresponding to the channels of the second rate further include: a reset pin of the channel of the second rate.

With reference to the first aspect, in certain implementations of the first aspect, the pins corresponding to the channels of the second rate further include: and the resetting of the channel of the second speed and the speed selection of the channel of the second speed are combined into a pin.

In other words, the reset pin of the channel of the second rate and the rate selection pin of the channel of the second rate may be combined into one pin so that the channel of the second rate can support different rates, for example, 10Gbps upstream and 2.5Gbps upstream in a time division manner.

With reference to the first aspect, in certain implementations of the first aspect, the control module is further configured to: opening or closing a channel of the first rate corresponding to the first transceiving circuit; and/or opening or closing the channel of the second rate corresponding to the second transceiving circuit.

Specifically, when the dual-channel optical module is docked, the line card may set the SERDES and PON MAC connected to the two-rate channels to switch to a required working mode, and output or receive the electrical interface signal of the corresponding optical module; when a single-channel optical module is docked, the line card may close a channel at one rate, switch the SERDES and PON MAC connected to the channel at the other rate to a required operating mode, and output or receive an electrical interface signal of the corresponding optical module.

It should be understood that "closing" one channel may also be replaced by setting the channel to be idle, and this is not limited in this embodiment of the present application.

In a second aspect, there is provided a light module comprising: the first transceiver circuit is used for transmitting signals corresponding to a channel with a first rate; the second transceiving circuit is used for transmitting signals corresponding to the channel with the second rate; an optical module interface, connected to the first transceiver circuit and the second transceiver circuit, including a plurality of pins, configured to be correspondingly connected to pins of a line card through the plurality of pins, where the plurality of pins include a pin corresponding to a channel at the first rate and a pin corresponding to a channel at the second rate; in the plurality of pins, an in-phase transmission pin of a differential signal and an inverted transmission pin of the differential signal exist, the in-phase transmission pin and the inverted transmission pin are not adjacent, and a grounding pin adjacent to the in-phase transmission pin and the inverted transmission pin does not exist; a first capacitor is arranged on a first pin adjacent to the in-phase transmission tube pin, or the first pin is a grounding pin; a second capacitor is arranged on a second pin adjacent to the inverted transmission tube pin, or the second pin is a grounding pin; the capacitance of the first capacitor is smaller than or equal to a first threshold, and the capacitance of the second capacitor is smaller than or equal to a second threshold.

Illustratively, the first pin is a grounding pin, and a second capacitor is arranged on a second pin adjacent to the inverted transmission pin, so that the first pin is not required to be connected with a capacitor.

Illustratively, a first capacitor is arranged on a first pin adjacent to the in-phase transmission pin, and a second pin is a grounding pin, so that the second pin is not required to be connected with a capacitor. Therefore, signal backflow on the transmission channels corresponding to the first pin and the second pin can be better, and the transmission performance is better.

With reference to the second aspect, in some implementations of the second aspect, the in-phase transmission pin is a transmit part data input pin of the channel of the second rate, and the inverted transmission pin is a transmit part inverted data input pin of the channel of the second rate; or, the in-phase transmission pin is a receiving part data input pin of the channel with the second rate, and the inverted transmission pin is a receiving part inverted data input pin of the channel with the second rate.

With reference to the second aspect, in some implementations of the second aspect, in the pins of the channel corresponding to the first rate, a transmitting part data input pin of the channel of the first rate is adjacent to a transmitting part inverted data input pin of the channel of the first rate, and a receiving part data output pin of the channel of the first rate is adjacent to a receiving part inverted data output pin of the channel of the first rate.

With reference to the second aspect, in some implementations of the second aspect, in the pins of the channel corresponding to the second rate, the transmit part data input pin of the channel of the second rate and the transmit part inverse data input pin of the channel of the second rate are adjacent, and the receive part data output pin of the channel of the second rate and the receive part inverse data output pin of the channel of the second rate are not adjacent. In other words, in the present embodiment, the in-phase transmission pin is a reception part data input pin of the channel of the second rate, and the inverted transmission pin is a reception part inverted data input pin of the channel of the second rate.

With reference to the second aspect, in some implementations of the second aspect, the following pins are included between the in-phase transmission pin and the anti-phase transmission pin: the reset pin of the channel with the first rate, the signal detection pin of the channel with the first rate and a trigger signal for receiving a signal strength indication function; the first pin is a reset pin of the channel with the first rate, and the second pin is a trigger signal of the received signal strength indication function.

With reference to the second aspect, in some implementations of the second aspect, the pins corresponding to the channels of the first rate further include: a rate select pin of the first rate channel.

With reference to the second aspect, in some implementations of the second aspect, the following pins are included between the in-phase transmission pin and the anti-phase transmission pin: a ground pin, a signal detection pin of the channel with the first rate, and a trigger signal pin for receiving a signal strength indication function; the first pin is the ground pin, and the second pin is a trigger signal pin of the received signal strength indication function.

With reference to the second aspect, in some implementations of the second aspect, the pins of the channel corresponding to the first rate further include: resetting of the channel of the first rate and selecting a pin for the rate of the channel of the first rate.

In other words, the reset pin of the channel of the first rate and the rate selection pin of the channel of the first rate may be merged into one pin on the optical module. However, it should be understood that, if the optical module only needs to reset or select one function at a rate, the above-mentioned one pin may only provide one function, which is not limited in the embodiment of the present application.

With reference to the second aspect, in some implementations of the second aspect, the pins corresponding to the channels of the second rate further include: a reset pin of the channel of the second rate.

With reference to the second aspect, in some implementations of the second aspect, the pins of the channel corresponding to the second rate further include: resetting of the channel of the second rate and selecting a pin for the rate of the channel of the second rate.

With reference to the second aspect, in certain implementation manners of the second aspect, the first-rate channel is a first 10gigabit symmetric passive optical network XGS-PON channel, the second-rate channel is a second XGS-PON channel, and the optical module is a dual 10G PON optical module.

In a third aspect, an OLT is provided, including: the line card in any implementation manner of the first aspect or the first aspect, and/or the optical module in any implementation manner of the second aspect or the second aspect.

Drawings

Fig. 1 shows a networking schematic of a passive optical network PON.

Fig. 2 shows a networking schematic diagram of a PON based on a joint combo optical module.

Fig. 3 shows a schematic block diagram of a line card according to an embodiment of the present application.

Fig. 4 shows a connection diagram of a line card and an optical module according to an embodiment of the present application.

Fig. 5 shows a networking schematic diagram of a PON based on line cards and optical modules according to an embodiment of the present application.

Fig. 6 is a graph showing a comparison of results before and after line card optimization according to an embodiment of the present invention.

Fig. 7 shows a networking schematic diagram of a PON based on a line card and an existing optical module according to an embodiment of the present application.

Fig. 8 shows a networking schematic diagram of a PON based on a line card and an existing optical module according to an embodiment of the present application.

Fig. 9 shows a networking schematic diagram of a PON based on a line card and an existing optical module according to an embodiment of the present application.

Fig. 10 shows a networking schematic diagram of a PON based on a line card and an existing optical module according to an embodiment of the present application.

Fig. 11 shows a connection diagram of a line card and an improved optical module according to an embodiment of the present application.

Detailed Description

The technical solution in the present application will be described below with reference to the accompanying drawings.

First, terms referred to in embodiments of the present application will be briefly described.

1. Passive Optical Network (PON)

A PON is a passive optical network of a point-to-multipoint (PTMP) structure, which is a combination of network elements in an optical access network based on an Optical Distribution Network (ODN). The PON is a typical passive optical network, which means that an optical distribution network does not include any electronic devices and electronic power sources, and the ODN is composed of all passive devices such as optical splitters (splitters).

A PON includes an OLT installed at a central control station and a plurality of Optical Network Units (ONUs) installed at customer sites and implements a specific set of physical medium dependent layers, transmission convergence layers, and management protocols.

Fig. 1 shows a networking schematic diagram of a PON, and in fig. 1, an optical line terminal OLT 110 is connected to 3 optical network units ONU 130 through an optical distribution network ODN. The ODN refers to the entire passive optical network from the OLT port to the various ONU ports. The ODN includes, among other things, an optical splitter (splitter)120, which may also be referred to as an optical splitter. It should be understood that fig. 1 exemplarily shows 3 ONUs, and in other networking scenarios, one OLT may be connected with a greater number of ONUs, which is not limited in this embodiment of the present application.

The OLT needs to interface with the ODN through a photoelectric conversion circuit. On one hand, the photoelectric conversion circuit needs to convert the electric signal sent by the OLT into an optical signal and transmit the optical signal to the ONU through the ODN; on the other hand, the optical-to-electrical conversion circuit also needs to convert an optical signal transmitted from the ONU through the ODN into an electrical signal and then transmit the electrical signal to the OLT. The photoelectric conversion circuit is positioned on the OLT line card. Because the interior of the photoelectric conversion circuit is relatively complex and the failure rate is relatively high, the photoelectric conversion circuit is generally integrated into an optical module and inserted into an OLT (optical line terminal) line card, so that the photoelectric conversion circuit is convenient to replace. The optical module is embedded into the OLT line card through a mechanical mechanism and is electrically connected with the OLT line card through an electrical interface.

2. Optical module

The optical module comprises a photoelectronic device, a functional circuit, an optical interface and the like, wherein the photoelectronic device comprises a transmitting part and a receiving part. In brief, the optical module functions as a photoelectric converter, the transmitting end converts an electrical signal into an optical signal, and the receiving end converts the optical signal into the electrical signal after the optical signal is transmitted through the optical fiber. An optical module is an optoelectronic device that performs photoelectric and electro-optical conversion. The sending end of the optical module converts the electrical signal into an optical signal, and the receiving end converts the optical signal into the electrical signal.

Currently, the interface types of the mainstream PON OLT optical module include a gigabit ethernet interface small-package pluggable optical module (10-GB small-form-factor pluggable transceiver, XFP) and a small-package hot-pluggable (SFP +). The SFP + optical module is smaller in structure size, and can achieve higher interface density compared with an XFP module. For example, on a certain PON device, an OLT line card supporting an SFP + module can have 16 OLT ports, while an OLT line card supporting an XFP module typically has only 8 OLT ports.

Specifically, the optical module and the OLT line card may be electrically connected through a gold finger on the optical module and a connector on the OLT line card, and the gold finger of the optical module may be inserted into the connector on the OLT line card. The number of gold fingers and pins of a connector of the existing SFP + optical module is two types: a conventional 20-foot and an expanded 22-foot.

The OLT line card is referred to as a line card for short in the present application, but it should be understood that the line card may also be referred to as a board card, an OLT board card, or other names, which is not limited in this embodiment of the present application.

3. PON technology

Currently, the mainstream PON technology mainly includes gigabit-capable passive optical networks (GPON), 10gigabit-capable passive optical networks (XG-PON), 10gigabit-capable symmetric passive optical networks (XGs-PON), and joint (combo) PONs. The XG-PON is obtained by GPON smooth evolution, the network topology of the GPON is used, and optical fibers, splitters and the like of the GPON are reused. The XGS-PON is a symmetric XGPON. Because the XG-PON and the GPON have different uplink and downlink wavelengths, a combiner is required to be arranged outside to combine or separate the working signals in the uplink and downlink directions, so that the XG-PON and the GPON are compatible. The Combo PON can combine two wavelengths in one optical module, for example, the XG-PON and GPON Combo optical module can integrate the transceiving circuits and the wave splitting/combining devices of the GPON and the XG-PON into the same optical module, so that independent sending and receiving of GPON and XG-PON optical signals are realized, and coexistence of a single-port GPON and an XG-PON can be realized; for example, the XGS-PON & GPON Combo optical module may integrate the transceiver circuits and the wavelength-division/multiplexing devices of GPON and XGS-PON in the same optical module, thereby realizing independent transmission and reception of GPON and XGS-PON optical signals and enabling coexistence of single-port GPON and XGS-PON. Therefore, the machine room space is effectively saved, and the network construction cost of the operator for realizing kilomega home entry is effectively reduced. In the present application, the optical module corresponding to the combo PON may also be referred to as a combo optical module.

The optical modules of the GPON and the XG-PON integrate a group of photoelectric and electro-optical conversion circuits, the number of electric signals between the optical modules and an OLT line card is small, and the optical modules are generally defined by pins with 20 feet; the combo optical module integrates two groups of photoelectric and electro-optical conversion circuits, increases the electrical signals between the combo optical module and an OLT line card, and is generally defined by using 22-pin pins.

Fig. 2 shows a networking schematic diagram of a combo optical module-based PON. In fig. 2, the combo optical module integrates two sets of optical-electrical and electrical-optical conversion circuits (or may be a downlink wavelength division mode and an uplink time division mode integrating two sets of optical-electrical conversion and one set of optical-electrical conversion). The combo optical module uses a 22-pin electrical interface and also comprises two groups of electrical signal channels corresponding to serializer/deserializer (SERDES). The SERDES may be integrated inside a Medium Access Control (MAC) chip, but the embodiment of the present invention is not limited thereto. For one of the electrical signal channels, for downlink transmission, the transmission data output by the MAC chip (e.g., XGS-PON MAC or GPON MAC in fig. 2) may be converted into a serial signal by the SERDES, and then transmitted to the combo optical module, which performs electrical-to-optical conversion on the serial signal; for uplink transmission, the combo optical module can perform optical-to-electrical conversion on the optical signals, then sends the converted electrical signals to the SERDES, and the electrical signals are converted into parallel data through the SERDES and then sent to the MAC chip for processing.

Specifically, the XGS-PON & GPON combo optical module includes a group of electrical signal channels supporting uplink and downlink 10gigabit per second (Gbps) (divisor, accurate rate is 9.95328Gbps, this application is abbreviated as 10Gbps), and a group of electrical signal channels supporting downlink 2.5Gbps (divisor, accurate rate is 2.48832Gbps, this application is abbreviated as 2.5Gbps), uplink 1.25Gbps (divisor, accurate rate is 1.24416Gbps, this application is abbreviated as 1.25 Gbps). The two electrical signal paths may also be referred to as a high speed path and a low speed path.

Wherein, the electrical signal channel supporting up and down 10Gbps is used for connecting the electrical interface of the XGS-PON channel, and can also support the speed of down 10Gbps and up 2.5Gbps, as shown in fig. 2, the group of electrical signal channels is connected with the XGS-PON MAC, and the transmission data (converted by SERDES) of the XGS-PON MAC can pass through the XGS-PON&The GPON combo optical module performs electric-to-optical conversion, and the ODN is used for obtaining a downlink optical signal lambda ₁ Transmitting to an XG-PON ONU or an XGS-PON ONU; upstream optical signal lambda from an XG-PON ONU or an XGS-PON ONU ₂ Can pass through XGS-PON&The GPON combo optical module performs optical-to-electrical conversion, and the converted 10G or 2.5G electricityThe signal is then sent to the XGS-PON MAC (SERDES conversion).

The electrical signal channels supporting downlink 2.5Gbps and uplink 1.25Gbps are used to connect the electrical interface of the GPON channel, as shown in fig. 2, the group of electrical signal channels is connected with the GPON MAC, and the transmission data (converted by SERDES) of the GPON MAC can pass through the XGS-PON&The GPON combo optical module performs electric-to-optical conversion, and the ODN is used for obtaining the downlink optical signal lambda ₃ Transmitting to a GPON ONU; upstream optical signal λ from GPON ONU ₄ Can pass through XGS-PON&The GPON combo optical module performs optical-to-electrical conversion, and the converted 1.25G electrical signal is sent to the GPON MAC (subjected to SERDES conversion).

It should be understood that the XG-PON ONU described above is used to indicate an ONU capable of supporting the XG-PON technology, the XGs-PON ONU is used to indicate an ONU capable of supporting the XGs-PON technology, and the GPON ONU is used to indicate an ONU capable of supporting the GPON technology.

The combo optical module shown in fig. 2 adopts a 22-pin electrical interface, and in order to be compatible with the previous generation 20-pin electrical interface, the high-frequency performance is abandoned on a low-speed channel, and only electric signals supporting downlink 2.5Gbps and uplink 1.25Gbps can be ensured to pass well. The following description will be made with reference to the table to define the 22-pin electrical interface in the combo optical module shown in fig. 2.

Watch 1

Because the optical module and the OLT are electrically connected through the gold finger on the optical module and the connector on the OLT line card, the OLT line card and the optical module respectively include the 22-pin electrical interface (also referred to herein as 22 pins).

The increasing demand of people for access bandwidth continuously pushes the development of access technology to higher bandwidth. The PON OLT optical module experiences from GPON with 2.5Gbps downlink and 1.25Gbps uplink to XG-PON with 10Gbps downlink and 2.5Gbps uplink and to XGS-PON with 10Gbps uplink and downlink. In order to further increase the access bandwidth of the PON, the number of the uplink and downlink channels may also be increased in the same optical fiber in a form of wavelength division multiplexing, for example, two groups of uplink and downlink channels are implemented by a Wavelength Division Multiplexer (WDM) shown in fig. 2.

On the basis, wavelength division multiplexing of two paths of uplink and downlink high-speed signals (for example, 10Gbps signals) is realized, and the access bandwidth of the PON can be improved to a greater extent, but two groups of electrical signal channels capable of supporting the uplink and downlink high-speed signals (for example, 10Gbps signals) are required on an interface of the combo optical module. The current 22-pin PON SFP + electrical interface (i.e. 22 pins shown in table one) cannot meet this requirement, and correspondingly, since the optical module is connected to the line card through the connector, the current line card cannot meet the requirement. If the pins of the existing electrical interface are simply replaced, the transmission performance of the signals is affected.

In view of this, the present application provides a new line card, an optical module and an OLT, which can implement wavelength division multiplexing of two uplink and downlink signals, thereby increasing the access bandwidth of the PON to a greater extent, reducing the insertion loss and return loss of the in-phase transmission pin and the anti-phase transmission pin of non-adjacent differential signals, and facilitating to improve the transmission performance of signals.

Fig. 3 shows a schematic block diagram of a line card 300 according to an embodiment of the present application. The line card 300 includes: a control module 310 and a connector 320. The control module 310 is configured to control a first transceiver circuit and a second transceiver circuit, where the first transceiver circuit is configured to transmit a signal corresponding to a channel with a first rate, and the second transceiver circuit is configured to transmit a signal corresponding to a channel with a second rate; the connector 320 is provided with a plurality of pins for corresponding connection with pins of the optical module through the plurality of pins, and the plurality of pins on the connector include pins corresponding to a channel of a first rate and pins corresponding to a channel of a second rate.

Corresponding to the line card 300, the optical module in the embodiment of the present application includes: the first transceiver circuit, the second transceiver circuit and the optical module interface are arranged, wherein the first transceiver circuit is used for transmitting signals corresponding to a channel with a first rate; the second transceiver circuit is used for transmitting signals corresponding to a channel with a second rate; the optical module interface is connected with the first transceiver circuit and the second transceiver circuit, and comprises a plurality of pins which are used for being correspondingly connected with the connector pins of the line card through the plurality of pins, wherein the plurality of pins comprise pins corresponding to a channel with a first rate and pins corresponding to a channel with a second rate.

In a possible implementation manner, the first rate is downstream 10G and upstream 10G/2.5G, the first rate channel may be referred to as a first 10gigabit symmetric passive optical network XGS-PON channel, the second rate channel is downstream 10G and upstream 10G/2.5G, the second rate channel may be referred to as a second XGS-PON channel, and the type of the optical module interfaced with the line card may be referred to as a dual 10G PON optical module.

It should be understood that the XGS-PON channel and the dual 10G PON optical module are merely exemplary, and the line card and the optical module of the present application do not exclude channels that can be applied to other rates, and the names of the line card and the optical module are not limited in the embodiments of the present application.

Optionally, the control module 310 may specifically include a Central Processing Unit (CPU) and a MAC, where the operation of the optical module interface is controlled by the MAC and the CPU, and the operation of the MAC itself is also controlled by the CPU.

Taking the pin in the first table as an example, the pin Tx Disable can be directly controlled by the CPU, and the Reset pin (Reset), the signal detection pin (SD), the Rate selection pin (Rate _ Sel), the pin RSSI Trig, etc. need to be accurately matched in time sequence and can be controlled by the MAC. The I2C interface is a low-speed interface for the CPU to access and control the optical module. Illustratively, the optical module has a micro programmed control unit (MCU) inside, the CPU may be connected to the MCU of the optical module through an I2C interface, and both transceiver circuits on the optical module may be controlled by the MCU.

It should be understood that the pin corresponding to the channel with the first rate is used for interfacing with the first transceiver circuit, that is, for transmitting a signal corresponding to the channel with the first rate, and the pin corresponding to the channel with the second rate is used for interfacing with the second transceiver circuit, that is, for transmitting a signal corresponding to the channel with the second rate, where the signal transmitted by the channel with the first rate is an uplink downlink signal and the signal transmitted by the channel with the second rate is an uplink downlink signal, so that a basis is laid for implementing wavelength division multiplexing of the two uplink and downlink signals.

In the plurality of pins, a same-phase transmission pin (positive) of the differential signal and an inverted-phase transmission pin (negative) of the differential signal exist, the same-phase transmission pin and the inverted-phase transmission pin are not adjacent, and a grounding pin adjacent to the same-phase transmission pin and the inverted-phase transmission pin does not exist; a first capacitor is arranged on a first pin adjacent to the in-phase transmission tube pin, and a second capacitor is arranged on a second pin adjacent to the anti-phase transmission tube pin; the capacity of the first capacitor is smaller than or equal to a first threshold value, and the capacity of the second capacitor is smaller than or equal to a second threshold value.

Specifically, the in-phase transmission pin and the inverted transmission pin of the differential signal are not adjacent to each other, and there is no ground pin adjacent to the in-phase transmission pin and the inverted transmission pin. The first capacitor is added on a first pin adjacent to the same-phase transmission pin, the second capacitor is added on a second pin adjacent to the opposite-phase transmission pin, and the first capacitor and the second capacitor can play the role of a backflow ground at high speed, so that the insertion loss of high-speed signals can be reduced.

Therefore, in the embodiment of the application, the capacitors are respectively added on the optical module golden finger and the line card bottom plate of the first pin adjacent to the in-phase transmission pin and the second pin adjacent to the anti-phase transmission pin, so that the signal reflux of the corresponding channels of the two pins is optimized, the insertion loss and return loss of the in-phase transmission signal and the anti-phase transmission signal of the non-adjacent differential signals under high frequency are reduced, and the signal transmission performance is favorably improved.

Illustratively, for the first and second XGS-PON channels, by adding capacitance, signal backflow at a high frequency (above 1 GHz) of the XGS-PON channel (the first or second XGS-PON channel) corresponding to the first and second pins can be optimized.

It should be understood that the non-adjacent in-phase transmission pin and the non-adjacent inverted transmission pin means that there are one or more other pins between the in-phase transmission pin and the inverted transmission pin, and the application does not limit the number of the pins existing between the in-phase transmission pin and the inverted transmission pin.

Optionally, the first capacitor and the second capacitor may be a capacitor in a small package, may also be a buried capacitor inside a PCB, and may also be a parasitic capacitor between a copper sheet facet inside a Printed Circuit Board (PCB) and an adjacent ground, which is not limited in this embodiment of the present application.

The in-phase transmission pin can be an in-phase transmitting pin and can also be an in-phase receiving pin; similarly, the inverting transmission pin may be an inverting transmission pin or an inverting reception pin, which is not limited in this embodiment of the present application.

Fig. 4 shows a connection diagram of a line card and an optical module according to an embodiment of the present application. On the line card side, the first pin and the second pin are grounded through a capacitor respectively; on the optical module side, the first pin and the second pin are grounded through a capacitor, respectively. The capacities of the four capacitors shown in fig. 4 may all be the same, or may all or part of the capacitors may be different, which is not limited in this embodiment of the application.

In order to better comply with the existing optical module, the pins corresponding to the channel of the first rate include: a transmit portion data input pin of a channel of a first rate, a transmit portion inverse data input pin of a channel of a first rate, a receive portion data output pin of a channel of a first rate, a receive portion inverse data output pin of a channel of a first rate. Wherein the transmit portion data input pin of the channel at the first rate is adjacent to the transmit portion inverted data input pin of the channel at the first rate, and the receive portion data output pin of the channel at the first rate is adjacent to the receive portion inverted data output pin of the channel at the first rate.

The pin corresponding to the channel of the second rate includes: a transmit portion data input pin of a channel of a second rate, a transmit portion inverse data input pin of a channel of a second rate, a receive portion data output pin of a channel of a second rate, a receive portion inverse data output pin of a channel of a second rate. And the receiving part data output pin of the channel of the second rate is not adjacent to the receiving part inverted data output pin of the channel of the second rate. In other words, in the present embodiment, the in-phase transmission pin is a reception part data input pin of the channel of the second rate, and the inverted transmission pin is a reception part inverted data input pin of the channel of the second rate.

For convenience of understanding, the first XGS-PON channel is an example of a first rate channel, and the second XGS-PON channel is an example of a second rate channel. However, it should be understood that the first XGS-PON channel described below may be replaced by a channel with another rate, and the second XGS-PON channel may be replaced by a channel with another rate, which is not limited in this embodiment of the present application.

Because the performance of the uplink electric signal channel of the second XGS-PON channel cannot meet the requirement of 10Gbps, in the embodiment of the present application, a first capacitor is disposed on a first pin adjacent to a data output pin of a receiving portion of the second XGS-PON channel, and a second capacitor is disposed on a second pin adjacent to an inverted data output pin of the receiving portion of the second XGS-PON channel.

Specifically, capacitors are added on optical module golden fingers and a wire card bottom plate of the first pin and the second pin, signal backflow of the second XGS-PON channel under high frequency (1 GHz-5 GHz) is optimized, and the insertion loss and return loss performance of the second XGS-PON channel under high frequency is improved.

As an alternative embodiment, the following pins may be included between the in-phase transmission pin and the anti-phase transmission pin: the signal detection circuit comprises a reset pin of a first XGS-PON channel, a signal detection pin of the first XGS-PON channel and a trigger signal pin for receiving a signal strength indication function; the first pin is a reset pin of the first XGS-PON channel, and the second pin is a trigger signal pin for receiving a signal strength indication function.

Fig. 5 shows a networking schematic diagram of a PON based on a new line card and a new optical module according to an embodiment of the present application. Fig. 5 is similar to fig. 2, except that fig. 5 employs the line card and the optical module according to the embodiment of the present application, so that the PON shown in fig. 5 can implement wavelength division multiplexing of two uplink and downlink channels at 10 Gbps.

The two electrical signal channels are respectively connected with electrical interfaces of two XGS-PON channels (namely the first XGS-PON channel and the second XGS-PON channel), and can support the uplink and downlink rates of 10Gbps, or the downlink rates of 10Gbps and the uplink rates of 2.5 Gbps. As shown in FIG. 5, for a set of electrical signal channels connected to the XGS-PON MAC, the transmit data (converted by the SERDES) of the XGS-PON MAC may pass through the XGS-PON&The GPON combo optical module performs electric-to-optical conversion, and the ODN is used for obtaining the downlink optical signal lambda ₁ (or lambda) ₅ ) Transmitting to an XG-PON ONU or an XGS-PON ONU; upstream optical signal lambda from an XG-PON ONU or an XGS-PON ONU ₂ (or lambda) ₆ ) Can pass through XGS-PON&The GPON combo optical module performs optical-to-electrical conversion, and the converted 10G or 2.5G electric signal is sent to the XGS-PON MAC (through SERDES conversion).

As an optional embodiment, the pin corresponding to the first XGS-PON channel further comprises: a reset pin of the first XGS-PON channel and/or a rate select pin of the first XGS-PON channel.

As an alternative embodiment, the pin corresponding to the second XGS-PON channel further comprises: a reset pin of a second XGS-PON channel.

As an optional embodiment, the pin corresponding to the second XGS-PON channel further comprises: resetting of the second XGS-PON channel and rate selection of the second XGS-PON channel are combined into one pin. In other words, the reset pin of the second XGS-PON channel and the rate selection pin of the second XGS-PON channel may be combined into one pin so that the second XGS-PON channel can support upstream 10Gbps and upstream 2.5Gbps in a time division manner. The rate selection pin is used for switching the working rate of the receiving circuit.

Table two lists pin order and functional description in the line card and optical module according to the embodiment of the present application. In table two, pin 8 is the reset pin of the first XGS-PON channel (also called XGS-PON 1), pin 12 is the rate selection pin of the first XGS-PON channel, and pin 19 is the reset and rate selection unified pin of the second XGS-PON channel (also called XGS-PON 2).

Watch two

Compared with the first table, the second table replaces the pins corresponding to the GPON channel in the first table with the pins corresponding to the second XGS-PON channel in the application, and the pins corresponding to the original XGS-PON channel are the pins corresponding to the first XGS-PON in the application. In addition, the pin 19 shown in table two is an all-in-one pin, but it should be understood that if the second XGS-PON channel does not need the function of rate selection, or the second XGS-PON channel only supports one uplink rate, merging may not be performed, which is not limited in this embodiment of the present application.

It should be understood that the pin names in table two above are exemplary, and are only for compatibility with existing table two, and each pin may also have other names, which is not limited in this embodiment of the application. Table iii is similar, and will not be described in detail later.

And if the pin corresponding to the GPON channel in the first table is simply replaced by the pin corresponding to the second XGS-PON channel, the replaced pin is simulated, and according to the simulation result, the downlink electric signal of the second XGS-PON channel can meet the performance requirement of 10Gbps rate, while the uplink electric signal can not meet the requirement. Therefore, on the line card and the optical module, the capacitors can be respectively added to a first pin adjacent to a receiving part data output pin of the second XGS-PON channel and a second pin adjacent to a receiving part inverted data output pin of the second XGS-PON channel, so that the performance of an uplink channel is optimized. The first pin is a No. 8 pin XGS-PON Reset adjacent to a No. 7 pin XGS-PON2 RD-in the table two, and the second pin is a No. 10 pin RSSI Trig adjacent to a No. 11 pin XGS-PON2 RD + in the table two.

Fig. 6 shows a comparison graph of the results before and after optimization, wherein a dotted line is a frequency curve before optimization, and a solid line is a frequency curve after optimization, and it can be seen from fig. 6 that the transmission performance of the optimized second XGS-PON channel at high frequency is significantly improved.

By optimizing the uplink electric signal channel of the second XGS-PON channel, the transmission performance of the second XGS-PON channel can be improved, and wavelength division multiplexing of two paths of uplink and downlink 10Gbps is realized. The modification reduces the high-frequency performance of the signals corresponding to the first pin and the second pin, but the signals of the two pins have low rates and do not substantially affect the signals.

The line card in the embodiment of the application can not only realize wavelength division multiplexing of two paths of uplink and downlink 10Gbps by connecting a new optical module (namely the dual 10G PON optical module), but also be compatible with the existing optical module, and ensure that the line card can normally cooperate with the optical module to work when the line card is butted with the optical modules of different types.

As an alternative embodiment, the control module 310 is further configured to: opening or closing a channel with a first speed corresponding to the first transceiving circuit; and/or opening or closing a channel of a second rate corresponding to the second transceiving circuit.

Specifically, when the dual-channel optical module is docked, the line card may set the SERDES and PON MAC connected to the two-rate channels to switch to a required working mode, and output or receive the electrical interface signal of the corresponding optical module; when a single-channel optical module is docked, the line card may close one of the channels at one rate, switch the SERDES and PON MAC connected to the channel at the other rate to a required operating mode, and output or receive an electrical interface signal of the corresponding optical module. For the optical module of the single transceiver, the line card can use the channel of the first rate; for the optical module with dual channels, the line card may configure the high-rate transceiver to use a channel with a first rate and the low-rate transceiver to use a channel with a second rate.

It should be understood that "closing" one channel may be replaced by setting the channel to be idle, and the embodiment of the present application is not limited thereto.

Fig. 7 to 10 show networking schematic diagrams of a PON in which an optical module is docked by a line card according to an embodiment of the present application. The line card in fig. 7 is docked with the XG-PON & GPON Combo optical module, and at this time, the line card configures the high-rate transceiver to use the first channel and the low-rate transceiver to use the second channel. The linecard in fig. 8 interfaces with an XGS-PON optical module, which is an optical module for a single transceiver, at which time the linecard configures the transceiver to use a first channel and configures a second channel to be off or idle. The linecard in fig. 9 interfaces with an XG-PON optical module, which is an optical module for a single transceiver, at which time the linecard configures the transceiver to use a first channel and configures a second channel to be off or idle. The line card in fig. 10 is docked with a GPON optical module, which is an optical module of a single transceiver, and at this time, the line card configures the transceiver to use the first channel and configures the second channel to be closed or idle.

For further optimization, the optical module according to the embodiment of the present application may be improved, that is, in the definition of the pins of the dual 10G optical module, the pin 8 in the above table two is defined as a ground pin, and the OLT line card bottom plate is still grounded through a capacitor. The advantage of this is that, because the impedance of the capacitor at high frequency is hardly affected by parasitic parameters (mainly equivalent series inductance (ESL)), the direct grounding of the No. 8 pin on the optical module side can achieve the good backflow of the No. 7 pin XGS-PON2 RD-on the optical module gold finger side, and the backflow of the No. 11 pin XGS-PON2 RD + also has certain benefits. The purpose of the 8 th pin on the line card side being grounded through a capacitor is to maintain forward compatibility.

Next, the improved optical module (also referred to as an improved dual 10G optical module) will be described in detail. In the improved optical module, the first pin (or the second pin) is modified into a grounding pin, so that the first pin (or the second pin) is directly grounded without connecting a capacitor. Therefore, signal backflow on the XGS-PON channels corresponding to the first pin and the second pin can be better, and the transmission performance is better.

Illustratively, the first pin adjacent to the receive partial data output pin of the second XGS-PON channel is set as a ground pin, and exemplarily, pin No. 8 in table two is changed to a ground pin.

Optionally, the pin corresponding to the first XGS-PON channel further comprises: the reset of the first XGS-PON channel and the rate selection of the first XGS-PON channel are integrated into a pin. In other words, the reset pin of the first XGS-PON channel and the rate select pin of the first XGS-PON channel may be combined into one pin on the optical module. However, it should be understood that, if the optical module only needs to reset or select one function at a rate, the above-mentioned one pin may only provide one function, which is not limited in the embodiment of the present application.

Illustratively, table three lists the pin order and the functional description in the optical module after the improvement of the embodiment of the present application. In the third table, the No. 8 pin is a ground pin, the No. 12 pin is a first speed selection combining pin for resetting and speed selection of the first XGS-PON channel, and the No. 19 pin is a first speed selection combining pin for resetting and speed selection of the second XGS-PON channel.

Watch III

The pin No. 12 shown in table three is a unified pin, but it should be understood that, if the first XGS-PON channel does not need the function of rate selection, or the first XGS-PON channel only supports one uplink rate, merging may not be performed, which is not limited in this embodiment of the present application.

Fig. 11 shows a connection diagram of a line card and an improved optical module according to an embodiment of the present application. On the line card side, the RSSI Trig of the No. 8 pin and the RSSI Trig of the No. 10 pin are grounded through a capacitor respectively; on the improved double 10G optical module side, the No. 8 pin is directly grounded, and the No. 10 pin RSSI Trig is grounded through a capacitor. The capacities of the three capacitors shown in fig. 8 may be all the same, or may be all or partially different, and this is not limited in this embodiment of the present application.

Because the OLT may interface with a plurality of different types of optical modules through the line card, the improved optical module in the embodiment of the present application may be referred to as a dual 10G optical module, and the existing optical module may be referred to as a non-dual 10G optical module. When the improved optical module is in butt joint, the line card can determine that the 8 # pin outputs a low level or floats, and when the improved optical module is in butt joint with a non-double 10G optical module, the line card can determine that the 8 # pin is still a reset pin of the first XGS-PON channel, so that the line card is required to distinguish the types of the optical module in the embodiment, and the improved optical module is normally matched with the optical modules of different types to work.

As an optional embodiment, optionally, the processing module is further configured to: and inquiring the type of the optical module interfaced with the line card through an interface of a two-wire-integrated circuit (I2C). If the type of the optical module is a double 10G PON optical module, the line card determines that a reset pin of the first XGS-PON channel and a rate selection pin of the first XGS-PON channel are the same pin; and if the type of the optical module is not the double 10G PON optical module, the line card determines that the reset pin of the first XGS-PON channel and the rate selection pin of the first XGS-PON channel are two independent pins.

Taking the third table as an example, when the dual 10G PON optical module shown in the third table is docked, the No. 8 pin is the ground pin GND on the optical module side, and is not used on the line card side, and can output a low level or float, and signal backflow is optimized by a capacitor near the connector; the Reset and Rate _ Sel pins of the first XGS-PON channel are functionally unified to pin number 12. When other non-double 10G PON optical modules are docked, the pin No. 8 is defined as the Reset of the corresponding channel, and the pin No. 12 is defined as the Rate _ Sel of the corresponding channel. The switching of the signals can be realized by peripheral digital circuits.

The improved optical module can better realize signal backflow of the second XGS-PON, and when the line card is connected with a new optical module, the line card can transmit signals according to the pin definition of the new optical module; when the line card is in butt joint with an existing optical module, signals can be transmitted according to the pin definition of the existing optical module. When different types of optical modules are butted, the line cards can normally cooperate with the optical modules to work, and compatibility with other PON optical modules is realized.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one type of logical functional division, and other divisions may be realized in practice, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a read-only memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A line card, comprising:

the control module is used for controlling a first transceiving circuit and a second transceiving circuit, wherein the first transceiving circuit is used for transmitting signals corresponding to a channel with a first rate, and the second transceiving circuit is used for transmitting signals corresponding to a channel with a second rate;

the connector is provided with a plurality of pins and is used for being correspondingly connected with pins of an optical module through the plurality of pins, and the plurality of pins comprise pins corresponding to the channels with the first speed and pins corresponding to the channels with the second speed;

in the plurality of pins, there are an in-phase transmission pin of a differential signal and an opposite-phase transmission pin of the differential signal, the in-phase transmission pin and the opposite-phase transmission pin are not adjacent, and there is no ground pin adjacent to the in-phase transmission pin and the opposite-phase transmission pin, a first capacitor is arranged on a first pin adjacent to the in-phase transmission pin, and a second capacitor is arranged on a second pin adjacent to the opposite-phase transmission pin, wherein the capacity of the first capacitor is less than or equal to a first threshold, and the capacity of the second capacitor is less than or equal to a second threshold.

2. The line card of claim 1, wherein the in-phase transmission pin is a transmit partial data input pin of the channel at the second rate, and the anti-phase transmission pin is a transmit partial anti-phase data input pin of the channel at the second rate; or,

the in-phase transmission pin is a receiving part data input pin of the channel with the second speed, and the reverse phase transmission pin is a receiving part reverse phase data input pin of the channel with the second speed.

3. The line card of claim 1 or 2, wherein, among the pins corresponding to the channels of the first rate, transmit portion data input pins of the channels of the first rate are adjacent to transmit portion inverse data input pins of the channels of the first rate, and receive portion data output pins of the channels of the first rate are adjacent to receive portion inverse data output pins of the channels of the first rate.

4. The line card according to claim 1 or 2, characterized in that the in-phase transmission pins and the anti-phase transmission pins include the following pins therebetween:

the reset pin of the channel with the first rate, the signal detection pin of the channel with the first rate and the trigger signal pin for receiving the signal strength indication function;

the first pin is a reset pin of the channel with the first rate, and the second pin is a trigger signal pin of the received signal strength indication function.

5. The line card of claim 1 or 2, wherein the pins corresponding to the lanes for the first rate further comprise:

a reset pin of a channel of the first rate and/or a rate selection pin of a channel of the first rate.

6. The line card of claim 1 or 2, wherein the pins corresponding to the lanes for the first rate further comprise:

the reset of the first speed channel and the speed selection of the first speed channel are combined into a pin.

7. The line card according to claim 1 or 2, wherein the first rate lanes are first 10gigabit symmetric passive optical network, XGS-PON, lanes, the second rate lanes are second XGS-PON lanes, and the optical module is of the type dual 10G PON optical module.

8. The line card according to claim 1 or 2, wherein if the type of the optical module is a first type of optical module, the reset pin of the first rate channel and the rate selection pin of the first rate channel are the same pin;

if the type of the optical module is not the first type of optical module, the reset pin of the channel with the first speed and the speed selection pin of the channel with the first speed are two independent pins;

the control module is further configured to:

and querying the type of the optical module through a two-wire serial bus I2C interface.

9. The line card of claim 1 or 2, wherein the pins corresponding to the lanes at the second rate further comprise:

a reset pin of the channel of the second rate.

10. The line card of claim 1 or 2, wherein the pins corresponding to the lanes for the second rate further comprise:

and the resetting of the channel of the second speed and the speed selection of the channel of the second speed are combined into a pin.

11. The line card of claim 1 or 2, wherein the control module is further configured to:

opening or closing the channel of the first speed corresponding to the first transceiving circuit; and/or

And opening or closing the channel of the second rate corresponding to the second transceiving circuit.

12. A light module, comprising:

the first transceiving circuit is used for transmitting signals corresponding to a channel with a first rate;

the second transceiver circuit is used for transmitting signals corresponding to the channel with the second rate;

an optical module interface, connected to the first transceiver circuit and the second transceiver circuit, including a plurality of pins, for corresponding connection with pins of a line card through the plurality of pins, where the plurality of pins include a pin corresponding to a channel of the first rate and a pin corresponding to a channel of the second rate;

in the plurality of pins, an in-phase transmission pin of a differential signal and an inverted transmission pin of the differential signal exist, the in-phase transmission pin and the inverted transmission pin are not adjacent, and a grounding pin adjacent to the in-phase transmission pin and the inverted transmission pin does not exist; a first capacitor is arranged on a first pin adjacent to the in-phase transmission pin, or the first pin is a grounding pin; a second capacitor is arranged on a second pin adjacent to the inverted transmission tube pin, or the second pin is a grounding pin; the capacitance of the first capacitor is smaller than or equal to a first threshold, and the capacitance of the second capacitor is smaller than or equal to a second threshold.

13. The optical module of claim 12, wherein the in-phase transmission pin is a transmit part data input pin of the channel of the second rate, and the anti-phase transmission pin is a transmit part anti-phase data input pin of the channel of the second rate; or,

14. The optical module according to claim 12 or 13, wherein among the pins corresponding to the channels of the first rate, the transmitting partial data input pins of the channels of the first rate are adjacent to the transmitting partial inverse data input pins of the channels of the first rate, and the receiving partial data output pins of the channels of the first rate are adjacent to the receiving partial inverse data output pins of the channels of the first rate.

15. The optical module according to claim 12 or 13, characterized in that the in-phase transmission pins and the anti-phase transmission pins comprise the following pins therebetween:

the signal detection circuit comprises a reset pin of a channel with a first rate, a signal detection pin of the channel with the first rate and a trigger signal pin for receiving a signal strength indication function;

16. The optical module of claim 15, wherein the pins corresponding to the channels of the first rate further comprise:

a rate select pin of the first rate channel.

17. The optical module according to claim 12 or 13, characterized in that the in-phase transmission pins and the anti-phase transmission pins comprise the following pins therebetween:

the signal detection circuit comprises a grounding pin, a signal detection pin of a channel with the first rate and a trigger signal pin for receiving a signal strength indication function;

the first pin is the ground pin, and the second pin is a trigger signal pin of the received signal strength indication function.

18. The optical module of claim 17, wherein the pins corresponding to the channels of the first rate further comprise:

19. The optical module according to claim 12 or 13, wherein the pins corresponding to the channels of the second rate further comprise:

a reset pin of the channel of the second rate.

20. The optical module according to claim 12 or 13, wherein the pins corresponding to the channels of the second rate further comprise:

resetting of the channel of the second rate and selecting a pin for the rate of the channel of the second rate.

21. The optical module of claim 12 or 13, wherein the first rate channel is a first 10gigabit symmetric passive optical network, XGS-PON, channel, and wherein the second rate channel is a second XGS-PON channel, and wherein the optical module is of the type dual 10G PON optical module.

22. An optical line termination, OLT, comprising: the line card according to any one of claims 1 to 11, and/or the optical module according to any one of claims 12 to 21.