CN1119342A - 带有多层连接的电子封装件 - Google Patents
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Abstract
一种用于电子封装件的电路化衬底,其中的衬底(例如陶瓷)上包括一个以上由合适的介电材料例如聚酰亚胺分隔开的导电层(例如铜),各层包括其自身的各接触位置,它们用例如焊料来直接电连接到置于衬底上形成最终封装件一部分的半导体芯片的相应接触点。还提供了一种制造这种封装件的方法。值得注意的是,这样得到的封装件不含有导电层之间在所需接触位置处的互连,而是这类接触位置与芯片直接连接。
Description
本发明涉及到电子封装,特别是至少采用二个不同导体层(例如信号层、电源或接地层)作为其部件的那种封装。这种封装件特别适用于信息处理系统(计算机)。
上述类型的典型电子封装件包括一个关键元件,即介电衬底,在这一由陶瓷或诸如玻璃纤维加固的环氧树脂(FR4)之类的合适的聚合物材料所构成的衬底之上或之中,带有各种所需的导电层。
在工业界,这种多层电子封装件的一个代表性的例子称之为多层陶瓷聚酰亚胺(MCP)封装,它采用了一个陶瓷衬底,该衬底上至少带有两个被电介质中间层(在MCP情况下典型地为聚酰亚胺)分隔开来的导体层(例如铜)。这种封装结构还可以包含从其外表面(与衬底上带有上述各层的表面相对的表面)伸出的导电管脚之类部件,用来插入位于诸如印刷电路板(PCB)之类的第二衬底上的例如金属插座等导电接受装置。这种封装件典型地还包括一个或多个(通常是几个)位于衬底上表面上并根据需要连接于各个导体层的半导件器件(芯片)。在本技术领域中提供了这样一种使用焊料的连接,其工艺是本发明的受让人开发的众所周知和广泛采用的工艺。工业界称此工艺为塌陷可控芯片连接(C-4),该工艺在各种出版物(包括专利)中已有描述,没有赘述之必要。
此处提及的各类型电子封装件的例子在下列美国专利中也有描述:Schaible等人的4430365、Currie等人的4446477、Magdo等人的4805683、Arnold等人的4835593。
对于其上带有电路的各种陶瓷衬底的描述,还可以从下列IBM技术发明公告(TDB)中看到:IBM TDB第22卷第10期(1980年3月)、IBM TDB第32卷第10A期(1990年3月)。
在已知的制造至少包含一个与其电路连接的芯片的MCP封装件的工艺中,开始是在陶瓷的上表面上沉积一个第一金属层。此层一开始是由Cr-Cu-Cr组成的,是用熟知的溅射技术溅射沉积的。然后用一层光致抗蚀剂覆盖此Cr-Cu-Cr层,再经过一系列的光刻步骤(轻度烘焙、曝光、显影和烘培),在Cr-Cu-Cr上形成所需的抗蚀剂图形。然后用熟知的腐蚀操作把下面Cr-Cu-Cr层中的未保护部分的金属除去。接着清除(剥离)掉剩下的抗蚀剂保护图形,以曝露出留在陶瓷上表面上的所需的电路图形。显然,这一图形包括至少一个而最好是几个接触位置,每一接触位置适用于分别电连接到芯片上的一个接触点。然后在下一操作步骤中,在整个留下的包括各接触位置的电路图形上沉积一层电介质(例如聚酰亚胺),工业界称这种沉积为地毯式涂覆(意味着覆盖整个电路)。在聚酰亚胺上执行另一系列光刻步骤以确定窗口(称之为“通道”)图形,然后清除已被显影过的选定部位的介电聚酰亚胺,从而暴露出其下面的电路部分。显然,上述的接触位置也因此而暴露出来了。此时,将聚酰亚胺烘焙成固化状态。在另一种操作中,可用激光剥离来代替构成上述一部分光刻步骤的化学工艺以达到所需的对聚酰亚胺的选择性清除。然后用熟知的腐蚀操作清除掉Cr-Cu-Cr层的上部Cr层,使该层留下的暴露部分(接触位置)由一个上部铜层和一薄层铬所组成,这可以增大Cu-Cr在陶瓷上的附着力。
在下一步制作中,在聚酰亚胺和暴露的导电接触位置上沉积一个第二金属层。采用了熟知的分批蒸发工艺,其结果是再形成一个由Cr-Cu-Cr组成的层。此时采用前述的分批蒸发工艺而不用所述的溅射步骤,这是由于前者的热循环更长,可用以驱散可能残留并可能影响导电层之间的最终互连的溶剂和水汽。然后重复前述的光刻和湿法处理步骤以确定第二导电层所需的第二图形。最后的光刻图形化之后再执行顶部铬腐蚀以选择性地清除原先在该上部导电层中出现的铬。如同下部第一导电层情况中那样,这一第二导电层包括至少一个而最好是几个用于提供芯片连接的接触位置。
上述工艺的结果是在介电陶瓷的上表面形成了至少两个导电层,每层上至少有一个用来例如由上述的焊料分别电连接到芯片的接触点的接触位置,之后,芯片则置于暴露的接触位置上并与之电连接。如将要看到的,这些导电层也是由聚酰亚胺介电层来分隔开的,该介电层在后续的封装操作中如果需要时使二层导电层电学隔离。
上述制造工艺至少有二个缺点。其一是此工艺需要执行几个不同的步骤,需用相当长的时间和使用复杂而昂贵的设备。其二是此工艺要求在选定的位置(第一层与第二导电层中的金属接触的那些接触位置)处形成金属-金属互连。这种互连对电阻的变化很敏感,在制作这类精度要求高的多层电子封装件之类的产品时,这自然是极不可取的。为确保产业界对这类层间互连所要求的可靠性,特殊的控制手段和测试操作是至关重要的。这也增加了最终封装件的总成本。
如此处将要描述的,本发明描述了一种多层电子封装件,其中至少采用了两个导电层,每层都带有分立的接触位置,用于分别与半导体芯片的接触点电连接。值得注意的是,一个层的接触位置以较大的距离(高度)位于介电衬底上表面的上方,但却直接电连接于相应的芯片接触点。如将要描述的,比之前述MCP产品的上述工艺,此类产品的制造工艺能够以较少的步骤和较短的时间来执行。同样值得注意的是,这一工艺得到的产品中无需在分离的金属导体层间的金属-金属互连,从而克服了上述的有关缺点。虽然本发明特别适用于MCP产品的制造,但并不意味本发明只限于此处限定的工艺,本发明也可方便地用于其它类型的衬底封装件,包括那些采用熟知的FR4和其它介电材料作为基本衬底元件的封装件。
可以相信这一电子封装件及其制造工艺代表了本技术领域的一大进步。
因此,本发明的目的是增强电子封装件包括其制造工艺在内的技术。
本发明的另一目的是提供一种电子封装件,它至少包括两个分立的导电层,每层都有各自的接触位置,其中,当将芯片置于衬底上构成其部件时,在向半导体芯片上各个接触点提供直接的电连接的同时,各层的接触位置到下部衬底上表面的距离不同。
本发明的又一目的是提供一种制造这种电子封装件的工艺。
本发明的再一个目的是提供一种工艺和最终封装结构,比之先前所述的情况,它可以用较少的操作步骤和较短的时间来生产,从而对封装件的消费者和生产者来说提供了一种成本优势。
根据本发明的一个方面,提供了一种制造电子封装件的方法,它包含下列步骤:提供一个带有一个第一表面的衬底;在此第一表面提供一个至少包括一个接触位置的电路图形;用介电材料覆盖第一电路图形;在该电介质上提供一个第二电路图形。它包括其本身的位于与第一图形接触位置不同高程处的接触位置;然后清除部分的介电层以暴露出第一层的接触的位置。值得注意的是,当芯片置于衬底上时,不同高程(到衬底上表面之距离)的两种接触位置都用来直接电连接(如焊接)到半导体芯片的相应点上。
根据本发明的另一个方面,提供了一种电路衬底,它包含一个带有一个上表面的介电衬底、在此表面上并包括位于距此表面为第一距离处的第一暴露接触位置的一个第一电路图形、在第一图形上并在其中有一窗口以暴露第一接触位置的一个介电层,以及在介电层上的一个第二电路图形,该图形包括位于距此表面比第一图形的第一接触位置更远的第二距离处的第二接触位置。此第二接触位置也被暴露出来,其暴露出的第一和第二接触位置都用来直接电连接致电半导体芯片的各个接触点。
图1-5示出了根据本发明一个实施例制造电路化衬底的工艺的各个步骤,此衬底设计为用于上述类型的电子封装件;
图6示出了根据上述步骤生产的电路化衬底,它具有一个位于其上并与衬底电连接的电子器件(半导体芯片);以及
图7和8表示分别用来在图6所示封装上两个导电层的最外部分之间提供电连接的引线夹的两个实施例。
结合上述附图参照下列公开和所附权利要求以便更好地了解本发明及其它的目的、优点和功用。
图1-5示出了根据本发明的一种情况制造电路化衬底的各个步骤。不讲自明,此衬底是专门设计用于上述类型的电子封装件结构,特别是用于信息处理系统的。本领域中公认此种封装结构必须满足严格的设计要求。如此处所指出的,本发明是能够做到这一点的,比之产业界已知的许多这类封装结构,还可确保最终结构的生产成本较低而所费时间较少。
在图1中,提供了一个至少包括一个大体平整的上表面13的衬底11。衬底11最好是陶瓷的或氧化铝的,但这不意味着本发明的范围不能用其它材料。在表面13上形成一个导电薄层15,其最好的材料为用溅射工艺三步制作的Cr、Cu和Cr。具体地说,用本领域熟知的标准溅射工艺溅射沉积第一铬层(例如0.08μm厚)。在一例此工艺中,可采用Ulvac公司制造的Ulvac-850系统之类的排成行的(in-line)溅射系统。其它无须赘述。这一第一铬层用来增进下一个金属层对衬底11的附着力。然后在铬上溅射沉积一个4.0μm厚的铜层,接着溅射沉积一个厚度仅为约0.08μm的极薄的铬覆盖层。后续工艺(以下所述),包括局部消除中,层15用作本发明电路化衬底的第一电路图形。
对层15进行一系列的熟知的光刻步骤以确定第一电路图形,该图形包括必要的接触位置以及可能伴随的精细电路连线。如所周知,这种连接位置将用来使第一层最终电连接于诸如半导体芯片17(图6)之类的电器件上各个接触点,芯片则成为根据此处提供的方法形成的电路化衬底的最终封装件的一部分。在这种工艺中,在层15上使用一种合适的光抗蚀剂(例如涂覆),接着对光抗蚀剂加热(烘焙)、曝光(例如用投影晒相仪)、显影(例如用含二甲苯的显影液)、然后再加热(烘焙)。用这种工艺可清除层15的选定区域(图1中未示出),显然,保留下来的部分就构成了衬底11上起始层所需的电路图形。在另一种情况下,可能希望使层15保持大体整体的结构,例如用作接地或供电功能。在较前所述的实施例中,此层可用作信号层。清除部分层15的最佳工艺若需要的话则是腐蚀。无论层15是用作信号层、电源层或接地层,都至少包括一个,最好是几个接触位置作为其部件。在一个实施例中,提供了大约300个这种位置。
腐蚀之后则清除掉所有残留的光抗蚀剂。结果就在衬底11的表面13上形成了所需的最终电路图形。在一个实施例中,此图形的总厚度仅为约4.0μm。
如图2所示,在本发明的下一步骤中,在第一层15的图形上地毯式涂覆一层介电材料19,例如聚酰亚胺。最好用标准涂覆操作施加厚度约为8.0μm(在全部固化之后)的聚酰亚胺。在这一操作过程中,把用潜溶剂冲稀了的聚酰亚胺喷射在部件上并在设置了传送带的炉子中于大约90℃烘焙几分钟,直到聚酰亚胺达到A级固化。这种固化等级(如A、B、C)在本技术中是熟知的,无需赘述。显然本发明不限于聚酰亚胺,在其它聚合物(如特氟隆(E.I.duPont deN-emours公司的一种商标))中也可成功地使用。值得注意的是,在一个例子中,涂覆的聚酰亚胺接着烘焙到一个高的固化态,温度约为365℃。如下面更详细的描述所指出,聚酰亚胺的高固化态有利于允许对聚酰亚胺的后续处理。
在图3所示的下一步骤中,在固化的聚酰亚胺19上沉积一个第二金属层21。达到这一沉积的最好工艺是采用上述的溅射操作。与层15一样,此第二层最好也由Cr、Cu和Cr组成,且最好用与层15相同的方法和设备来沉积。然而在此第二层21中,采用了8μm的铜。因此,此处指出的工艺能够最大限度地利用设备,从而在这方面确保节省成本。如所指出,这一溅射操作是在相当高的温度(例如400℃以上的温度)下进行的。重要的是已高度固化的下部聚酰亚胺能够经受所用时间内的这种温度。此外,聚酰亚胺未曾经历一系列通常执行腐蚀的湿法化学处理(如产业界熟知的相似工艺中发生的那样)。这种腐蚀可能加速吸水材料聚酰亚胺中的水吸收,引起在后续金属沉积过程中水汽排出现象。本发明消除了这种可能性。
第二层21就位后,进行一系列光刻步骤,最好与制作层15上的第一图形(倘若形成了这一图形且不是如图1-3所示的整体(Solid)层)所用的步骤相似。此时,把光抗蚀剂地毯式涂覆在金属层21上,接着进行第一次烘焙,再进行曝光和显影步骤。然后后续烘焙。这些步骤最好与目前熟知的用于诸如陶瓷和FR4材料之类衬底的电路化步骤相似,无需赘述。也可使用产业界熟知的设备,这说明了本发明为何能节省成本和时间的又一个例子。其结果是一种分立导电元件23例如线、焊点等的图形。如同层15的第一图形,此图形也至少包括一个且最好是许多(例如700个)接触位置(在附图中标以参考号23’),就象第一层15的接触位置一样,它们是特别设计用来电连接到芯片17的各个接触点(图6)的。在一个例子中,接触位置23’具有大体圆柱形的结构,直径仅为约100μm,总厚度仅为约8.0μm。值得注意的是,层15和23若为前述的Cr-Cu-Cr材料构成,则二者仍含有保护性铬的顶部子层。亦即,在前面工艺中,包括加入聚酰亚胺19之前,这一子层未曾从第一层15上除去。于是,在本发明的最佳实施例中,每一个层15和21(元件23和23’)都由Cr-Cu-Cr组成。然而在层15的情况下,由于这些层可能有不同的使用,此时的总厚度可能稍小于层21。例如,若此层要用作接地或电源层,则可能希望较薄的层15,而若要将层21用作信号层,则层21可能要较厚。不管如何,本发明足以适应这些层厚度变化的需要。在一个实施例中,接触位置23’同最近邻元件23之间的距离仅为约35μm,再一次表明本发明的导电电路可获得高的密度。
在图4的实施例中,显然所有留下的光抗蚀剂(包括残留的)均已被消除,留下的结构大致如图4所示。
在本发明的下一步骤中,如图5所示,清除了选定部分的聚酰亚胺19,在第一层15上留下一系列暴露的下部部分25。值得注意的是,暴露的部分25要用作层15所需的接触位置,从而将层15连接到芯片17上相应的选定接触点。在一个实施例中,提供了总共300个这种暴露区,通常彼此分开仅约230μm的距离。考虑到上述位置的区段23和23’之间的间距,从一个区段(23或23’)到最近的下部暴露区段25之间的总距离仅为大约35μm。在一个例子中,每一暴露区也是大致的环状结构,其直径仅为约100μm。
清除聚酰亚胺指定部位从而暴露出层15上的区段25的最好方法是采用激光剥离。在这种工艺中,可使用激发物激光器,激光器也可同相关的掩模(如介电质)一并使用以剥离所需的连接点。用来执行此工艺的最好设备是熟知的连接于光束整形光路的工业激光器。激光剥离过程在仅为约10-15秒的时间内即可完成,留下上述整个暴露的区段25。值得注意的是,在这一工艺过程中,下部金属层15用来保护衬底,若采用聚合物或其它对热更为敏感的材料时,这是一个非常重要的特点。
值得注意的是,暴露区25和顶部区23’的上表面分别位于表面13之上二个不同高程处。在一个实施例中,区域25位于仅约为4.0μm的距离(D1)处,而上部区域23’各位于约20μm的距离(D2)处,亦即为较近区段距离的五倍。这表示了本发明的一个非常重要的特征,因为显然二种区段(接触位置)都例如通过适当的导电焊料之类的材料而用来直接连接到各芯片接触点。由于不存在与本发明独特的指导相反的将层21直接置于层15上时将出现的金属-金属(例如铜对铜或铜对铬)界面,从而克服了上文提到过的潜在的不利影响,例如通过界面的不一致的电阻,这将要求在一切可能的情况下进行相对多的检验及可能的校正措施。
上述步骤之后,希望从层15以及21上(亦即只是其暴露部分)都清除铬顶部(假设采用了Cr-Cu-Cr)。于是,在图5的实施例中,对区域23’以及下部层15的暴露区25的上表面进行处理。由于其上提供了保护(如光致抗蚀剂),区域23可能未被处理。实现这一清除的最好方法是本领域熟知的腐蚀工艺。结果是选定的暴露表面由铜组成,而铬已被清除。
在图6中,半导体芯片17置于衬底11之上,并用许多焊接元件31直接电连接到暴露区域23’和25。实现这一步的最好方法是由本发明受让人开发并广泛使用的上述C-4焊接工艺。也可采用其它连接工艺,本发明并不限于此特定工艺。最好的焊料是工业上所用的Sn∶Pb=3∶97的焊料。各焊料元件31开始都沉积在芯片17下表面上各个接触点(导体)上(未示出)。这种导体接触点在半导体产业中是熟知的,无需赘述。在最佳实施例中,对每一区域23’和25,使用了相同尺寸的焊料量(例如6μg),从而表明本发明对采用现行熟知的芯片-焊料组合(这种组合对每个芯片接触点通常使用等量的焊料)的可适应性。但本发明并不受此限制,也可以使用不等量焊料(例如在区域25位置处使用较大量的焊料,而在较近距离(从芯片下表面算起)的区域23’处使用较少焊料)。
在一较佳方法中,用熟知的工业方法(焊料撞击)使每一焊接元件都附着(焊接)在相应的芯片位置上。然后例如用电视摄象机和相关的精密设备,将芯片相对于衬底11反转并对准,特别要确保各焊料元件和相关暴露的接触位置之间的精确对准。一经定位(使焊料元件与各接触位置接合),就对衬底-芯片组合体加热,例如在氮回流炉中加热到约350℃的温度,维持约3分钟。在所有希望的位置就发生焊料回流并获得完好的电连接。采用工业界熟知的包封技术可进一步增加芯片对封装的可靠性。几类已知的包封材料可用于各种焊料连接。
在图7和8中,指出了用来使本发明衬底的选定部分电连接于其它电路(例如诸如印刷电路板PCB之类的分立电路化衬底41上的电路)的两个不同的实施例。在本发明的较佳实施例中,将带有连接于其上从而组成可称之为第一层电子封装组件的芯片17的衬底11电连接到这种外部附加衬底上,特别是倘若本发明的最终用途是在计算机中的情况。图7和8的实施例代表了实现此目的的相当简单而有效的方法。然而显然,图7和8所示的方法并不对本发明构成限制。几个其它的变通方法,包括例如焊球附着法、导体管脚法、引线焊接法等等,都可以成功地使用。
在图7中,示出了一个例如不锈钢或铜的引线夹51,它被直接焊接到上层21的外围部分处(从图4-6所示的内部)。在一个实施例中,可以使用总数为376个这种引线夹,而且本发明不限于使用此处所示的这一种。如所示,每个引线夹的形状都是弯曲的,且其厚度最好是仅为约0.2mm。其下部(53)设计成位于PCB41上的焊点或相似的导体55上并与其直接连接(例如用焊料57’)。在图7中,引线夹只在上层21的外围部分处焊接(用焊料57)于其上。在一个实施例中,为此采用了Sn∶Pb=10∶90的焊料。焊料最好先放在引线夹上,然后使引线附着位置和焊料进行直接接合。将引线夹-衬底置于上述的炉子中,在约350℃温度下持续约3分钟即完成回流。引线夹51和芯片17附着的最好方法是采用焊料31(芯片和位置23’及25之间)和57同时回流。
在图8的实施例中,引线夹51焊接到衬底的第一层15(例如接地层),而不是焊接到层21。在选择性清除部分覆盖用聚酰亚胺19从而暴露部分下部层15之后,即可实现。这一步(清除)最好与暴露区段25的清除聚酰亚胺的操作同时完成。此步骤最好采用激光剥离。
于是指出并描述了一种新的电路化衬底及其制造方法,其中获得了位于最少两个不同高程层面上的衬底接触位置之间的有效的电连接。本发明的方法可方便地适用于额外导电层的采用,而且本发明不限于采用此处所述的二个这种层。比之现有技术中很多已知的方法,包括此处较早描述的方法来说,此处所述的方法能够以最大限度利用工艺设备的状态来执行,且执行的步骤较少,时间较短。对封装件的购买者来说,本发明代表着一种成本上的节省。
虽然已描述了本发明最佳实施例所考虑的问题,但对本技术领域的熟练人员来说,显而易见,可以作出各种改变和修正不超越所附权利要求书所规定的本发明的范围。
Claims (25)
1.一种制造适合于电连接到电子器件的电路化衬底的方法,所述方法包括:
提供一个带有一第一表面的衬底;
在上述衬底的上述第一表面上提供一个第一电路图形,上述图形至少包括一个接触位置;
用一层介电材料把上述包括上述接触位置的第一电路图形基本覆盖起来;
在上述介电材料层上提供一个第二电路图形,上述第二电路图形至少包括一个接触位置;
清除至少一部分的上述介电材料层以暴露出上述第一电路图形的所述接触位置,上述第一和第二电路图形的所述接触位置被暴露出来且位于相对于上述衬底的上述第一表面的不同高程处,上述接触位置适合于分别与上述电子器件直接电连接。
2.如权利要求1的方法,其特征是:上述第一电路图形采用在上述衬底的上述第一表面上沉积至少一个金属层的方法来制成。
3.如权利要求2的方法,其特征是:上述第一电路图形采用光刻工艺形成,上述工艺包括在上述金属层上沉积一层光致抗蚀剂,然后使上述光致抗蚀剂的选定区域曝光和显影以确定上述电路图形。
4.如权利要求1的方法,其特征是:把上述介电材料地毯式涂覆在上述第一电路图形上。
5.如权利要求4的方法,其特征是:上述介电材料是一种聚合物,且上述聚合物在沉积于上述第一电路图形上之后将其固化。
6.如权利要求1的方法,其特征是:上述第二电路图形用在上述介电材料层上沉积至少一个金属层的方法来形成。
7.如权利要求6的方法,其特征是:用溅射方法来实现在上述介电材料层上沉积至少一个金属层的步骤。
8.如权利要求6的方法,其特征是:上述第二电路图形用光刻工艺形成,且上述工艺包括在上述金属层上沉积一层光致抗蚀剂材料,然后使上述光致抗蚀剂的选定区域曝光和显影以确定上述第二电路图形。
9.如权利要求1的方法,其特征是:用激光剥离来清除上述介电材料层的上述部分。
10.如权利要求1的方法,其特征是进一步包括下列步骤:把上述电子器件电连接到上述第一和第二电路图形的上述暴露的接触位置上。
11.如权利要求10的方法,其特征是:用焊接方法来实现上述电子器件同上述接触位置的上述电连接。
12.一种适合于与电子器件电连接的电路化衬底,上述衬底包含:
一个包括一个上表面的介电衬底;
一个在上述上表面上并在离上述上表面为第一距离处至少有一个暴露的接触位置的第一电路图形;
一层位于上述第一电路图形上的介电材料,其中至少包括一个位于上述暴露的接触位置附近的窗口,用来暴露上述接触位置;
一个位于上述介电材料层上的第二电路图形,其中在离上述介电衬底的上述上表面为第二距离处至少有一个暴露的接触位置,此接触位置同上述第一电路图形的上述暴露接触位置分隔开一个预定距离,上述第二距离大于上述第一距离,上述第一和第二电路图形的上述暴露的接触位置适合于分别直接与电子器件电连接。
13.如权利要求12的电路化衬底,其特征是:上述介电衬底由陶瓷构成。
14.如权利要求12的电路化衬底,其特征是:上述第一电路图形由铜构成。
15.如权利要求14的电路化衬底,其特征是:上述第一电路图形为基本上整体的结构。
16.如权利要求12的电路化衬底,其特征是:上述介电材料层由聚酰亚胺构成。
17.如权利要求16的电路化衬底,其特征是:上述聚酰亚胺基本上完全固化。
18.如权利要求16的电路化衬底,其特征是:上述介电材料层中邻近上述第一电路图形的上述一个暴露的接触位置的上述窗口的剖面结构大致为锥形。
19.如权利要求12的电路化衬底,其特征是:上述第二电路图形由铜构成。
20.如权利要求12的电路化衬底,其特征是:上述第二电路图形由许多线条构成,上述第一电路图形的上述暴露的接触位置位于下面并大致在离上述上表面为上述第一距离处的二条上述线条之间。
21.如权利要求12的电路化衬底,其特征是:还包括一个其上至少带有两个接触点的电子器件,上述接触点中的选定者被电连接到上述第一和第二电路图形的相应的上述接触位置上。
22.如权利要求21的电路化衬底,其特征是:还包括至少两个焊料元件,上述焊料元件中被选定的元件提供了上述电子器件的上述接触点和上述第一与第二电路图形的上述各个暴露的接触位置之间的电连接。
23.如权利要求12的电路化衬底,其特征是:还包括一个位于上述暴露的接触位置上并至少与其中一个位置相接触的焊料元件,而且还包括一个固定在上述电路化衬底并电连接到上述焊料元件的导电夹。
24.如权利要求23的电路化衬底,其特征是:还包括一个第二电路化衬底,上述导电夹将上述第一电路化衬底电连接到上述第二电路化衬底。
25.如权利要求24的电路化衬底,其特征是:上述第二电路化衬底包括一印刷电路板。
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US233193 | 1994-04-26 | ||
US08/233,193 US5712192A (en) | 1994-04-26 | 1994-04-26 | Process for connecting an electrical device to a circuit substrate |
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EP (1) | EP0683513A1 (zh) |
JP (1) | JP2862126B2 (zh) |
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CN (1) | CN1079582C (zh) |
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CN1560911B (zh) * | 2004-02-23 | 2010-05-12 | 威盛电子股份有限公司 | 电路载板的制造方法 |
CN114365584A (zh) * | 2020-06-29 | 2022-04-15 | 庆鼎精密电子(淮安)有限公司 | 线路板及其制作方法 |
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JPH07297321A (ja) | 1995-11-10 |
US5712192A (en) | 1998-01-27 |
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MY116347A (en) | 2004-01-31 |
JP2862126B2 (ja) | 1999-02-24 |
CN1079582C (zh) | 2002-02-20 |
EP0683513A1 (en) | 1995-11-22 |
US5612573A (en) | 1997-03-18 |
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