CN111930386B

CN111930386B - PATTERN file compiling method and device and electronic equipment

Info

Publication number: CN111930386B
Application number: CN202011018745.2A
Authority: CN
Inventors: 杨坤; 邓标华
Original assignee: Wuhan Jinghong Electronic Technology Co ltd; Wuhan Jingce Electronic Group Co Ltd
Current assignee: Wuhan Jinghong Electronic Technology Co ltd; Wuhan Jingce Electronic Group Co Ltd
Priority date: 2020-09-24
Filing date: 2020-09-24
Publication date: 2020-12-29
Anticipated expiration: 2040-09-24
Also published as: CN111930386A

Abstract

The invention discloses a PATTERN file compiling method, a PATTERN file compiling device and electronic equipment, wherein the method comprises the following steps: classifying each line of instructions in the PATTERN file, and generating an instruction query table by taking keywords as key values; the instruction lookup table stores the mapping relation between the keywords and the types of the classification instructions at each level; preprocessing the PATTERN file, storing register statements corresponding to each module in the PATTERN file in a register list, and storing test vectors in a vector list; traversing each instruction in the register list and the vector list corresponding to each module, searching a corresponding classification instruction in an instruction query table according to a keyword of the instruction, and storing the classification instruction in a data structure body; the invention grades the instructions through the instruction query table, and stores the instructions in the register list and the vector list generated by preprocessing into the data structure body according to the grading condition based on the instruction query table, thereby greatly reducing the difficulty and complexity of coding development.

Description

PATTERN file compiling method and device and electronic equipment

Technical Field

The invention belongs to the technical field of semiconductor testing, and particularly relates to a PATTERN file compiling method and device and electronic equipment.

Background

The Test of semiconductor memory (semiconductor-controller memory) involves repeated operations to different addresses of the memory, such as Block/Page, etc., and if a Test file is written according to a conventional Automatic Test Equipment (ATE) Test, a large amount of space is required to store a Test vector (PATTERN), so the semiconductor memory Test generally uses an algorithm PATTERN Generator (ALPG) to generate signals required by a chip in real time, and a user only needs to write an operation to be executed with a short loop jump instruction. In order to be able to specify the writing of these instructions, a specification of a set of languages is required, which can be programmed to check for errors therein, and which can generate a binary file for the FPGA.

At present, the PATTERN file industry commonly uses a structured text file similar to assembly grammar, and has the advantages of being particularly suitable for setting commands of loop, jump and operation registers, and having the defects of high complexity of compiling and developing and poor expansibility due to more commands and the need of combining hardware.

Disclosure of Invention

Aiming at least one defect or improvement requirement in the prior art, the invention provides a PATTERN file compiling method, a PATTERN file compiling device and electronic equipment, aiming at compiling a test PATTERN file in a structured text format into a binary file and solving the problems of high complexity and poor expansibility of PATTERN compiling and developing.

To achieve the above object, according to a first aspect of the present invention, there is provided a method for compiling a patern file, the method comprising the steps of:

classifying each line of instructions in the PATTERN file, and generating an instruction query table by taking keywords as key values; the instruction lookup table stores the mapping relation between the keywords and the types of the classification instructions at each level;

preprocessing the PATTERN file, storing register statements corresponding to each module in the PATTERN file in a register list, and storing test vectors in a vector list;

and traversing each instruction in the register list and the vector list corresponding to each module, searching a corresponding classification instruction in an instruction lookup table according to the keyword of the instruction, and storing the classification instruction in a data structure body.

Preferably, in the method for compiling a patern file, the classification instruction is a code that can be recognized by an algorithm PATTERN generator.

Preferably, in the method for compiling a patern file, each patern file corresponds to one data structure, and the number of modules and the patern length are recorded in a header of the data structure.

Preferably, in the method for compiling a patern file, the preprocessing the patern file specifically includes:

reading the instructions in the PATTERN file in sequence by taking a minimum compiling unit as a unit, and if the minimum compiling unit has matched keywords in an instruction lookup table, sequentially reading the multistage instructions corresponding to the keywords; if not, continuing to read the next minimum compiling unit;

during the above reading process, register declarations corresponding to each module in the PATTERN file are stored in the register list and the test vectors are stored in the vector list.

Preferably, in the method for compiling a patern file, the sequentially reading the multiple levels of instructions corresponding to the keyword specifically includes:

when reading each level of instructions, judging whether the next minimum compiling unit needs to be read continuously according to the type of each level of classified instructions, if so, continuously reading the next minimum compiling unit and judging whether the next level of classified instructions exist; if not, directly reading the next-level classification instruction.

Preferably, the patern file compiling method further includes:

and deleting spaces between two adjacent characters in the same keyword in the register statement and the test vector, and storing the spaces in a corresponding list.

Preferably, the patern file compiling method further includes:

and converting the data structure into a binary file required by an algorithm mode generator.

According to a second aspect of the present invention, there is also provided a patern file compiling apparatus, including:

the system comprises a configuration module, a search module and a search module, wherein the configuration module is used for classifying instructions of each line in a PATTERN file and generating an instruction query table by taking key words as key values; the instruction lookup table stores the mapping relation between the keywords and the types of the classification instructions at each level;

the preprocessing module is used for preprocessing the PATTERN file, storing the register statement corresponding to each module in the PATTERN file in a register list, and storing the test vector in a vector list;

and the compiling module is used for traversing each instruction in the register list and the vector list corresponding to each module, searching the corresponding classification instruction in the instruction query table according to the key word of the instruction and storing the classification instruction in the data structure body.

Preferably, in the above patern file compiling apparatus, each of the patern files corresponds to one data structure, and the number of modules and the patern length are recorded in a header of the data structure.

Preferably, in the patern file compiling device, the preprocessing module reads the instructions in the patern file in sequence by using the minimum compiling unit as a unit, and if the minimum compiling unit has a matching keyword in the instruction lookup table, sequentially reads the multi-level instructions corresponding to the keyword; if not, continuously reading the next minimum compiling unit and judging whether the combination of the minimum compiling units has matched keywords in the instruction query table;

during the reading process, register declarations corresponding to each module in the PATTERN file are stored in a register list and test vectors are stored in a vector list.

Preferably, in the above patern file compiling device, when reading each level of instruction, the preprocessing module determines whether to continue to read in the next minimum compiling unit according to the type of each level of classification instruction, and if so, continues to read in the next minimum compiling unit and determines whether there is a next level of classification instruction; if not, directly reading the next-level classification instruction.

Preferably, in the above patern file compiling apparatus, the preprocessing module deletes spaces between two adjacent characters in the same keyword in the register statement and the test vector, and stores the spaces in the corresponding list.

According to a third aspect of the present invention, there is also provided an electronic device, comprising at least one processing unit, and at least one storage unit, wherein the storage unit stores a computer program, which, when executed by the processing unit, causes the processing unit to perform any of the steps of the patern file compiling method.

In general, compared with the prior art, the above technical solution contemplated by the present invention can achieve the following beneficial effects:

(1) the invention classifies the instructions of each row in the PATTERN file, generates the instruction query table by taking the key words as key values, and the instruction query table flexibly classifies the instructions; the PATTERN file is preprocessed to generate a register list and a vector list, and then instructions in the register list and the vector list are stored in a data structure body in a grading mode according to an instruction query table, so that the difficulty and complexity of coding development are greatly reduced through instruction grading compilation.

(2) The size of a Pattern file analyzed by the method corresponds to a C + + data structure, the size of the Pattern file can be known through the head of the data structure, and the temporary binary file can be read back conveniently, so that the function of the Pattern file can be expanded conveniently.

Drawings

Fig. 1 is a flowchart of a patern file compiling method according to an embodiment of the present invention;

FIG. 2 is a schematic flow chart of a pre-processing procedure provided by an embodiment of the present invention;

FIG. 3 is a flow chart of a data structure generation process provided by an embodiment of the invention;

fig. 4 is a logic block diagram of a patern file compiling apparatus according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

Fig. 1 is a flowchart of a method for compiling a patern file according to this embodiment, and referring to fig. 1, the method includes the following steps:

s1: classifying each line of instructions in the PATTERN file, and generating an instruction query table by taking keywords as key values; the instruction lookup table stores the mapping relation between the keywords and the types of the classification instructions at all levels;

at present, the patern file for testing semiconductor memories is a structured text file, generally composed of the following parts:

MPAT and END fields indicating the start and END of the procedure;

REGISTER declaration, mainly making REGISTER initialization;

the model BEGIN and model END MODULEs define that there may be multiple models, and the content between START and STPS of a model is a line-to-line vector, each line vector containing at least one instruction, including but not limited to a control instruction, a jump instruction, a data instruction, an address instruction, etc.

The following is an example of a PATTERN file:

MPAT MSAMPLE

REGISTER

XMAX = #1F

YMAX = #1F

IDX1 = #3FE

CPE1 = R

DRE1 = W

MODULE BEGIN

START #0

NOP XB<0 YB<0 TP<0

ST0： JNI1 ST0 X<XB Y<YB XB<XB+1 YB<YB+1^BX W C0 TS1

ST1： JNI1 ST1 X<XB Y<YB XB<XB+1 YB<YB+1^BX R C0 TS2

STPS

MODULE END

END

in this embodiment, first, instructions in each line in the PATTERN file are classified, and an instruction lookup table is generated by using a keyword as a key value, as shown in table 1:

TABLE 1 instruction look-up table

Key with a key body	First order classification	Two stage classification	Three-level classification
				“REGISTER”	ALPG_REGISTER
“MPAT”	ALPG_MPAT	0x00
				“END”	ALPG_MPAT	0x01
“IDX1”	ALPG_REG	ALPG_REG_SEQ	0x00
				“IDX2”	ALPG_REG	ALPG_REG_SEQ	0x01
“XB<XB”	ALPG_SET	ALPG_ADD_XBASE	0x00
				“XB<XB+”	ALPG_SET	ALPG_ADD_XBASE_D	0x09
“XB<XB-”	ALPG_SET	ALPG_ADD_XBASE_D	0x0A

Only part of the contents of the instruction lookup table are shown in table 1, the key in the instruction lookup table may be one or a plurality of consecutive tokens (a word or symbol in the text is a meaningful minimum unit in the compiling process), the corresponding value is a definition of the instruction classification, the number of stages of the instruction classification is not particularly limited, and depends on the specific composition of each instruction and different classification strategies; as shown in table 1, in this embodiment, the instruction is classified into at most three stages, or may be classified into only one stage or two stages, the value under each stage of classification is used to indicate the type of the corresponding classification instruction, and the instruction lookup table is used to store the mapping relationship between the key of the instruction and the type of the classification instruction at each stage; the classification instructions at each level are codes recognizable by the algorithm pattern generator.

The instructions are classified in multiple stages through the instruction query table, so that codes are conveniently realized, the instruction query table is configured in advance and stored, and the instruction query table can be used in the subsequent processing and compiling processes of the PATTERN files.

S2: preprocessing a PATTERN file, storing register statements corresponding to each module in the PATTERN file in a register list, and storing test vectors in a vector list;

traversing each character in the PATTERN file, storing subsequent contents into a REGISTER list when a REGISTER keyword is read, storing the subsequent contents into a vector list according to lines after a START keyword is read, and storing the subsequent contents into the vector list according to lines, wherein the storing process is as shown in FIG. 2, specifically:

reading the instructions in the PATTERN file in sequence by taking a minimum compiling unit as a unit, and if the minimum compiling unit has matched keywords in an instruction lookup table, sequentially reading the multistage instructions corresponding to the keywords; when reading each level of instructions, firstly, judging whether the next minimum compiling unit needs to be read continuously according to the type of each level of classification, if so, continuously reading the next minimum compiling unit, and then judging whether the next level of classification instructions exist. If the key word matched with the currently read minimum compiling unit is not inquired in the instruction inquiry table, continuously reading the next minimum compiling unit; and if the combination of the plurality of minimum compiling units which are read continuously has a matched key word in the instruction lookup table, sequentially reading the multistage instructions corresponding to the key word.

For example: when the 'XB < XB +' is read in the PATTERN file, a table look-up finds that the matched key words exist in the instruction look-up table, and the query table can query to obtain the instruction 0x09 under the ALPG _ ADD _ XBASE _ D category under the ALPG _ SET category, the key words and the query are combined and stored in a vector list after being queried into a multi-stage classification instruction.

As a preferred example, in the process of storing the register statement into the register list and the test vector into the vector list, deleting a space between two adjacent characters in the same keyword in the register statement and the test vector, and then storing the deleted space into the corresponding list, wherein the stored content is a key value which can be directly inquired from the instruction inquiry table, and syntax errors in the file are eliminated through the step; this step need not be performed if there is no space between two adjacent characters in the keyword itself.

Through the preprocessing process, a register list and a vector list are generated correspondingly for each Module in the PATTERN file, and the number of the modules in the PATTERN file and the number of PATTERNs of each Module are obtained.

S3: traversing each instruction in the register list and the vector list corresponding to each module, searching a corresponding classification instruction in an instruction query table according to the keyword of the instruction, and storing the classification instruction in a data structure body;

fig. 3 is a flowchart of a data structure generating process provided in this embodiment, and referring to fig. 3, data instructions in the register list and the vector list generated by preprocessing are continuously analyzed, first, each instruction in the register list corresponding to each module is traversed, a classification instruction corresponding to the instruction is searched in the instruction lookup table according to a keyword of the instruction, and the classification instruction is stored in the data structure; after processing of each instruction in the register list is completed, traversing each instruction in the vector list corresponding to each Module, searching a corresponding classification instruction in an instruction query table according to a keyword of the instruction and storing the classification instruction in a data structure, and adding a record Pattern in a corresponding Module in the data structure; and after the processing of one Module is finished, entering the processing process of the next Module until all the modules in the PATTERN file are processed, and obtaining a data structure body, wherein the organization type of the data structure body is not particularly limited, and a C/C + + data structure is generally selected.

It should be noted that, the processing order of the register list and the vector list is not limited in sequence, and the register list may be processed first, or the vector list may be processed first; since the order of the register list in the Pattern file is advanced, the present embodiment selects the priority handling register list.

In this embodiment, each PATTERN file is processed to obtain a corresponding data structure, and the number of modules and the PATTERN length information are recorded in the header of the data structure, so that the data structure is converted into a binary file required by the algorithm PATTERN generator. The size of the data structure body can be known through the head of the data structure body, and the temporary binary file can be read back conveniently, so that the function can be expanded conveniently.

And finally, downloading the compiled binary file into the ATE to control an algorithm pattern generator ALPG in the ATE to send an address/command to the memory chip and apply a level signal to a control pin so as to realize the test of the semiconductor memory.

Example two

The embodiment provides a patern file compiling device, which can be implemented in a software and/or hardware manner, and can be integrated on an electronic device to implement the patern file compiling method in the first embodiment; referring to fig. 4, the compiling apparatus includes a configuration module, a preprocessing module, and a compiling module; wherein,

the configuration module is used for classifying the instructions of each line in the PATTERN file and generating an instruction query table by taking the keywords as key values; the instruction lookup table stores the mapping relation between the keywords and the types of all levels of classification instructions;

the preprocessing module is used for preprocessing the PATTERN file, storing register statements corresponding to each module in the PATTERN file in a register list, and storing test vectors in a vector list; the preprocessing module reads the instructions in the PATTERN file in sequence by taking a minimum compiling unit as a unit, and if the minimum compiling unit has matched keywords in an instruction lookup table, the preprocessing module reads the multistage instructions corresponding to the keywords in sequence; if not, continuously reading the next minimum compiling unit and judging whether the combination of the minimum compiling units has matched keywords in the instruction query table; during the reading process, register declarations corresponding to each module in the PATTERN file are stored in a register list and test vectors are stored in a vector list.

In addition, the preprocessing module deletes spaces between two adjacent characters in the same keyword in the register statement and the test vector and stores the spaces into a corresponding list.

The compiling module is used for traversing each instruction in the register list and the vector list corresponding to each module, searching the corresponding classification instruction in the instruction query table according to the keyword of the instruction and storing the classification instruction in the data structure body; each PATTERN file corresponds to a data structure, and the head of the data structure records the number of modules and the PATTERN length.

For specific functions implemented by the functional modules, reference is made to the first embodiment, and details are not described here.

EXAMPLE III

The present embodiment further provides an electronic device, which includes at least one processor and at least one memory, where the memory stores a computer program, and when the computer program is executed by the processor, the processor executes the steps of the patern file compiling method in the first embodiment, and the specific steps refer to the first embodiment and are not described herein again; in this embodiment, the types of the processor and the memory are not particularly limited, for example: the processor may be a microprocessor, digital information processor, on-chip programmable logic system, or the like; the memory may be volatile memory, non-volatile memory, a combination thereof, or the like.

The electronic device may also communicate with one or more external devices (e.g., keyboard, pointing terminal, display, etc.), with one or more terminals that enable a user to interact with the electronic device, and/or with any terminals (e.g., network card, modem, etc.) that enable the electronic device to communicate with one or more other computing terminals. Such communication may be through an input/output (I/O) interface. Also, the electronic device may communicate with one or more networks (e.g., a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public Network, such as the internet) via the Network adapter.

It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A patern file compiling method, comprising:

traversing each character in the PATTERN file, storing register statements corresponding to each module in the PATTERN file in a register list, and storing test vectors in a vector list;

2. The patern file compilation method of claim 1, wherein each patern file corresponds to a data structure, and wherein a header of the data structure records a number of modules and a patern length.

3. The method of patern file compilation as recited in claim 1, wherein traversing each character in the patern file, storing register declarations corresponding to each module in the patern file in a register list, and storing test vectors in a vector list, comprises:

reading the instructions in the PATTERN file in sequence by taking a minimum compiling unit as a unit, and if the minimum compiling unit has matched keywords in an instruction lookup table, sequentially reading the multistage instructions corresponding to the keywords; if not, continuously reading the next minimum compiling unit and judging whether the combination of the minimum compiling units has matched key words in the instruction query table;

4. The method for compiling a PATTERN file as claimed in claim 3, wherein the sequentially reading the plurality of levels of instructions corresponding to the key is specifically:

5. The PATTERN file compilation method of claim 4, further comprising:

6. The patern file compilation method of claim 1, further comprising:

7. A patern file compiling apparatus, comprising:

the preprocessing module is used for traversing each character in the PATTERN file, storing the register statement corresponding to each module in the PATTERN file in a register list and storing a test vector in a vector list;

8. The patern file compiling device of claim 7 wherein the preprocessing module reads the instructions in the patern file in sequence in units of a minimum compiling unit, and if the minimum compiling unit has a matching keyword in the instruction look-up table, reads the multiple levels of instructions corresponding to the keyword in sequence; if not, continuously reading the next minimum compiling unit and judging whether the combination of the minimum compiling units has matched keywords in the instruction query table;

9. The patern file compiling device of claim 8, wherein when reading each level of instructions, the preprocessing module determines whether to continue reading in the next smallest compiling unit according to the type of each level of classified instructions, and if so, continues reading in the next smallest compiling unit and determines whether there is a next level of classified instructions; if not, directly reading the next-level classification instruction.

10. An electronic device, comprising at least one processing unit and at least one memory unit, wherein the memory unit stores a computer program that, when executed by the processing unit, causes the processing unit to perform the steps of the method of any of claims 1 to 6.