CN111881079A - Clock time processing method and device based on digital signal processor and hardware acceleration unit - Google Patents
Clock time processing method and device based on digital signal processor and hardware acceleration unit Download PDFInfo
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- CN111881079A CN111881079A CN202010730038.XA CN202010730038A CN111881079A CN 111881079 A CN111881079 A CN 111881079A CN 202010730038 A CN202010730038 A CN 202010730038A CN 111881079 A CN111881079 A CN 111881079A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
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- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
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- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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Abstract
The invention discloses a clock time processing method and a clock time processing device based on a digital signal processor and a hardware acceleration unit. By expanding the general digital signal processor, a hardware acceleration unit adaptive to the time-frequency field processing is added, and the high-performance long-life-cycle clock time processing system which is extensible and has adaptability to the future protocol updating is realized. The invention has flexible expandability, and can adopt a software adaptation method to adapt to future protocol upgrading and performance enhancement aiming at the clock field.
Description
Technical Field
The invention relates to the fields of satellite navigation, time synchronization, instruments and meters, weapon control and the like, in particular to a clock time processing method and a clock time processing device based on a digital signal processor and a hardware acceleration unit.
Background
The fields of satellite navigation, time synchronization, instrumentation, weapon control, etc., require clock time processing with higher accuracy and faster alignment.
In the prior art, the clock alignment processing with ns-level precision is realized by adopting an FPGA (field programmable gate array) which is used as a realization method for quickly adapting to the market, and the method has the following defects:
the FPGA configuration unit is complex, the original test cost is high, and manufacturers usually have choices based on the cost, and have natural reliability problems of insufficient test, soft failure and the like.
And 2, the phase-locked loop provided by the FPGA technology is not high in jitter performance and cannot meet the high-performance requirement.
Based on the defects, the system adopts an SOC architecture, is internally provided with a DSP/CPU, and has the advantages of concentrated test on an instruction system and a memory and high reliability and fault protection. The performance which is several times better than that of the FPGA scheme can be obtained by internally arranging a special phase-locked loop and an event input and output unit.
Disclosure of Invention
The present invention aims to solve the above problems and provide a clock time processing method based on a digital signal processor and a hardware acceleration unit.
The invention aims to solve the problems and provides a device of a clock time processing method based on a digital signal processor and a hardware acceleration unit, which has reasonable design and convenient operation.
In order to achieve the purpose, the invention adopts the following technical scheme: a clock time processing method based on a digital signal processor and a hardware acceleration unit,
when an event arrives, the receiving unit refers to the time scale bus, marks a time scale on the event and becomes a time event;
the DSP/CPU obtains various time events directly through the receiving unit or indirectly through the special processing unit, obtains estimation parameters through algorithm processing such as abnormity judgment, filtering and the like, and makes various actions according to the estimation parameters, such as directly controlling the I type or II type sending unit to send an event message or indirectly controlling the special processing unit to trigger a specific protocol to stipulate the actions.
According to the method, the clock time processing device based on the digital signal processor and the hardware acceleration unit is provided, a DSP/CPU and hardware acceleration unit architecture is adopted, wherein the hardware acceleration unit comprises:
(1) a set of time stamp buses and at least one set of general data buses;
(2) at least one time stamp unit. A sufficiently large counter is driven, incremented or cyclically incremented during the assertion period, based on an external temporal physical reference. The value of this counter is communicated to other units with a fixed delay through a time stamp bus;
(3) the receiving unit can identify the time mark characteristics of the incoming signals, refers to the time scale on the current time scale bus, accurately reports the time of the incoming signals, and outputs integer or real time by taking the time scale as a unit;
(4) at least one transmitting unit with passive transmission of accurate measurements, which may be a class I transmitting unit or a class II transmitting unit. The class I sending unit is defined as that the class I sending unit is directly triggered by a receiving event or a DSP processor to send a time mark bus without waiting, but a sent signal sequence or message is measured by taking the time scale of the time mark bus as a reference, and information related to the measured value is reported to the DSP or added in the sending sequence or message. The class II sending unit is defined as a unit which can be triggered by a receiving event or a DSP processor and sends a designated signal sequence or a message at regular time according to the time on a time scale bus;
(5) other general ports may be mounted at any position through the bus, and are not limited herein.
In the above clock time processing apparatus based on the digital signal processor and the hardware acceleration unit, the DSP/CPU may directly access the time scale unit, the part or all of the receiving units, I-class and II-class transmitting units, the operation assisting unit, and other general-purpose ports through one or more groups of general-purpose access buses; the special processing unit can be accessed, and part or all of the receiving units I, II, the transmitting unit, the operation auxiliary unit and other general ports are accessed by the special processing unit; the accessed content includes, but is not limited to, reading message accompanying information, triggering message sending, responding to an interrupt, presetting a sending event at a specific time, and modifying various parameter configurations.
In the clock time processing device based on the digital signal processor and the hardware acceleration unit, the time marking unit can broadcast the time marking information to each module needing the time marking information with fixed delay through one or more time marking buses, and the clock time processing device comprises a receiving unit, a class I and class II sending unit and a DSP/CPU.
In the clock time processing device based on the digital signal processor and the hardware acceleration unit, one or more specific operation auxiliary units are further added, and the functions of the auxiliary units are specific complex operation steps related to general problems in the field, so that the efficiency is improved by hardware.
In the clock time processing device based on the digital signal processor and the hardware acceleration unit, a special processing unit is further added, so that certain transceiving ports and the special processing unit form a high-cohesion processing subsystem, and thus, a high-bandwidth service message can only process reported and measured information and necessary message fields without passing through a general data bus.
The invention has the beneficial effects that:
1) the design is realized by the embedded DSP/CPU of the SOC, and compared with the existing FPGA/ASIC scheme, the design can quickly respond to new market requirements and shorten the TTM of the product.
2) The soft architecture enables the chip to be more redundant and adapt to the change of the demand, and many emerging demands can be realized by software change, so that the life cycle of the chip is prolonged.
3) The performance upgrading product can be rapidly pushed out only by expanding and upgrading the hardware acceleration unit.
Drawings
Fig. 1 is a general block diagram of the present invention.
FIG. 2 is a schematic diagram of a timing mark unit according to the present invention.
FIG. 3 is an exemplary receiving unit according to the present invention.
FIG. 4 is an illustration of a class I sending unit of the present invention.
FIG. 5 is an exemplary class II transmitting unit of the present invention.
FIG. 6 is a diagram of a specific processing unit according to the present invention.
FIG. 7 is a diagram of an arithmetic assisting unit according to the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
A clock time processing method based on a digital signal processor and a hardware acceleration unit comprises the following steps: when an event arrives, the receiving unit refers to the time scale bus, marks a time scale on the event and becomes a time event; the DSP/CPU obtains various time events directly through the receiving unit or indirectly through the special processing unit, obtains estimation parameters through algorithm processing such as abnormity judgment, filtering and the like, and makes various actions according to the estimation parameters, such as directly controlling the I type or II type sending unit to send an event message or indirectly controlling the special processing unit to trigger a specific protocol to stipulate the actions.
A clock time processing method device based on a digital signal processor and a hardware acceleration unit adopts a DSP/CPU and hardware acceleration unit architecture, wherein the hardware acceleration unit comprises:
(1) a set of time stamp buses and at least one set of general data buses;
(2) at least one time stamp unit. A sufficiently large counter is driven, incremented or cyclically incremented during the assertion period, based on an external temporal physical reference. The value of this counter is communicated to other units with a fixed delay through a time stamp bus;
(3) the receiving unit can identify the time mark characteristics of the incoming signals, refers to the time scale on the current time scale bus, accurately reports the time of the incoming signals, and outputs integer or real time by taking the time scale as a unit;
(4) at least one transmitting unit with passive transmission of accurate measurements, which may be a class I transmitting unit or a class II transmitting unit. The class I sending unit is defined as that the class I sending unit is directly triggered by a receiving event or a DSP processor to send a time mark bus without waiting, but a sent signal sequence or message is measured by taking the time scale of the time mark bus as a reference, and information related to the measured value is reported to the DSP or added in the sending sequence or message. The class II sending unit is defined as a unit which can be triggered by a receiving event or a DSP processor and sends a designated signal sequence or a message at regular time according to the time on a time scale bus;
(5) other general ports may be mounted at any position through the bus, and are not limited herein.
The DSP/CPU can directly access the time mark unit through one or more groups of general access buses, and directly access part or all of the receiving units, I-type and II-type sending units, the operation auxiliary unit and other general ports; the special processing unit can be accessed, and part or all of the receiving units I, II, the transmitting unit, the operation auxiliary unit and other general ports are accessed by the special processing unit; the accessed content includes, but is not limited to, reading message accompanying information, triggering message sending, responding to an interrupt, presetting a sending event at a specific time, and modifying various parameter configurations.
The time mark unit can broadcast the time mark information to each module needing the time mark information with fixed delay through one or more groups of time mark buses, and comprises a receiving unit, a class I and class II sending unit and a DSP/CPU.
One or more specific operation auxiliary units are further added, the functions of the auxiliary units are specific complex operation steps related to general problems in the field, and the efficiency is improved by hardware.
And a special processing unit is further added, so that certain transceiving ports and the special processing unit form a high-cohesion processing subsystem, high-bandwidth service messages can only process reported and measured information and a circuit (DIE) with necessary message fields on the same silicon chip without passing through a general data bus, and the same units have consistent operating environment temperature and power supply voltage in a process consistency range, so that after the units with better output isolation characteristics are cascaded, a delay injection unit chain with equal-difference delay can be obtained by controlling layout and wiring length. By selecting at which stage the cell is injected a signal change, a correspondingly delayed signal change can be seen at the final output stage. By selecting the injection point, the output delay can be controlled with a granularity of Δ t, as shown in fig. 5.
On the basis, more closely, N subdivided phases are obtained by performing resistance voltage division output on the last two adjacent taps, and time phase output which is finer than that of a single-stage tap can be obtained by selecting N subdivided phase signals, wherein the step is called as analog interpolation. For example, the timing of the simulated interpolation is shown in FIG. 6
1) For the time stamp unit, as shown in fig. 2, the following example is given:
the example adopts 3 counters with 1 added and 64 bits for technology, 1 is added in each reference clock period, normally 3 counters have the same output, and the output count value is directly driven to the time mark bus through error-proof majority judgment. When the system has soft failure due to abnormality such as cosmic ray bombardment, an error occurs in a certain bit, and the error can be corrected immediately by preventing most of the decisions from being mistaken. The reliability of time counting is improved.
2) For the receiving unit, as shown in fig. 3, the following example is given:
in the example, the arrival time of the edge of the input signal is directly measured, the system obtains parallel data related to fractional delay in a period through a time delay chain, and integer delay is given by subsequent processing and reference to a time mark bus. The receiving unit directly gives the occurrence indication of the time and the corresponding occurrence time.
3) For a class I transmit unit, as shown in fig. 4, the following example is given:
the sending time sent from the general access line directly triggers the time identification head of the output event sequence, the output event sequence is fed back and measured at the same time, and the measuring method can be consistent with the method of the receiving unit. And the measurement result is sent to a stamp module for generating a subsequent time mark sequence, and is reported to the DSP/CPU through a general access bus. This is a non-blocking transmit unit.
4) For a class II transmit unit, as shown in fig. 5, the following example is given:
the class II sending unit needs to accurately control the sending time of the event, the time is not up to wait, therefore, a queue needs to be added for sending, a comparison scheduling unit needs to be arranged at the head of the queue, tic is compared with the reserved sending time of the head of the queue in real time, and when the integer time is up, the subsequent unit is controlled to delay the sending of the residual decimal time.
5) For a proprietary processing unit, as shown in fig. 6, the following example is given:
fig. 6 shows an example of a special processing unit for processing and switching 1588 protocol, where the system interfaces with a general GE/FE interface, GE synchronous ethernet reception (belonging to the receiving unit in the above invention), GE synchronous ethernet transmission (belonging to the class I transmitting unit in the above invention), and PPS _ OUT (belonging to the class II transmitting unit in the above invention). Except for the common GE/FE interface, the interfaces have a common time scale bus; meanwhile, the network interface receives the control of a 1588 protocol processing and switching special processing unit, the 1588 protocol processing and switching special processing unit processes messages of each port at full speed, only necessary time processing information is submitted to DSP/CPU processing, and processing bottleneck cannot be caused to the DSP/CPU.
6) For the arithmetic auxiliary unit, as shown in fig. 7, the following example is given:
given an example of the hardware acceleration of floating point processing with extended bit width, in the time processing, the common double precision bit width can not process the time information without loss, therefore, the hardware acceleration of floating point processing with 256 bits is introduced, and the hardware acceleration processes the mutual conversion between the floating point and the fixed point with 256 bits and the addition, subtraction, multiplication and division of the floating point and the fixed point. So as to reduce the software load and simplify the software processing complexity.
The above description is only a preferred embodiment of the present invention, and the protection scope is not limited to the embodiment, and any technical solution that falls under the idea of the present invention should fall within the protection scope of the present invention. It should also be noted that modifications and embellishments within the scope of the invention may occur to those skilled in the art without departing from the principle of the invention.
Claims (6)
1. A clock time processing method based on a digital signal processor and a hardware acceleration unit is characterized in that:
when an event arrives, the receiving unit refers to the time scale bus, marks a time scale on the event and becomes a time event;
the DSP/CPU obtains various time events directly through the receiving unit or indirectly through the special processing unit, obtains estimation parameters through algorithm processing such as abnormity judgment, filtering and the like, and makes various actions according to the estimation parameters, such as directly controlling the I type or II type sending unit to send an event message or indirectly controlling the special processing unit to trigger a specific protocol to stipulate the actions.
2. The apparatus of claim 1, wherein the DSP/CPU architecture and the hardware acceleration unit architecture are adopted, and the hardware acceleration unit comprises:
(1) a set of time stamp buses and at least one set of general data buses;
(2) at least one time stamp unit. A sufficiently large counter is driven, incremented or cyclically incremented during the assertion period, based on an external temporal physical reference. The value of this counter is communicated to other units with a fixed delay through a time stamp bus;
(3) the receiving unit can identify the time mark characteristics of the incoming signals, refers to the time scale on the current time scale bus, accurately reports the time of the incoming signals, and outputs integer or real time by taking the time scale as a unit;
(4) at least one transmitting unit with passive transmission of accurate measurements, which may be a class I transmitting unit or a class II transmitting unit. The class I sending unit is defined as that the class I sending unit is directly triggered by a receiving event or a DSP processor to send a time mark bus without waiting, but a sent signal sequence or message is measured by taking the time scale of the time mark bus as a reference, and information related to the measured value is reported to the DSP or added in the sending sequence or message. The class II sending unit is defined as a unit which can be triggered by a receiving event or a DSP processor and sends a designated signal sequence or a message at regular time according to the time on a time scale bus;
(5) other general ports may be mounted at any position through the bus, and are not limited herein.
3. The device of claim 2, wherein the DSP/CPU can directly access the timing unit, part or all of the receiving units, I-class and II-class transmitting units, the arithmetic auxiliary unit, and other general-purpose ports through one or more sets of general-purpose access buses; the special processing unit can be accessed, and part or all of the receiving units I, II, the transmitting unit, the operation auxiliary unit and other general ports are accessed by the special processing unit; the accessed content includes, but is not limited to, reading message accompanying information, triggering message sending, responding to an interrupt, presetting a sending event at a specific time, and modifying various parameter configurations.
4. The apparatus of claim 3, wherein the time stamp unit broadcasts the time stamp information to each module requiring the time stamp information with a fixed delay through one or more time stamp buses, and comprises a receiving unit, a class I and class II transmitting unit, and a DSP/CPU.
5. The apparatus of claim 4, further comprising one or more specific auxiliary computing units, wherein the auxiliary computing units are configured to perform specific complex computing steps related to general field problems, and the hardware implementation is used to improve efficiency.
6. The device of claim 5, wherein a special processing unit is further added, so that some transceiving ports and the special processing unit constitute a high-cohesion processing subsystem, so that high-bandwidth service messages can not pass through a general data bus, and the DSP/CPU only processes reported and measured information and necessary message fields.
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