CN111833805A

CN111833805A - Grid scanning driving circuit, driving method and display device

Info

Publication number: CN111833805A
Application number: CN201910308922.1A
Authority: CN
Inventors: 黄飞
Original assignee: Yungu Guan Technology Co Ltd
Current assignee: Chengdu Vistar Optoelectronics Co Ltd
Priority date: 2019-04-17
Filing date: 2019-04-17
Publication date: 2020-10-27
Anticipated expiration: 2039-04-17
Also published as: CN111833805B

Abstract

The application relates to a grid scanning driving circuit, a driving method and a display device. The gate scanning driving circuit comprises an input sub-circuit, a control sub-circuit and an output sub-circuit. The control sub-circuit is connected with the input sub-circuit and used for pulling up the input signal to a first voltage under the control of a clock signal or pulling down the input signal to a second voltage under the control of the clock signal. The control sub-circuit includes a voltage regulation control sub-circuit and an output potential holding sub-circuit. The output potential holding sub-circuit performs pre-pull-up action on the level of the voltage signal pull-up node, so that better bootstrap of the level of the voltage signal pull-down node is kept at a lower level, and finally the output signal of the grid scanning driving circuit is kept more stable and effective.

Description

Grid scanning driving circuit, driving method and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a gate scan driving circuit, a driving method, and a display device.

Background

Organic Light Emitting Display (OLED) is regarded as the next generation of the most promising new flat panel Display technology. The colorization mode is that pixel units are formed by sub-pixels made of red, blue and green materials to further form a pixel arrangement structure. The display effect of the pixel unit or the pixel arrangement structure requires the control of the gate scanning driving circuit. Therefore, the performance of the gate scan driving circuit directly affects the display effect of the organic light emitting display panel.

The gate scan driving circuit includes a plurality of transistors. The traditional grid scanning driving circuit can generate large threshold voltage drift and large leakage current, so that the grid scanning circuit has the problem of unstable output signals or ineffective voltage drop during cascade connection.

Disclosure of Invention

Therefore, it is necessary to provide a gate scanning driving circuit, a driving method and a display device, which aim at the problem that the conventional gate scanning driving circuit generates a large threshold voltage drift and a large leakage current, so that the output signal of the gate scanning circuit is unstable or the voltage drops are invalid when the gate scanning circuits are cascaded.

A gate scan driving circuit includes:

an input sub-circuit for providing an input signal;

the control sub-circuit is connected with the input sub-circuit and used for pulling up the input signal to a first voltage under the control of a clock signal or pulling down the input signal to a second voltage under the control of the clock signal; and

the output sub-circuit is connected with the control sub-circuit and is used for converting the signals processed by the control sub-circuit into output signals to be output;

wherein the control sub-circuit comprises a voltage regulation control sub-circuit and an output potential holding sub-circuit;

one end of the voltage regulation control sub-circuit is connected with the input sub-circuit and used for pulling up an input signal to a first regulation voltage or pulling down the input signal to a second regulation voltage under the control of a clock signal;

the output potential holding sub-circuit is connected with the other end of the voltage regulation control sub-circuit and is used for pulling the first regulation voltage up to the first voltage or pulling the second regulation voltage down to the second voltage.

In one embodiment, the output potential holding sub-circuit includes: a first clock signal input terminal, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a first level signal input terminal;

the first clock signal input end is respectively connected with the source electrode of the sixth transistor and the drain electrode of the eighth transistor; the grid electrode of the sixth transistor is connected with the drain electrode of the eighth transistor; a drain of the sixth transistor is connected to a gate of the eighth transistor and a source of the seventh transistor, respectively;

a gate of the seventh transistor is connected to a gate of the ninth transistor; a drain of the seventh transistor is connected to the first level signal input terminal; the drain electrode of the ninth transistor is connected with the source electrode of the eighth transistor; a source of the ninth transistor is connected to the first level signal input terminal;

the grid electrode of the ninth transistor is connected with the first node of the voltage regulation control sub-circuit; the drain of the ninth transistor is connected to the second node of the voltage regulation control sub-circuit.

In one embodiment, the voltage regulation control sub-circuit comprises: a pull-down control signal sub-circuit and a pull-up control signal sub-circuit;

a first end of the pull-down control signal sub-circuit is connected with the input sub-circuit and the first node respectively; a second end of the pull-down control signal sub-circuit is connected with the first clock signal input end; and the third end of the pull-down control signal sub-circuit is connected with the second node.

In one embodiment, the output sub-circuit comprises: a pull-up output sub-circuit and a pull-down output sub-circuit;

the first end of the pull-up output sub-circuit is connected with the first level signal input end; a second end of the pull-up output sub-circuit is connected with the first node; the third end of the pull-up output sub-circuit and a second level signal input end; the fourth end of the pull-up output sub-circuit is connected with an output signal end;

the first end of the pull-down output sub-circuit is connected with the output signal end; a second end of the pull-down output sub-circuit is connected with the second node; the third end of the pull-down output sub-circuit is connected with the second level signal input end; the fourth end of the pull-down output sub-circuit is connected with a second level signal input end; and the fifth end of the pull-down output sub-circuit and the second clock signal input end.

In one embodiment, the pull-up output sub-circuit comprises: the first level signal input end, a voltage signal pull-up node, the second level signal input end, a tenth transistor, a first capacitor and a second capacitor;

one end of the first capacitor is connected with the first level signal input end; the other end of the first capacitor is connected with the voltage signal pull-up node;

one end of the second capacitor is connected with the voltage signal pull-up node; the other end of the second capacitor is connected with the second level signal input end;

a gate of the tenth transistor is connected to the voltage signal pull-up node; a source of the tenth transistor is connected to the output signal terminal; a drain of the tenth transistor is connected to the first level signal input terminal.

In one embodiment, the pull-down output sub-circuit comprises: the second level signal input end, the voltage signal pull-down node, the second clock signal input end, the eleventh transistor, the twelfth transistor and the third capacitor;

a drain of the twelfth transistor is connected to the second node; the grid electrode of the twelfth transistor is connected with the second level signal input end; a source of the twelfth transistor is connected with the voltage signal pull-down node;

one end of the third capacitor is connected with the voltage signal pull-down node; the other end of the third capacitor is connected with the second level signal input end;

the grid electrode of the eleventh transistor is connected with the voltage signal low-pulling node; a drain of the eleventh transistor is connected to the output signal terminal; a source of the eleventh transistor is connected to the second clock signal input terminal.

In one embodiment, any of the transistors mentioned above are all P-type transistors.

In one embodiment, the signals input by the first clock signal input terminal and the second clock signal input terminal are complementary clock pulse signals.

A pixel driving method comprises a plurality of grid scanning driving circuits, wherein each grid scanning driving circuit is connected with a pixel unit and is used for controlling the pixel unit to display according to a first voltage or a second voltage;

the pixel driving method includes:

at a first moment, controlling an input signal of the grid scanning driving circuit to be a second voltage, controlling a first clock signal to be a second voltage, controlling an output signal of the grid scanning driving circuit to be a first voltage, pulling up a voltage signal pull-up node to a first adjusting voltage, and pulling down a voltage signal pull-down node to a second adjusting voltage;

at a second moment, controlling an input signal of the grid scanning driving circuit to be a first voltage, controlling a first clock signal to be a first voltage, controlling an output signal of the grid scanning driving circuit to be a second voltage, pulling up a voltage signal high node to the first voltage, and pulling down a voltage signal low node to the second voltage;

and at the third moment, controlling the input signal of the grid scanning driving circuit to be the first voltage, the first clock signal to be the second voltage, the second clock signal to be the first voltage, controlling the output signal of the grid scanning driving circuit to be the first voltage, controlling the voltage signal pull-up node to be the second voltage, and controlling the voltage signal pull-down node to be the first voltage.

A display device comprises the gate scanning driving circuit.

The application provides a grid scanning driving circuit, a driving method and a display device. The gate scanning driving circuit comprises an input sub-circuit, a control sub-circuit and an output sub-circuit. The control sub-circuit is connected with the input sub-circuit and used for pulling up the input signal to a first voltage under the control of a clock signal or pulling down the input signal to a second voltage under the control of the clock signal. The control sub-circuit includes a voltage regulation control sub-circuit and an output potential holding sub-circuit. The output potential holding sub-circuit performs pre-pull-up action on the level of the voltage signal pull-up node, so that better bootstrap of the level of the voltage signal pull-down node is kept at a lower level, and finally the output signal of the grid scanning driving circuit is kept more stable and effective.

Drawings

Fig. 1 is a block diagram of a gate scan driving circuit provided in an embodiment of the present application;

FIG. 2 is a circuit diagram of a gate scan driving circuit provided in an embodiment of the present application;

FIG. 3 is a circuit diagram of a gate scan driving circuit provided in an embodiment of the present application;

FIG. 4 is a timing diagram of a gate scan driving circuit provided in an embodiment of the present application;

FIG. 5 is a comparison of a timing diagram of a node PD pulled down by a voltage signal in a gate scan driving circuit according to an embodiment of the present application and a conventional scheme;

fig. 6 is a comparison diagram of a timing diagram of a node-pull-up voltage signal pulling up a node PU in a gate scan driving circuit according to an embodiment of the present application and a conventional scheme.

The reference numbers illustrate:

gate scanning driving circuit 10

Input sub-circuit 100

Control sub-circuit 200

Voltage regulation control subcircuit 210

First node 213

Second node 214

Output potential holding sub-circuit 220

Output sub-circuit 300

Pull-up output subcircuit 310

Pull-down output sub-circuit 320

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more clearly understood, the gate scan driving circuit, the driving method and the display device of the present application are further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

As described in the background art, the stable and effective operation of the gate scan driving circuit of the organic light emitting display panel is always a key point of the improvement of the performance of the gate scan driving circuit. The traditional grid scanning driving circuit can generate large threshold voltage drift and large leakage current, so that the grid scanning circuit has the problem of unstable output signals or ineffective voltage drop during cascade connection.

The application provides a grid scanning driving circuit, a driving method and a display device. The gate scanning driving circuit can provide a solution to the problem that the output signal is unstable or the voltage drop is ineffective. The inventor finds that the stability of the output voltage of the gate scanning driving circuit can be effectively improved by adding a new potential holding circuit when the gate scanning driving circuit is designed. The design scheme in the application is a new circuit structure which is proposed by the inventor through a plurality of experiments. The electrode scanning circuit in this application guarantees that the level of voltage signal pull-down node keeps at lower level fast through the level of continuously pulling high voltage signal pull-up node PU point. The electrode scanning circuit can ensure that the output voltage is more stable and effective, so that the performance of the organic light-emitting display panel is better improved, the yield of the display panel is improved, and the market competitiveness of the display panel is improved.

Referring to fig. 1, the present application provides a gate scan driving circuit 10, which includes an input sub-circuit 100, a control sub-circuit 200, and an output sub-circuit 300.

The input sub-circuit 100 is used to provide an input signal, which may be a high voltage or a low voltage. In this step, the voltage range of the input signal may be 6V to-6V. For example, the voltage of the input signal may be 5V, and the voltage of the input signal may be-5V. The output of the input sub-circuit 100 is connected to the input of the control sub-circuit 200.

In one embodiment, referring to fig. 2, the input sub-circuit 100 includes an input signal terminal STV, a second level input terminal VL, and a first clock signal input terminal CK. The input sub-circuit 100 further comprises a first transistor P1 and a second transistor P2. The gate of the first transistor P1 is connected with the gate of the second transistor P2. The source of the first transistor P1 is the output terminal of the input sub-circuit 100. The source of the first transistor P1 is connected to an input of the control sub-circuit 200. The drain of the first transistor P1 is connected to the second level input terminal VL. The source of the second transistor P2 is connected to the input signal terminal STV. The drain of the second transistor P2 is the output terminal of the input sub-circuit 100. The drain of the second transistor P2 is connected to an input of the control sub-circuit 200. The input sub-circuit 100 provided in this step can enable the input signal (input voltage) of the input signal terminal STV to be stably transmitted in the gate scan driving circuit 10, so as to avoid damage to the pixel unit caused by unstable voltage signal.

The control sub-circuit 200 is connected to the input sub-circuit 100. The control sub-circuit 200 is used to pull up the input signal to a first voltage under the control of the clock signal, or pull down the input signal to a second voltage under the control of the clock signal.

In this step, the first voltage may be a high voltage, and a specific voltage may be in a range of 0V to 10V. Of course, the range of the first voltage may be another range according to the type of the device selected in the control sub-circuit 200. The control and adjustment of the control sub-circuit 200 can make the gate scan driving circuit 10 control the display state of the pixel unit.

The output sub-circuit 300 is connected to the control sub-circuit 200. The output sub-circuit 300 is used to convert the signal processed by the control sub-circuit 200 into an output signal for outputting.

In this step, the output sub-circuit 300 may include at least one transistor and at least one capacitor. The output sub-circuit 300 may transmit signals that are controlled and regulated by the control sub-circuit 200.

As a preferred embodiment, on the basis of the above embodiment, the control sub-circuit 200 includes a voltage regulation control sub-circuit 210 and an output potential holding sub-circuit 220.

One end of the voltage regulation control sub-circuit 210 is connected to the input sub-circuit 100, and is configured to pull up the input signal to a first regulation voltage or pull down the input signal to a second regulation voltage under the control of the clock signal.

The output potential holding sub-circuit 220 is connected to the other end of the voltage regulation control sub-circuit 210, and is configured to pull up the first adjustment voltage to the first voltage, or pull down the second adjustment voltage to the second voltage. The output potential holding sub-circuit 220 is used to implement secondary stabilization of the voltage adjusted by the voltage adjustment control sub-circuit 210. In this step, the output potential holding sub-circuit 220 achieves the effect of ensuring more stable and effective output voltage by means or scheme of reversely acting the output signal on the inside of the control sub-circuit 200.

In this embodiment, the output potential holding sub-circuit 220 is introduced. In one embodiment, the output potential holding sub-circuit 220 may include a sixth transistor P6, a seventh transistor P7, an eighth transistor P8, and a ninth transistor P9. The output potential holding sub-circuit 220 pre-pulls the level of the voltage signal pull-up node PU high, so as to ensure that the level of the voltage signal pull-down node PD is better bootstrapped and kept at a lower level, and finally, the output signal of the gate scan driving circuit 10 is kept more stable and effective.

Referring to fig. 2, as a preferred embodiment, on the basis of the above embodiment, the output voltage holding sub-circuit 220 includes: a first clock signal input terminal CK, a sixth transistor P6, a seventh transistor P7, an eighth transistor P8, a ninth transistor P9, and a first level signal input terminal VH.

The first clock signal input terminal CK is connected to the source of the sixth transistor P6 and the drain of the eighth transistor P8, respectively. The gate of the sixth transistor P6 is connected with the drain of the eighth transistor P8. A drain of the sixth transistor P6 is connected to a gate of the eighth transistor P8 and a source of the seventh transistor P7, respectively.

A gate of the seventh transistor P7 is connected with a gate of the ninth transistor P9. A drain of the seventh transistor P7 is connected to the first level signal input terminal VH. A drain of the ninth transistor P9 is connected with a source of the eighth transistor P8. A source of the ninth transistor P9 is connected to the first level signal input terminal VH.

The gate of the ninth transistor P9 is connected to the first node 213 of the voltage regulation control sub-circuit 210. The drain of the ninth transistor P9 is connected to the second node 214 of the voltage regulation control sub-circuit 210.

In the present embodiment, the output potential holding sub-circuit 220 includes the sixth transistor P6, the seventh transistor P7, the eighth transistor P8, and the ninth transistor P9. The output potential holding sub-circuit 220 pre-pulls the level of the voltage signal pull-up node PU high, so as to ensure that the level of the voltage signal pull-down node PD is better bootstrapped and kept at a lower level, and finally, the output signal of the gate scan driving circuit 10 is kept more stable and effective. In this embodiment, the transistors with different specifications are selected according to different requirements of different pixel units for the output potential holding sub-circuit 220. That is, the specifications and operating parameters of the sixth transistor P6, the seventh transistor P7, the eighth transistor P8, and the ninth transistor P9 are not unique.

Referring to fig. 3, as a preferred embodiment, on the basis of the foregoing embodiment, the voltage regulation control sub-circuit 210 includes: a pull-down control signal sub-circuit 211 and a pull-up control signal sub-circuit 212.

A first terminal of the pull-down control signal sub-circuit 211 is connected to the input sub-circuit 100 and the first node 213, respectively. A second terminal of the pull-down control signal sub-circuit 211 is connected to the first clock signal input terminal CK. The third terminal of the pull-down control signal sub-circuit 211 is connected to the second node 214.

In this embodiment, the voltage regulation control sub-circuit 210 is divided into the pull-down control signal sub-circuit 211 and the pull-up control signal sub-circuit 212. The classified voltage regulation control sub-circuit 210 distinguishes the pull-up control sub-circuit from the pull-down control sub-circuit, and fully shows the individual processing processes of the sub-circuits. In this embodiment, it is convenient to separately adjust the parameters of the pull-down control signal sub-circuit 211 and the pull-up control signal sub-circuit 212.

As a preferred implementation, on the basis of the above implementation, the output sub-circuit 300 includes: a pull-up output sub-circuit 310 and a pull-down output sub-circuit 320.

A first terminal of the pull-up output sub-circuit 310 is connected to the first level signal input terminal VH. A second terminal of the pull-up output sub-circuit 310 is connected to the first node 213. The third terminal of the pull-up output sub-circuit 310 is connected to the second level signal input terminal VL. The fourth terminal of the pull-up output sub-circuit 310 is connected to an output signal terminal.

The first terminal of the pull-down output sub-circuit 320 is connected to the output signal terminal. A second terminal of the pull-down output sub-circuit 320 is connected to the second node 214. The third terminal of the pull-down output sub-circuit 320 is connected to the second level signal input terminal VL. The fourth terminal of the pull-down output sub-circuit 320 is connected to the second level signal input terminal VL. The fifth terminal of the pull-down output sub-circuit 320 and the second clock signal input terminal CKB.

In this embodiment, the output sub-circuit 300 is divided into the pull-up output sub-circuit 310 and the pull-down output sub-circuit 320. For different circuit requirements, the output end of the pull-up output sub-circuit 310 or the pull-down output sub-circuit 320 may be connected to a certain voltage control circuit or a display circuit.

As a preferred implementation, on the basis of the above implementation, the pull-up output sub-circuit 310 includes: the first level signal input end VH, the voltage signal pull-up node PU, the second level signal input end VL, the tenth transistor P10, the first capacitor and the second capacitor.

One end of the first capacitor is connected with the first level signal input end VH. The other end of the first capacitor is connected with the voltage signal pull-up node.

One end of the second capacitor is connected with the voltage signal pull-up node. The other end of the second capacitor is connected with the second level signal input end VL.

The gate of the tenth transistor P10 is connected to the voltage signal pull-up node. A source of the tenth transistor P10 is connected to the output signal terminal. A drain of the tenth transistor P10 is connected to the first level signal input terminal VH.

In this embodiment, a circuit connection manner of the pull-up output sub-circuit 310 is specifically provided. It is of course understood that the specific connection of the pull-up output sub-circuit 310 is not limited to the one mentioned in this application. The pull-up output sub-circuit 310 and the pull-down output sub-circuit 320 may be independently controlled for output.

As a preferred embodiment, on the basis of the above embodiments, the pull-down output sub-circuit 320 includes: the second level signal input end VL, the voltage signal pull-down node PD, the second clock signal input end CKB, the eleventh transistor P11, the twelfth transistor P12 and the third capacitor.

A drain of the twelfth transistor P12 is connected to the second node 214. A gate of the twelfth transistor P12 is connected to the second level signal input terminal VL. The source of the twelfth transistor P12 is connected to the voltage signal pull-down node.

One end of the third capacitor is connected with the voltage signal pull-down node. The other end of the third capacitor is connected with the second level signal input end VL.

The gate of the eleventh transistor P11 is connected to the voltage signal pull-down node. A drain of the eleventh transistor P11 is connected to the output signal terminal. A source of the eleventh transistor P11 is connected to the second clock signal input terminal CKB.

In this embodiment, a circuit connection manner of the pull-down output sub-circuit 320 is specifically provided. It will be understood, of course, that the specific connection of the pull-down output sub-circuit 320 is not limited to the one mentioned in this application. The pull-up output sub-circuit 310 and the pull-down output sub-circuit 320 may be independently controlled for output.

As a preferred embodiment, in addition to the above embodiments, any of the transistors mentioned above is a P-type transistor.

The P-type transistor can be a P-type field effect transistor and a P-type metal oxide semiconductor transistor. Specifically, a Field Effect Transistor (FET)) is abbreviated as a Field Effect Transistor. There are two main types of field effect transistors: junction Field Effect Transistors (JFETs) and metal-oxide-semiconductor field effect transistors (MOS-FETs). A field effect transistor is a transistor that is also referred to as a unipolar transistor, in which the majority carriers participate in conduction. It belongs to a voltage control type semiconductor device. Has high input resistance (10)⁷Ω～10¹⁵Omega), small noise, low power consumption, large dynamic range, easy integration, no secondary breakdown phenomenon, wide safe working area and the like.

A Metal-Oxide-Semiconductor Field-effect transistor (MOSFET) is a Field-effect transistor that can be widely used in analog circuits and digital circuits. The mosfet may be classified into an N-channel type in which electrons are dominant and a P-channel type in which holes are dominant according to their channel polarities, and is generally called an N-type mosfet (NMOSFET) and a P-type mosfet (PMOSFET).

The oxide layer in the MOSFET is located above the channel and has a thickness of tens to hundreds of angstroms according to the operating voltage

Are not equal. The material of a typical mosfet is silicon dioxide (SiO)₂). Some new advanced processes have been available using, for example, silicon oxynitride (SiON) as the oxide layer.

In another embodiment, the transistor can also be an N-type transistor. Since the on-voltage and the off-voltage of the P-type transistor and the N-type transistor are different, when the transistors in the gate scan driving circuit 10 are N-type transistors, the applied voltage signal in fig. 4 and the obtained output voltage signal will change accordingly.

As a preferred embodiment, on the basis of the above embodiment, the signals inputted from the first clock signal input terminal CK and the second clock signal input terminal CKB are complementary clock pulse signals.

In this embodiment, the application of complementary clock signals can ensure a better balance of the voltage signals in the gate scan driving circuit 10.

The operation principle of the gate scan driving circuit 10 is described in detail below with reference to fig. 3 and 4:

fig. 3 shows a specific circuit diagram of the gate scan driving circuit 10 when P-type transistors are provided. Fig. 4 shows a timing chart of voltage signals of the gate scan driving circuit 10 shown in fig. 3. In fig. 4, VH is high and VL is low. The voltage signal pull-up node PU is a node that is pulled up when the output signal is active. The voltage signal pull-down node PD is a node that is pulled down when the output signal is active. When the output signal OUT is at a low level, it is an output required by the gate scan driving circuit 10. When the output signal OUT is at a high level, it is an unnecessary output of the gate scanning drive circuit 10. In fig. 4, the end time of the first time period is the first time, the end time of the second time period is the second time, and the end time of the third time period is the third time.

At the first time, the input signal STV is at a low level, the first clock signal CK is at a low level, the second clock signal CKB is at a high level, and the first transistor P1 and the second transistor P2 are turned on. Then the third transistor P3, the fourth transistor P4 is turned on, and the twelfth transistor P12 is normally open. Meanwhile, the sixth transistor P6, the seventh transistor P7, the eighth transistor P8, and the ninth transistor P9 are turned on. The tenth transistor P10 is turned on slightly, the eleventh transistor P11 is turned on, and the other transistor (the fifth transistor P5) is turned off. The output signal OUT is at a high level, the voltage signal pull-up node PU is pulled up to about 0V, and the voltage signal pull-down node PD is pulled down to about-6V.

At the second time, the input signal STV is at a high level, the first clock signal CK is at a high level, and the second clock signal CKB is at a low level. The eleventh transistor P11 is still turned on, and at this time Vss of the eleventh transistor P11 is less than 0, and since the output signal OUT is rising, the potential of the voltage signal pull-down node PD node becomes lower. The fifth transistor P5 is turned on, the twelfth transistor P12 is still turned on, and the other tubes (P1, P2, P3, P4, P6, P7, P8, P9, P10) are turned off. The output signal OUT is at a low level, the node PU pulled high by the voltage signal is at a high level (about 6V), and the node PD pulled low by the voltage signal is bootstrapped to a lower level (about-13V).

At the third time, the input signal STV is at a high level, the first clock signal CK is at a low level, and the second clock signal CKB is at a high level. The first transistor P1, the second transistor P2 is turned on, the fourth transistor P4 is turned on, and the twelfth transistor P12 is still turned on. The eighth transistor P8 is turned on, the sixth transistor P6 is turned on, the tenth transistor P10 is turned on, and the eleventh transistor P11 is turned off. The output signal OUT is high and is high thereafter, the node PU pulled high by the voltage signal is low, and the node PD pulled low by the voltage signal is high.

In the embodiment of the present application, the output potential holding sub-circuit 220 (including the transistor P6, the transistor P7, the transistor P8, and the transistor P9, as shown in fig. 3) is introduced into the gate scan driving circuit 10. The output potential holding sub-circuit 220 performs a pre-pull-up action on the level of PU, so that the level of the second bootstrap pull-down at the PD point is lower, the eleventh transistor P11 is quickly opened to enter a deep linear region, the output signal OUT of the gate scan driving circuit 10 is quickly changed to a low level and is well maintained for a certain time, and the driving capability of the output signal OUT is enhanced.

Referring to FIG. 5, a graph comparing a voltage signal pull-down node PD signal according to an embodiment of the present application with a voltage signal pull-down node PD signal according to a conventional scheme is provided. Referring to FIG. 6, a comparison of the voltage signal pull-up node PU signal of an embodiment of the present application and the voltage signal pull-up node PU signal of the conventional scheme is provided.

In this embodiment, the output waveform of the voltage signal pull-up node PU signal is similar to the waveform of the first clock signal CK, and is pulled up to the high level at intervals. At the end of the first time period during normal operation, the voltage signal pull-up node PU signal is already pre-pulled up to a certain voltage. The voltage signal pull-up node PU signal has been fully pulled high at the end of the second time period. The signal that the voltage signal pulls down the node PD node twice bootstrap low due to this pre-pull-up action, so that the eleventh transistor P11 opens quickly into the deep linear region. The eleventh transistor P11 is turned on quickly into the deep linear region, so that the gate scan driving circuit 10 can make the output signal OUT go low quickly and keep it for a certain time (the output signal OUT is the output level required by the gate scan driving circuit 10 when it is low).

The present application further provides a pixel driving method, which includes a plurality of gate scan driving circuits 10 as described in any one of the above. Each of the gate scan driving circuits 10 is connected to a pixel unit, and is configured to control the pixel unit to perform display according to a first voltage or a second voltage. A plurality of the gate scan circuits 10 cascade-form a driving control of the entire organic light emitting display panel.

At the first moment, the input signal is the second voltage, the first clock signal is the second voltage, the second clock signal is the first voltage, the gate scan driving circuit 10 controls the output signal to be the first voltage, the pull-up node of the voltage signal is pulled up to the first adjustment voltage, and the pull-down node of the voltage signal is pulled down to the second adjustment voltage.

Specifically, at the first time, the input signal STV is at a low level, the first clock signal CK is at a low level, and the second clock signal CKB is at a high level. The output signal OUT is at a high level, the voltage signal pull-up node PU is pulled up to about 0V, and the voltage signal pull-down node PD is pulled down to about-6V.

At the second moment, the input signal is the first voltage, the first clock signal is the first voltage, the second clock signal is the second voltage, the gate scan driving circuit 10 controls the output signal to be the second voltage, the voltage signal pull-up node is pulled up to the first voltage, and the voltage signal pull-down node is pulled down to the second voltage.

Specifically, at the second time, the input signal STV is at a high level (6V), the first clock signal CK is at a high level (6V), and the second clock signal CKB is at a low level (-6V). The output signal OUT is low (-6V). The voltage signal pull-up node PU goes to a higher level (around 6V) and the voltage signal pull-down node PD node bootstraps to a lower level (-around 13V).

At the third moment, the input signal is the first voltage, the first clock signal is the second voltage, the second clock signal is the first voltage, the gate scan driving circuit 10 controls the output signal to be the first voltage, the pull-up node of the voltage signal is the second voltage, and the pull-down node of the voltage signal is the first voltage.

Specifically, at the third time, the input signal STV is at a high level, the first clock signal CK is at a low level, and the second clock signal CKB is at a high level. The output signal OUT is high and thereafter always high. The node PU is pulled high by the voltage signal to be at a low level (-6V), and the node PD is pulled low by the voltage signal to be at a high level (8V).

In the embodiment of the present application, in the gate scan driving method, the output potential holding sub-circuit 220 in the gate scan driving circuit 10 performs a pre-pull-up operation on the level of the voltage signal pull-up node PU. After the voltage signal pulls up the level of the node PU for pre-pulling up, the level of the secondary bootstrap pull-down of the voltage signal pull-down node PD is lower. The transistor in the gate scanning circuit 10 is quickly turned on to enter a deep linear region, so that the output signal OUT of the gate scanning driving circuit 10 is quickly changed to a low level and is kept for a certain time, and the driving capability of the output signal OUT is enhanced.

The present application further provides a display device, comprising the gate scan driving circuit 10 as described in any one of the above embodiments. The display device includes the gate driving circuit 10, a pixel unit or a pixel structure, and other display devices (e.g., a touch device).

In this embodiment, the display device may be a smart phone, a tablet computer, a car audio, or another display device applying the display panel. The display device may also be, for example, a smart billboard or other place where the display panel is applied. The display panel can be a hard-screen OLED or a flexible OLED, and different materials can be specifically selected for distinguishing according to the substrate.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A gate scan drive circuit (10), comprising:

an input sub-circuit (100) for providing an input signal;

a control sub-circuit (200) connected to the input sub-circuit (100) for pulling the input signal up to a first voltage under control of a clock signal or pulling the input signal down to a second voltage under control of the clock signal; and

the output sub-circuit (300) is connected with the control sub-circuit (200) and is used for converting the signals processed by the control sub-circuit (200) into output signals to be output;

wherein the control sub-circuit (200) comprises a voltage adjustment control sub-circuit (210) and an output potential holding sub-circuit (220);

one end of the voltage regulation control sub-circuit (210) is connected with the input sub-circuit (100) and used for pulling up an input signal to a first regulation voltage or pulling down the input signal to a second regulation voltage under the control of a clock signal;

the output potential holding sub-circuit (220) is connected with the other end of the voltage regulation control sub-circuit (210) and is used for pulling the first regulation voltage up to the first voltage or pulling the second regulation voltage down to the second voltage.

2. The gate scan drive circuit (10) of claim 1, wherein the output potential holding sub-circuit (220) comprises: a first clock signal input terminal, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a first level signal input terminal;

the gate of the ninth transistor is connected with the first node (213) of the voltage regulation control sub-circuit (210); the drain of the ninth transistor is connected to the second node (214) of the voltage regulation control sub-circuit (210).

3. A gate scan drive circuit (10) as claimed in claim 2, wherein the voltage regulation control sub-circuit (210) comprises: a pull-down control signal sub-circuit (211) and a pull-up control signal sub-circuit (212);

a first end of the pull-down control signal sub-circuit (211) is connected to the input sub-circuit (100) and the first node (213), respectively; a second terminal of the pull-down control signal sub-circuit (211) is connected to the first clock signal input terminal; the third terminal of the pull-down control signal sub-circuit (211) is connected to the second node (214).

4. A gate scan driver circuit (10) as claimed in claim 3, wherein the output sub-circuit (300) comprises: a pull-up output sub-circuit (310) and a pull-down output sub-circuit (320);

a first terminal of the pull-up output sub-circuit (310) is connected to the first level signal input terminal; a second terminal of the pull-up output sub-circuit (310) is connected to the first node (213); a third terminal and a second level signal input terminal of the pull-up output sub-circuit (310); the fourth end of the pull-up output sub-circuit (310) is connected with an output signal end;

a first terminal of the pull-down output sub-circuit (320) is connected with the output signal terminal; a second terminal of the pull-down output sub-circuit (320) is connected to the second node (214); the third end of the pull-down output sub-circuit (320) is connected with the second level signal input end; the fourth end of the pull-down output sub-circuit (320) is connected with a second level signal input end; a fifth terminal of the pull-down output sub-circuit (320) and a second clock signal input terminal.

5. The gate scan driver circuit (10) of claim 4, wherein the pull-up output subcircuit (310) includes: the first level signal input end, a voltage signal pull-up node, the second level signal input end, a tenth transistor, a first capacitor and a second capacitor;

6. The gate scan driver circuit (10) of claim 5, wherein the pull-down output sub-circuit (320) comprises: the second level signal input end, the voltage signal pull-down node, the second clock signal input end, the eleventh transistor, the twelfth transistor and the third capacitor;

a drain of the twelfth transistor is connected to the second node (214); the grid electrode of the twelfth transistor is connected with the second level signal input end; a source of the twelfth transistor is connected with the voltage signal pull-down node;

7. A gate scan drive circuit (10) as claimed in any one of claims 2 to 6, wherein the transistors are all P-type transistors.

8. A gate scan driver circuit (10) as claimed in any one of claims 1 to 6, wherein the signals input at the first and second clock signal inputs are complementary clock pulse signals.

9. A pixel driving method, comprising a plurality of gate scan driving circuits (10) according to any one of claims 1 to 8, wherein each gate scan driving circuit (10) is connected to a pixel unit for controlling the pixel unit to display according to a first voltage or a second voltage;

the pixel driving method includes:

at a first moment, controlling an input signal of the grid scanning driving circuit (10) to be a second voltage, controlling a first clock signal to be a second voltage, controlling an output signal of the grid scanning driving circuit (10) to be a first voltage, pulling up a voltage signal pull-up node to a first adjusting voltage, and pulling down a voltage signal pull-down node to a second adjusting voltage;

at a second moment, controlling an input signal of the grid scanning driving circuit (10) to be a first voltage, a first clock signal to be the first voltage, and a second clock signal to be a second voltage, controlling an output signal of the grid scanning driving circuit (10) to be the second voltage, pulling up a voltage signal pull-up node to the first voltage, and pulling down a voltage signal pull-down node to the second voltage;

and at the third moment, controlling the input signal of the grid scanning driving circuit (10) to be the first voltage, the first clock signal to be the second voltage, the second clock signal to be the first voltage, controlling the output signal of the grid scanning driving circuit (10) to be the first voltage, controlling the pull-up node of the voltage signal to be the second voltage, and controlling the pull-down node of the voltage signal to be the first voltage.

10. A display device comprising a gate scan driver circuit (10) as claimed in any one of claims 1 to 8.