CN111722691A - Power supply correction circuit and server - Google Patents
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- CN111722691A CN111722691A CN202010569342.0A CN202010569342A CN111722691A CN 111722691 A CN111722691 A CN 111722691A CN 202010569342 A CN202010569342 A CN 202010569342A CN 111722691 A CN111722691 A CN 111722691A
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Abstract
The invention provides a power supply correction circuit and a server, wherein the circuit comprises: the first signal group comprises a first selection device and a second selection device, and a GND pin and a VCC pin of the first selection device are reversely connected with a GND pin and a VCC pin of the second selection device; the second signal group comprises a third selection device and a fourth selection device, a GND pin and a VCC pin of the third selection device are reversely connected with a GND pin and a VCC pin of the fourth selection device, the GND pin of the third selection device is connected to the GND pin of the first selection device, and the VCC pin of the third selection device is connected with the VCC pin of the first selection device; the first signal group is configured such that when the input terminal inputs the VCC signal or the GND signal, the output terminal of the first signal group provides the first signal to the downstream circuit, and the second signal group is configured such that when the input terminal inputs the VCC signal or the GND signal, the output terminal of the second signal group provides the second signal to the downstream circuit. Through the scheme, the circuit board damage caused by reverse connection of the power supply can be avoided.
Description
Technical Field
The field relates to the field of computers, and more particularly to a power supply correction circuit and a server.
Background
A server is a computer system that can provide some services to other machines in a network, and has high-speed computing capability, long-time reliable operation, strong external data throughput capability, and the like. Besides the CPU main board, a complete server product also comprises a Riser board and a BP board, etc. to form a complete server with complete functions. In the existing server product, the main board, the Riser board, the BP board and other circuit boards are all connected through CABLE CABLEs. The data signals and power supply required by the Riser board and the BP board are all supplied to the Riser board and the BP board from the main board through the CABLE CABLE, so that the whole server can work normally.
When the existing server product is connected with a CABLE, if the power signal CABLE is connected incorrectly, the circuit board can be damaged.
Disclosure of Invention
In view of this, an object of the embodiments of the present invention is to provide a power correction circuit and a server, which can enable a downlink circuit board to normally operate under the condition that power supplies are reversely connected by using the method of the present invention, so as to avoid circuit board damage caused by reverse connection of power supplies and reduce the cost of developing products.
In view of the above object, an aspect of an embodiment of the present invention provides a power supply correction circuit including:
the first signal group comprises a first selection device and a second selection device, and a GND pin and a VCC pin of the first selection device are reversely connected with a GND pin and a VCC pin of the second selection device;
the second signal group comprises a third selection device and a fourth selection device, a GND pin and a VCC pin of the third selection device are reversely connected with a GND pin and a VCC pin of the fourth selection device, the GND pin of the third selection device is connected to the GND pin of the first selection device, and the VCC pin of the third selection device is connected with the VCC pin of the first selection device;
the first signal group is configured such that when the input terminal inputs the VCC signal or the GND signal, the output terminal of the first signal group provides the first signal to the downstream circuit, and the second signal group is configured such that when the input terminal inputs the VCC signal or the GND signal, the output terminal of the second signal group provides the second signal to the downstream circuit.
In accordance with one embodiment of the present invention,
the first signal group includes:
a first input pin of the first selection device is connected with a VCC pin, and a second input pin of the first selection device is connected with a GND pin and an input selection pin;
a first input pin of the second selection device is connected with a VCC pin, a second input pin of the second selection device is connected with a GND pin and an input selection pin, an output pin of the second selection device is connected with an output pin of the first selection device, the VCC pin of the second selection device is connected with the GND pin of the first selection device, and the GND pin of the second selection device is connected with the VCC pin of the first selection device;
the second signal group includes:
a first input pin of the third selection device is connected with the VCC pin and the input selection pin, and a second input pin of the third selection device is connected with the GND pin;
a first input pin of the fourth selection device is connected with the VCC pin and the input selection pin, a second input pin of the fourth selection device is connected with the GND pin, an output pin of the fourth selection device is connected with an output pin of the third selection device, the VCC pin of the fourth selection device is connected with the GND pin of the third selection device, and the GND pin of the fourth selection device is connected with the VCC pin of the third selection device;
and the VCC pin of the first selection device is connected with the VCC pin of the third selection device.
According to one embodiment of the invention, the first selection device, the second selection device, the third selection device and the fourth selection device are multiplexers.
According to one embodiment of the present invention, the first signal is a VCC signal and the second signal is a GND signal.
According to one embodiment of the present invention, the first selection device, the second selection device, the third selection device, and the fourth selection device are configured to connect the first input pin with the output pin when the input selection pin is at a low level, and to connect the second input pin with the output pin when the input selection pin is at a high level.
In another aspect of the embodiments of the present invention, there is also provided a server, including a power supply correction circuit, the power supply correction circuit including:
the first signal group comprises a first selection device and a second selection device, and a GND pin and a VCC pin of the first selection device are reversely connected with a GND pin and a VCC pin of the second selection device;
the second signal group comprises a third selection device and a fourth selection device, a GND pin and a VCC pin of the third selection device are reversely connected with a GND pin and a VCC pin of the fourth selection device, the GND pin of the third selection device is connected to the GND pin of the first selection device, and the VCC pin of the third selection device is connected with the VCC pin of the first selection device;
the first signal group is configured such that when the input terminal inputs the VCC signal or the GND signal, the output terminal of the first signal group provides the first signal to the downstream circuit, and the second signal group is configured such that when the input terminal inputs the VCC signal or the GND signal, the output terminal of the second signal group provides the second signal to the downstream circuit.
In accordance with one embodiment of the present invention,
the first signal group includes:
a first input pin of the first selection device is connected with a VCC pin, and a second input pin of the first selection device is connected with a GND pin and an input selection pin;
a first input pin of the second selection device is connected with a VCC pin, a second input pin of the second selection device is connected with a GND pin and an input selection pin, an output pin of the second selection device is connected with an output pin of the first selection device, the VCC pin of the second selection device is connected with the GND pin of the first selection device, and the GND pin of the second selection device is connected with the VCC pin of the first selection device;
the second signal group includes:
a first input pin of the third selection device is connected with the VCC pin and the input selection pin, and a second input pin of the third selection device is connected with the GND pin;
a first input pin of the fourth selection device is connected with the VCC pin and the input selection pin, a second input pin of the fourth selection device is connected with the GND pin, an output pin of the fourth selection device is connected with an output pin of the third selection device, the VCC pin of the fourth selection device is connected with the GND pin of the third selection device, and the GND pin of the fourth selection device is connected with the VCC pin of the third selection device;
and the VCC pin of the first selection device is connected with the VCC pin of the third selection device.
According to one embodiment of the invention, the first selection device, the second selection device, the third selection device and the fourth selection device are multiplexers.
According to one embodiment of the present invention, the first signal is a VCC signal and the second signal is a GND signal.
According to one embodiment of the present invention, the first selection device, the second selection device, the third selection device, and the fourth selection device are configured to connect the first input pin with the output pin when the input selection pin is at a low level, and to connect the second input pin with the output pin when the input selection pin is at a high level.
The invention has the following beneficial technical effects: in the power supply correction circuit provided by the embodiment of the invention, the first signal group is arranged, and when a VCC signal or a GND signal is input to the input end, the output end of the first signal group provides a first signal for the downlink circuit; the second signal group, the second signal group is configured to when input VCC signal or GND signal, the output of second signal group provides the technical scheme of second signal for descending the circuit, can make down circuit board normal work under the circumstances that the power connects conversely, has avoided the circuit board damage that the power joins conversely and arouses, reduces the cost of development product.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
Fig. 1 is a schematic diagram of a power supply correction circuit according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
In view of the above object, a first aspect of embodiments of the present invention proposes an embodiment of a power supply correction circuit. Fig. 1 shows a schematic diagram of the circuit.
As shown in fig. 1, the circuit includes:
a first signal group 1, the first signal group 1 including a first selection device (MUX1) and a second selection device (MUX2), a GND pin and a VCC pin of the first selection device (MUX1) being inversely connected to a GND pin and a VCC pin of the second selection device (MUX 2);
a second signal group 2, the second signal group 2 including a third selection device (MUX3) and a fourth selection device (MUX4), a GND pin and a VCC pin of the third selection device (MUX3) being connected in reverse to a GND pin and a VCC pin of the fourth selection device (MUX4), the GND pin of the third selection device (MUX3) being connected to the GND pin of the first selection device (MUX1), and the VCC pin of the third selection device (MUX3) being connected to the VCC pin of the first selection device (MUX 1);
the first signal group 1 is configured such that when the input terminal inputs the VCC signal or the GND signal, the output terminal of the first signal group 1 provides the first signal to the downstream circuit, and the second signal group 2 is configured such that when the input terminal inputs the VCC signal or the GND signal, the output terminal of the second signal group 2 provides the second signal to the downstream circuit.
By the technical scheme, the downlink circuit board can normally work under the condition that the power supply is reversely connected, the circuit board damage caused by reverse connection of the power supply is avoided, and the cost of developing products is reduced.
In a preferred embodiment of the present invention, the first signal group 1 includes: a first selection device (MUX1), a first input pin (B1) of which is connected with the VCC pin, and a second input pin (B2) of which is connected with the GND pin and the input selection pin (S); a second selection device (MUX2), wherein a first input pin (B1) of the second selection device is connected with a VCC pin, a second input pin (B2) is connected with a GND pin and an input selection pin (S), an output pin (A) of the first selection device is connected with an output pin (A) of the second selection device, a GND pin of the first selection device is connected with the VCC pin of the second selection device, and the VCC pin of the first selection device is connected with the GND pin of the second selection device;
the second signal group 2 includes: a third selection device (MUX3), the first input pin (B1) of which is connected with the VCC pin and the input selection pin (S), and the second input pin (B2) is connected with the GND pin; a fourth selection device (MUX4), wherein a first input pin (B1) of the fourth selection device is connected with a VCC pin and an input selection pin (S), a second input pin (B2) is connected with a GND pin, an output pin (A) of the third selection device is connected with an output pin (A) of the fourth selection device, a GND pin of the third selection device is connected with the VCC pin of the fourth selection device, and a VCC pin of the third selection device is connected with the GND pin of the fourth selection device;
the GND pin of the first selection device is connected with the GND pin of the third selection device, the VCC pin of the first selection device is connected with the VCC pin of the third selection device, and each input selection pin (S) is connected with a current-limiting resistor.
The circuit provided by the invention can be composed of four high-power-consumption MUX ICs and four current-limiting resistors, and the high-power-consumption MUX ICs can pass rated current. The circuit is placed on a downstream circuit board such as a Riser board or a BP board. The MUX IC needs to select a high-power IC meeting the power consumption requirement of a power supply, and a current-limiting resistor in the circuit mainly plays a role in current-limiting protection.
The VCC signal and the GND signal are power supply signals which are supplied to the circuit by the uplink mainboard through CABLE, and the two power supply signals output a VCC1 signal and a GND1 signal to a circuit board such as a downlink Riser board or a BP board after passing through a circuit which consists of four MUX ICs and four current-limiting resistors. The VCC and GND signals sent by the uplink main board through the CABLE can only be applied to the circuit, and power supplies required by other circuit parts in the downlink main board are provided by VCC1 and GND 1.
In a preferred embodiment of the invention, the first selection device, the second selection device, the third selection device and the fourth selection device are multiplexers.
In a preferred embodiment of the present invention, the first signal is a VCC signal and the second signal is a GND signal.
In a preferred embodiment of the present invention, the first selection device, the second selection device, the third selection device and the fourth selection device are configured such that the first input pin is connected to the output pin when the input selection pin is low, and the second input pin is connected to the output pin when the input selection pin is high.
Wherein the pin definition and pin selection functions of the MUX IC are shown in tables 1 and 2 below:
TABLE 1 Pin definition of MUX IC
B1 | Input |
B2 | Input |
A | Output |
S | Select input |
GND | Ground |
VCC | Power |
TABLE 2 Pin selection function of MUX IC
S | A(output) |
S=Low | A=B1 |
S=High | A=B2 |
When the VCC signal and GND signal of the circuit are connected to the circuit as shown in fig. 1, the voltage supplied to MUX1 and MUX3 meets the IC operation requirement, but the voltage supplied to MUX2 and MUX4 does not meet the IC operation requirement, so MUX1 and MUX3 can operate normally, and MUX2 and MUX4 do not operate. In this case, since MUX1 is set to Low by S, when a is B1 is VCC, power supply signal VCC1 to be output to the downstream circuit is set to VCC, and MUX3 is set to High by S, when a is B2 is GND, power supply signal GND1 to be output to the downstream circuit is set to GND.
When the VCC signal and the GND signal of the circuit are inserted into the circuit in the opposite manner to fig. 1, that is, the original VCC signal becomes the GND signal, and the original GND signal becomes the VCC signal. At this time, the voltage supplied to MUX2 and MUX4 meets the IC operation requirement, but the voltage supplied to MUX1 and MUX3 does not meet the IC operation requirement, so MUX2 and MUX4 can normally operate, and MUX1 and MUX3 do not operate. At this time, since MUX2 has S equal to GND equal to Low, a equal to B1 equal to VCC, power supply signal VCC1 output to the downstream circuit is equal to VCC. Since MUX4 has S ═ VCC High, a ═ B2 is GND, and the signal is output to down-link power supply signal GND1 is GND. As can be seen from the above, regardless of whether the uplink VCC signal and the GND signal are correctly connected, VCC1 signal and GND1 signal output to the downlink circuit are VCC1 — VCC and GND 1.
By the technical scheme, the downlink circuit board can normally work under the condition that the power supply is reversely connected, the circuit board damage caused by reverse connection of the power supply is avoided, and the cost of developing products is reduced.
It should be noted that, as will be understood by those skilled in the art, all or part of the processes in the methods of the above embodiments may be implemented by instructing relevant hardware through a computer program, and the above programs may be stored in a computer-readable storage medium, and when executed, the programs may include the processes of the embodiments of the methods as described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.
Furthermore, the method disclosed according to an embodiment of the present invention may also be implemented as a computer program executed by a CPU, and the computer program may be stored in a computer-readable storage medium. The computer program, when executed by the CPU, performs the above-described functions defined in the method disclosed in the embodiments of the present invention.
In view of the above object, a second aspect of embodiments of the present invention provides a server, including a power supply correction circuit, the power supply correction circuit including:
the first signal group comprises a first selection device and a second selection device, and a GND pin and a VCC pin of the first selection device are reversely connected with a GND pin and a VCC pin of the second selection device;
the second signal group comprises a third selection device and a fourth selection device, a GND pin and a VCC pin of the third selection device are reversely connected with a GND pin and a VCC pin of the fourth selection device, the GND pin of the third selection device is connected to the GND pin of the first selection device, and the VCC pin of the third selection device is connected with the VCC pin of the first selection device;
the first signal group is configured such that when the input terminal inputs the VCC signal or the GND signal, the output terminal of the first signal group provides the first signal to the downstream circuit, and the second signal group is configured such that when the input terminal inputs the VCC signal or the GND signal, the output terminal of the second signal group provides the second signal to the downstream circuit.
In a preferred embodiment of the present invention, the first signal group includes: a first input pin of the first selection device is connected with a VCC pin, and a second input pin of the first selection device is connected with a GND pin and an input selection pin; a first input pin of the second selection device is connected with a VCC pin, a second input pin of the second selection device is connected with a GND pin and an input selection pin, an output pin of the second selection device is connected with an output pin of the first selection device, the VCC pin of the second selection device is connected with the GND pin of the first selection device, and the GND pin of the second selection device is connected with the VCC pin of the first selection device;
the second signal group includes: a first input pin of the third selection device is connected with the VCC pin and the input selection pin, and a second input pin of the third selection device is connected with the GND pin; a first input pin of the fourth selection device is connected with the VCC pin and the input selection pin, a second input pin of the fourth selection device is connected with the GND pin, an output pin of the fourth selection device is connected with an output pin of the third selection device, the VCC pin of the fourth selection device is connected with the GND pin of the third selection device, and the GND pin of the fourth selection device is connected with the VCC pin of the third selection device;
and the VCC pin of the first selection device is connected with the VCC pin of the third selection device.
In a preferred embodiment of the invention, the first selection device, the second selection device, the third selection device and the fourth selection device are multiplexers.
In a preferred embodiment of the present invention, the first signal is a VCC signal and the second signal is a GND signal.
In a preferred embodiment of the present invention, the first selection device, the second selection device, the third selection device and the fourth selection device are configured such that the first input pin is connected to the output pin when the input selection pin is low, and the second input pin is connected to the output pin when the input selection pin is high.
It should be particularly noted that the embodiment of the system described above employs the embodiment of the method described above to specifically describe the working process of each module, and those skilled in the art can easily think that the modules are applied to other embodiments of the method described above.
Further, the above-described method steps and system elements or modules may also be implemented using a controller and a computer-readable storage medium for storing a computer program for causing the controller to implement the functions of the above-described steps or elements or modules.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
The embodiments described above, particularly any "preferred" embodiments, are possible examples of implementations and are presented merely to clearly understand the principles of the invention. Many variations and modifications may be made to the above-described embodiments without departing from the spirit and principles of the technology described herein. All such modifications are intended to be included within the scope of this disclosure and protected by the following claims.
Claims (10)
1. A power supply correction circuit, comprising:
the first signal group comprises a first selection device and a second selection device, and a GND pin and a VCC pin of the first selection device are reversely connected with a GND pin and a VCC pin of the second selection device;
a second signal group, which includes a third selection device and a fourth selection device, wherein the GND pin and the VCC pin of the third selection device are reversely connected with the GND pin and the VCC pin of the fourth selection device, the GND pin of the third selection device is connected to the GND pin of the first selection device, and the VCC pin of the third selection device is connected with the VCC pin of the first selection device;
the first signal group is configured to provide a first signal for a downlink circuit at an output end of the first signal group when a VCC signal or a GND signal is input to an input end, and the second signal group is configured to provide a second signal for the downlink circuit at an output end of the second signal group when the VCC signal or the GND signal is input to the input end.
2. The circuit of claim 1,
the first signal group includes:
a first selection device, wherein a first input pin of the first selection device is connected with a VCC pin, and a second input pin of the first selection device is connected with a GND pin and an input selection pin;
a first input pin of the second selection device is connected with a VCC pin, a second input pin of the second selection device is connected with a GND pin and an input selection pin, an output pin of the second selection device is connected with an output pin of the first selection device, the VCC pin of the second selection device is connected with the GND pin of the first selection device, and the GND pin of the second selection device is connected with the VCC pin of the first selection device;
the second signal group includes:
a first input pin of the third selection device is connected with a VCC pin and an input selection pin, and a second input pin of the third selection device is connected with a GND pin;
a first input pin of the fourth selection device is connected with a VCC pin and an input selection pin, a second input pin of the fourth selection device is connected with a GND pin, an output pin of the fourth selection device is connected with an output pin of the third selection device, the VCC pin of the fourth selection device is connected with the GND pin of the third selection device, and the GND pin of the fourth selection device is connected with the VCC pin of the third selection device;
and the GND pin of the first selection device is connected with the GND pin of the third selection device, and the VCC pin of the first selection device is connected with the VCC pin of the third selection device.
3. The circuit of claim 2, wherein the first select device, the second select device, the third select device, and the fourth select device are multiplexers.
4. The circuit of claim 2, wherein the first signal is a VCC signal and the second signal is a GND signal.
5. The circuit of claim 2, wherein the first selection device, the second selection device, the third selection device, and the fourth selection device are configured to connect the first input pin to the output pin when the input selection pin is low, and to connect the second input pin to the output pin when the input selection pin is high.
6. A server, the server comprising a power correction circuit, the power correction circuit comprising:
the first signal group comprises a first selection device and a second selection device, and a GND pin and a VCC pin of the first selection device are reversely connected with a GND pin and a VCC pin of the second selection device;
a second signal group, which includes a third selection device and a fourth selection device, wherein the GND pin and the VCC pin of the third selection device are reversely connected with the GND pin and the VCC pin of the fourth selection device, the GND pin of the third selection device is connected to the GND pin of the first selection device, and the VCC pin of the third selection device is connected with the VCC pin of the first selection device;
the first signal group is configured to provide a first signal for a downlink circuit at an output end of the first signal group when a VCC signal or a GND signal is input to an input end, and the second signal group is configured to provide a second signal for the downlink circuit at an output end of the second signal group when the VCC signal or the GND signal is input to the input end.
7. The server according to claim 6,
the first signal group includes:
a first selection device, wherein a first input pin of the first selection device is connected with a VCC pin, and a second input pin of the first selection device is connected with a GND pin and an input selection pin;
a first input pin of the second selection device is connected with a VCC pin, a second input pin of the second selection device is connected with a GND pin and an input selection pin, an output pin of the second selection device is connected with an output pin of the first selection device, the VCC pin of the second selection device is connected with the GND pin of the first selection device, and the GND pin of the second selection device is connected with the VCC pin of the first selection device;
the second signal group includes:
a first input pin of the third selection device is connected with a VCC pin and an input selection pin, and a second input pin of the third selection device is connected with a GND pin;
a first input pin of the fourth selection device is connected with a VCC pin and an input selection pin, a second input pin of the fourth selection device is connected with a GND pin, an output pin of the fourth selection device is connected with an output pin of the third selection device, the VCC pin of the fourth selection device is connected with the GND pin of the third selection device, and the GND pin of the fourth selection device is connected with the VCC pin of the third selection device;
and the GND pin of the first selection device is connected with the GND pin of the third selection device, and the VCC pin of the first selection device is connected with the VCC pin of the third selection device.
8. The server of claim 7, wherein the first selection device, the second selection device, the third selection device, and the fourth selection device are multiplexers.
9. The server of claim 7, wherein the first signal is a VCC signal and the second signal is a GND signal.
10. The server according to claim 7, wherein the first selection device, the second selection device, the third selection device, and the fourth selection device are configured to connect the first input pin with the output pin when the input selection pin is low, and to connect the second input pin with the output pin when the input selection pin is high.
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN201904618U (en) * | 2010-10-18 | 2011-07-20 | 奇鋐科技股份有限公司 | Circuit structure capable of connecting polarities of input power positively and reversely |
CN202363968U (en) * | 2011-12-14 | 2012-08-01 | 陕西千山航空电子有限责任公司 | Dual-power input selection and power reverse connection prevention circuit |
CN103346552A (en) * | 2013-06-25 | 2013-10-09 | 西安电子科技大学 | Reverse connection prevention circuit |
CN108281951A (en) * | 2018-02-09 | 2018-07-13 | 深圳奥特能电气有限公司 | A kind of electric power management circuit and power supply connecting device |
CN110504668A (en) * | 2019-09-27 | 2019-11-26 | 苏州浪潮智能科技有限公司 | A kind of DC power supply and machine input reverse-connection preventing circuit and server |
CN111061197A (en) * | 2019-12-31 | 2020-04-24 | Tcl空调器(中山)有限公司 | Control device and control method for reverse-plugging prevention circuit and household appliance |
-
2020
- 2020-06-20 CN CN202010569342.0A patent/CN111722691A/en active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN201904618U (en) * | 2010-10-18 | 2011-07-20 | 奇鋐科技股份有限公司 | Circuit structure capable of connecting polarities of input power positively and reversely |
CN202363968U (en) * | 2011-12-14 | 2012-08-01 | 陕西千山航空电子有限责任公司 | Dual-power input selection and power reverse connection prevention circuit |
CN103346552A (en) * | 2013-06-25 | 2013-10-09 | 西安电子科技大学 | Reverse connection prevention circuit |
CN108281951A (en) * | 2018-02-09 | 2018-07-13 | 深圳奥特能电气有限公司 | A kind of electric power management circuit and power supply connecting device |
CN110504668A (en) * | 2019-09-27 | 2019-11-26 | 苏州浪潮智能科技有限公司 | A kind of DC power supply and machine input reverse-connection preventing circuit and server |
CN111061197A (en) * | 2019-12-31 | 2020-04-24 | Tcl空调器(中山)有限公司 | Control device and control method for reverse-plugging prevention circuit and household appliance |
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