CN111450908B - Micro-fluidic pixel circuit and chip - Google Patents
Micro-fluidic pixel circuit and chip Download PDFInfo
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Abstract
The embodiment of the application discloses micro-fluidic pixel circuit and chip, this circuit includes: a voltage stabilizing circuit; the voltage stabilizing circuit is connected to two ends of the pixel working electrode and used for providing driving voltage for the pixel working electrode and stabilizing the driving voltage; the driving circuit is a level inverter circuit. Through the scheme of the embodiment, the microfluidic pixel circuit can still work normally under the condition that the electric leakage is increased by several orders of magnitude, so that the working stability is improved, and the service life is prolonged.
Description
Technical Field
The present disclosure relates to pixel circuit design, and more particularly to microfluidic pixel circuits and chips.
Background
In the processes of immunodetection, molecular detection, nucleic acid protein detection and gene sequencing sample pretreatment, a microfluidic chip is required. The micro-fluidic chip has the working principle that the surface tension between the liquid drop and the hydrophobic dielectric medium is changed by adjusting the potential applied between the liquid drop and the solid electrode, so that the contact angle between the liquid drop and the hydrophobic dielectric medium is changed, the liquid drop is asymmetrically deformed, the internal pressure difference is generated, and the operation and the control of the liquid drop are realized. The micro-fluidic chip can be divided into a passive type and an active type according to different back plate designs. The passive micro-fluidic chip is composed of a metal electrode, a dielectric layer and a hydrophobic layer, and a pixel working electrode (namely a pixel electrode) is directly connected with an operation signal through a metal wiring. The active micro-fluidic chip is composed of a metal electrode, an active semiconductor switch array layer, a dielectric layer and a hydrophobic layer, and the pixel working electrode is connected with an operation signal through the active semiconductor switch array.
At present, a common micro-fluidic chip on the market is a passive chip, a processing technology is usually a PCB (printed circuit board) technology or other similar micro-nano processing technologies, and a pixel working electrode is large. The passive chip has the advantages of simple design and manufacturing process and low cost, and has the defects of incapability of simultaneously controlling a plurality of liquid drops, large movable minimum liquid drop volume and consumption of a plurality of biological samples. In addition, the moving path of the liquid drop of the passive microfluidic chip is relatively fixed, and if the moving scheme of the liquid drop needs to be modified, the microfluidic chip needs to be redesigned. The number of array units in the unit area of the active micro-fluidic chip can be greatly increased, the control number of liquid drops is obviously improved compared with that of a passive chip, and the minimum controllable liquid drop volume is smaller. In addition, the liquid drop moving path of the active micro-fluidic chip can be flexibly and repeatedly modified, and the method can be suitable for more liquid drop moving schemes. The pixel circuit of a common active microfluidic chip is generally composed of a Thin Film Transistor (TFT) and a capacitor (fig. 1), and the voltage writing and holding of the pixel working electrode is completed by turning on and off the TFT (see fig. 2 for driving logic), so as to drive the droplet above the pixel working electrode to move. However, the above active microfluidic chip also has some problems: due to the higher operating voltage for droplet movement, the insulating layer and TFT transistor are subjected to higher stress, resulting in increased capacitance and TFT leakage current (fig. 3), and the voltage of the pixel working electrode will not be well maintained (fig. 4). When the voltage of the pixel working electrode is reduced to be lower than the movable driving voltage of the liquid drop, the liquid drop cannot move normally, and the micro-fluidic chip fails.
Disclosure of Invention
The embodiment of the application provides a micro-fluidic pixel circuit and a micro-fluidic pixel chip, which can still work normally under the condition that the electric leakage is increased by a plurality of orders of magnitude, so that the working stability is improved, and the service life is prolonged.
An embodiment of the present application provides a microfluidic pixel circuit, which may include: a voltage stabilizing circuit;
the voltage stabilizing circuit is connected to two ends of the pixel working electrode and used for providing driving voltage for the pixel working electrode and stabilizing the driving voltage;
wherein, the driving circuit is a level inverter circuit; the level inverting circuit is as follows: when inputting high voltage, outputting low voltage; or, when inputting low voltage, outputting high voltage; the high voltage is a voltage with a voltage value greater than or equal to a first preset threshold value; the low voltage is a voltage with a voltage value less than or equal to a second preset threshold value; the first preset threshold is greater than or equal to the second preset threshold.
In an exemplary embodiment of the present application, the voltage stabilizing circuit may include: a plurality of power supply thin film transistors TFT; the level inversion circuit is constituted by a plurality of TFTs; or,
the voltage stabilizing circuit may include: at least one TFT and at least one resistor; the level inverting circuit is constituted by the at least one TFT and the at least one resistor.
In an exemplary embodiment of the present application, when the voltage stabilizing circuit includes a plurality of power supplying thin film transistors TFTs, the plurality of TFTs may include:
a plurality of P-type TFTs;
a plurality of N-type TFTs; or,
at least one P-type TFT and at least one N-type TFT.
In an exemplary embodiment of the present application, the plurality of TFTs may be two TFTs, and may include: a first P-type TFT and a first N-type TFT;
the grid electrodes of the first P-type TFT and the first N-type TFT are set to receive a first control signal;
the source electrode of the first P-type TFT is set to receive a second control signal;
the drain electrode of the first P-type TFT is connected with the first end of the pixel working electrode;
the source electrode of the first N-type TFT is connected with the first end of the pixel working electrode;
the drain electrode of the first N-type TFT and the second end of the pixel working electrode are connected with a first common electrode;
or,
the grid electrodes of the first P-type TFT and the first N-type TFT are set to receive a first control signal;
the drain electrode of the first N-type TFT is connected with a second common electrode;
the source electrode of the first N-type TFT is connected with the first end of the pixel working electrode;
the drain electrode of the first P-type TFT is connected with the first end of the pixel working electrode;
the source of the first P-type TFT is connected to the second end of the pixel working electrode and configured to receive a second control signal.
In an exemplary embodiment of the present application, the plurality of TFTs may be two TFTs, and may include: a second P-type TFT and a third P-type TFT;
the grid electrode of the second P-type TFT is set to receive a first control signal;
the source electrode of the second P-type TFT is set to receive a second control signal;
the drain electrode of the second P-type TFT is connected with the pixel working electrode;
the grid electrode and the source electrode of the third P-type TFT are connected and are connected with the first end of the pixel working electrode;
the drain electrode of the third P-type TFT and the second end of the pixel working electrode are connected with a first common electrode;
or,
the grid electrode of the second P-type TFT is connected with the drain electrode of the second P-type TFT and is connected with the first end of the pixel working electrode;
the source electrode of the second P-type TFT is connected with a second common electrode;
the grid electrode of the third P-type TFT is arranged to receive a first control signal;
the source electrode of the third P-type TFT is connected with the drain electrode of the second P-type TFT and the first end of the pixel working electrode;
the drain of the third P-type TFT is connected to the second end of the pixel working electrode and configured to receive a second control signal.
In an exemplary embodiment of the present application, the plurality of TFTs is two TFTs, and may include: a second N-type TFT and a third N-type TFT;
the grid electrode of the second N-type TFT is connected with the source electrode of the second N-type TFT and is connected with the first end of the pixel working electrode;
the drain electrode of the second N-type TFT is connected with a second common electrode;
a gate of the third N-type TFT is configured to receive a first control signal;
the drain electrode of the third N-type TFT is connected with the source electrode of the second N-type TFT and the first end of the pixel working electrode;
the source electrode of the third N-type TFT is connected with the second end of the pixel working electrode and is configured to receive a second control signal;
or,
the grid electrode of the second N-type TFT is connected with the drain electrode of the second N-type TFT and is connected with a second common electrode;
the source electrode of the second N-type TFT is connected with the first end of the pixel working electrode;
a gate of the third N-type TFT is configured to receive a first control signal;
the drain electrode of the third N-type TFT is connected with the source electrode of the second N-type TFT and the first end of the pixel working electrode;
and the source electrode of the third N-type TFT is connected with the second end of the pixel working electrode and is configured to receive a second control signal.
In an exemplary embodiment of the present application, the plurality of TFTs may be four TFTs, and may include: a fourth P-type TFT, a fifth P-type TFT, a sixth P-type TFT, and a seventh P-type TFT;
the grid electrodes of the fourth P-type TFT and the sixth P-type TFT are connected and are set to receive a first control signal;
the source electrodes of the fourth P-type TFT and the sixth P-type TFT are arranged to receive a second control signal;
the drain electrode of the fourth P-type TFT is connected with the grid electrode of the seventh P-type TFT;
the grid electrode of the fifth P-type TFT is connected with the source electrode of the fifth P-type TFT, and is connected with the drain electrode of the fourth P-type TFT and the grid electrode of the seventh P-type TFT;
the drain electrode of the fifth P-type TFT is connected with the first common electrode;
the drain electrode of the sixth P-type TFT is connected with the source electrode of the seventh P-type TFT and is connected with the first end of the pixel working electrode;
the drain electrode of the seventh P-type TFT is connected with the first common electrode;
or,
the fourth P-type TFT is connected with the grid electrode of the sixth P-type TFT and is set to receive a first control signal;
the source electrodes of the fourth P-type TFT and the sixth P-type TFT are arranged to receive a second control signal;
the drain electrode of the fourth P-type TFT is connected with the grid electrode of the seventh P-type TFT;
the grid electrode of the fifth P-type TFT is connected with the drain electrode of the fifth P-type TFT and is connected with a second common electrode;
the source electrode of the fifth P-type TFT is connected with the drain electrode of the fourth P-type TFT and is connected with the grid electrode of the seventh P-type TFT;
the drain electrode of the sixth P-type TFT is connected with the source electrode of the seventh P-type TFT and is connected with the first end of the pixel working electrode;
and the drain electrode of the seventh P-type TFT is connected with the first common electrode.
In an exemplary embodiment of the present application, the voltage stabilizing circuit may further include: a first capacitor;
one substrate of the first capacitor is connected with the grid electrode of the seventh P-type TFT, the drain electrode of the fourth P-type TFT and the source electrode of the fifth P-type TFT, and the other substrate is arranged to receive the first control signal.
In an exemplary embodiment of the present application, the plurality of TFTs may be four TFTs, and may include: a fourth N-type TFT, a fifth N-type TFT, a sixth N-type TFT, and a seventh N-type TFT;
the fourth N-type TFT is connected with the grid electrode of the sixth N-type TFT and is set to receive a first control signal;
drains of the fourth N-type TFT and the sixth N-type TFT are configured to receive a second control signal;
the source electrode of the fourth N-type TFT is connected with the grid electrode of the seventh N-type TFT;
the grid electrode of the fifth N-type TFT is connected with the source electrode of the fifth N-type TFT and is connected with a second common electrode;
the drain electrode of the fifth N-type TFT is connected with the source electrode of the fourth N-type TFT and is connected with the grid electrode of the seventh N-type TFT;
the source electrode of the sixth N-type TFT is connected with the drain electrode of the seventh N-type TFT and is connected with the first end of the pixel working electrode;
the source electrode of the seventh N-type TFT and the second end of the pixel working electrode are connected with a first common electrode;
or,
the fourth N-type TFT is connected with the grid electrode of the sixth N-type TFT and is set to receive a first control signal;
drains of the fourth N-type TFT and the sixth N-type TFT are configured to receive a second control signal;
the source electrode of the fourth N-type TFT is connected with the grid electrode of the seventh N-type TFT;
a grid electrode of the fifth N-type TFT is connected with a drain electrode of the fifth N-type TFT and is connected with a grid electrode of the seventh N-type TFT;
the source electrode second common electrode of the fifth N-type TFT is connected;
the source electrode of the sixth N-type TFT is connected with the drain electrode of the seventh N-type TFT and is connected with the first end of the pixel working electrode;
and the source electrode of the seventh N-type TFT is connected with the second end of the pixel working electrode and is connected with the second common electrode.
In an exemplary embodiment of the present application, the voltage stabilizing circuit may further include: a second capacitor;
one substrate of the second capacitor is connected with the grid electrode of the seventh P-type TFT, the source electrode of the fourth P-type TFT and the drain electrode of the fifth P-type TFT, and the other substrate is arranged to receive the first control signal.
The embodiment of the present application further provides a microfluidic pixel chip, which may include: a microfluidic pixel circuit as claimed in any one of the above.
Compared with the related art, the microfluidic pixel circuit of the embodiment of the present application may include: a voltage stabilizing circuit; the voltage stabilizing circuit is connected to two ends of the pixel working electrode and used for providing driving voltage for the pixel working electrode and stabilizing the driving voltage; the driving circuit is a level inverter circuit. Through the scheme of the embodiment, the microfluidic pixel circuit can still work normally under the condition that the electric leakage is increased by several orders of magnitude, so that the working stability is improved, and the service life is prolonged.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. Other advantages of the present application may be realized and attained by the instrumentalities and combinations particularly pointed out in the specification and the drawings.
Drawings
The accompanying drawings are included to provide an understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not to limit the disclosure.
FIG. 1 is a schematic diagram of a microfluidic pixel circuit in the related art;
FIG. 2 is a schematic diagram of a driving timing sequence of a 1T1C microfluidic pixel circuit in the related art;
FIG. 3 is a schematic diagram of a pixel working electrode voltage drop caused by leakage in a microfluidic pixel circuit according to the related art;
fig. 4 is a block diagram of a microfluidic pixel circuit according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a CMOS pixel driving circuit according to an embodiment of the present invention;
FIG. 6 is a diagram of a second CMOS pixel driving circuit according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a P-type Zero-Vgs pixel driver circuit according to an embodiment of the present application;
FIG. 8 is a schematic diagram of a P-type Load pixel driving circuit according to an embodiment of the present disclosure;
FIG. 9 is a schematic diagram of an N-type Zero-Vgs pixel driver circuit according to an embodiment of the present application;
FIG. 10 is a schematic diagram of an N-type Load pixel driving circuit according to an embodiment of the present disclosure;
FIG. 11 is a diagram of a P-type 4T1C-Zero-Vgs pixel configuration in accordance with an embodiment of the present application;
FIG. 12 is a diagram of a P-type 4T1C-load pixel structure according to an embodiment of the present application;
fig. 13 is a structural view of a P-type 4T-Zero-Vgs type pixel of an embodiment of the present application;
FIG. 14 is a diagram of a P-type 4T-load pixel structure according to an embodiment of the present application;
fig. 15 is a structural view of a P-type 4T-Zero-Vgs type pixel of an embodiment of the present application;
FIG. 16 is a diagram of a P-type 4T-load pixel structure according to an embodiment of the present application;
FIG. 17 is a diagram of a P-type 4T1C-Zero-Vgs pixel configuration in accordance with an embodiment of the present application;
FIG. 18 is a diagram of a P-type 4T1C-load pixel structure according to an embodiment of the present application.
Detailed Description
The present application describes embodiments, but the description is illustrative rather than limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or instead of any other feature or element in any other embodiment, unless expressly limited otherwise.
The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive concept as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive aspects to form yet another unique inventive aspect, as defined by the claims. Thus, it should be understood that any of the features shown and/or discussed in this application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not limited except as by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.
Further, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other sequences of steps are possible as will be appreciated by those of ordinary skill in the art. Therefore, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Further, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present application.
An embodiment of the present application provides a microfluidic pixel circuit, as shown in fig. 4, which may include: a voltage stabilizing circuit 1;
the voltage stabilizing circuit 1 is connected to two ends of the pixel working electrode 2 and is used for providing a driving voltage for the pixel working electrode and stabilizing the driving voltage;
wherein, the driving circuit is a level inverter circuit; the level inverting circuit is as follows: when inputting high voltage, outputting low voltage; or, when inputting low voltage, outputting high voltage; the high voltage is a voltage with a voltage value greater than or equal to a first preset threshold value; the low voltage is a voltage with a voltage value less than or equal to a second preset threshold value; the first preset threshold is greater than or equal to the second preset threshold.
In the exemplary embodiment of the present application, in order to solve the problem that an active type microfluidic pixel chip (microfluidic pixel circuit) is prone to failure at a high operating voltage, the embodiment of the present application provides a new active type microfluidic pixel circuit design, where the circuit may be formed by connecting a voltage stabilizing circuit formed by a level inverting circuit to a pixel working electrode, for example, the voltage stabilizing circuit may include k1 TFTs (Thin film transistors) and k1 ≧ 2, and may further include k2 resistors, where k2 ≧ 0 and k3 capacitors, and k3 ≧ 0. Compared with the common active micro-fluidic pixel formed by one TFT and one capacitor, the pixel has low requirement on the switching characteristic of the TFT, and can still normally work even if the leakage of the TFT is increased by several orders of magnitude, so that the stability of the micro-fluidic chip can be improved and the service life of the micro-fluidic chip can be prolonged.
In an exemplary embodiment of the present application, the voltage stabilizing circuit 1 may include: a plurality of TFTs; the level inversion circuit is constituted by a plurality of TFTs; or,
the voltage stabilizing circuit may include: at least one TFT and at least one resistor; the level inverting circuit is constituted by the at least one TFT and the at least one resistor.
In an exemplary embodiment of the present application, the resistor may be a large-resistance resistor, and the specific resistance value is not limited herein, and may be set accordingly according to different application circuits.
In an exemplary embodiment of the present application, when the voltage stabilizing circuit includes a plurality of power supplying thin film transistors TFTs, the plurality of TFTs may include:
a plurality of P-type TFTs;
a plurality of N-type TFTs; or,
at least one P-type TFT and at least one N-type TFT.
In the exemplary embodiment of the present application, the voltage stabilizing circuit may be formed by a plurality of P-type TFTs, a plurality of N-type TFTs, or a mixture of P-type TFTs and N-type TFTs, and in any of these configurations, the voltage stabilizing circuit is used to connect into an inverter (i.e., a level inversion circuit) to achieve the purpose of voltage stabilization through level inversion (i.e., changing from high level to low level, or from low level to high level).
In the exemplary embodiment of the present application, at least one P-type TFT or at least one N-type TFT in each of the above-mentioned configurations may be replaced by a large resistor, and the purpose of voltage stabilization may also be achieved.
In the exemplary embodiments of the present application, detailed embodiments when the voltage stabilizing circuit includes a plurality of TFTs are given below. Hereinafter, the high voltage and the high level are the same, and the low voltage and the low level are the same.
The first scheme is as follows: (when the voltage regulator circuit includes at least one P-type TFT and at least one N-type TFT)
In an exemplary embodiment of the present application, the plurality of TFTs may be two TFTs, and may include: a first P-type TFT and a first N-type TFT;
as shown in fig. 5 (CMOS type pixel driving circuit one):
the gates of the first P-type TFT (TP1) and the first N-type TFT (TN1) are configured to receive a first control signal;
the source of the first P-type TFT (TP1) is configured to receive a second control signal;
the drain electrode of the first P-type TFT (TP1) is connected with the first end (Q end) of the pixel working electrode;
the source electrode of the first N-type TFT (TN1) is connected to the first end (Q end) of the pixel working electrode;
the drain electrode of the first N-type TFT (TN1) and the second end of the pixel working electrode are connected to a first common electrode (COM).
Alternatively, as shown in fig. 6 (CMOS type pixel drive circuit two):
the gates of the first P-type TFT (TP1) and the first N-type TFT (TN1) are configured to receive a first control signal;
the drain electrode of the first N-type TFT (TN1) is connected to a second common electrode (VDD);
the source electrode of the first N-type TFT (TN1) is connected with the first end (Q end) of the pixel working electrode;
the drain electrode of the first P-type TFT (TP1) is connected to the first end (Q-end) of the pixel working electrode;
the source of the first P-type TFT (TP1) is coupled to the second terminal of the pixel working electrode and is configured to receive a second control signal.
In the exemplary embodiment of the present application, the operation principle of the circuit shown in fig. 5 (a CMOS type pixel driving circuit) is described below by taking as an example:
1. pixel electrode Q point high voltage writing:
when the first control signal is sent to low level (the voltage signal is less than or equal to the second preset threshold), the TP1 tube is turned on, and the TN1 tube is turned off. TP1 is in an electrically conducting state, and the Q point of the pixel working electrode will become high when the second control signal is high.
2. Pixel electrode Q point low voltage write:
a. when the first control signal is given to high level (voltage signal which is greater than or equal to a first preset threshold), the TP1 tube is closed, and the TN1 tube is opened; the Q point of the pixel will always be at a low voltage (COM);
b. the first control signal is low, the tube TP1 is open, the second control signal is low, and the Q point becomes low.
3. Droplet movement: through signal configuration, the Q point of the pixel working electrode of one area pixel on the array can be set to be high voltage, while the Q point of the pixel working electrode of other area pixels is set to be low voltage, so that the liquid drop is positioned on the high voltage area. Taking the driving of the liquid drop moving to the right as an example, the signal configuration is changed, so that the voltage of the pixel electrode adjacent to the right side of the high voltage is changed from the low voltage to the high voltage, the voltage of the pixel working electrode on the left side is changed from the high voltage to the low voltage, and thus, the area with the high voltage moves to the right, and the liquid drop moves along with the area with the high voltage and moves to the right.
In an exemplary embodiment of the present application, the stability improvement principle of the first scheme is as follows:
1. consider the case where the leakage of the TFT increases: for a conventional 1T1C (i.e. a TFT, a capacitor) pixel circuit, after the TFT leakage increases, the Q-point voltage of the pixel operating point will decay, so that the liquid drop cannot move. The pixel architecture provided by the first scheme can improve the influence of leakage on voltage retention, and the principle is as follows:
a. case where the pixel working electrode is high voltage: TP1 is in the on state and TN1 is in the off state. The current in the T1 on state is much larger than the leakage current of TP1/TN1, so the increase of the TFT leakage does not affect the Q point voltage of the pixel.
b. Case where the pixel operation electrode is low voltage: TP1 is in the OFF state and TN1 is in the ON state. The current in the on state of TN1 is much larger than the leakage current of TFT, so the leakage current of TFT increases and the Q point voltage of pixel does not change.
2. Consider the case of increased leakage current at the drop end: for the conventional 1T1C pixel circuit, after the leakage current at the droplet end is increased, the voltage at the Q point of the pixel working point will be attenuated, so that the droplet cannot move. The pixel architecture provided by the first scheme can improve the influence of leakage on voltage retention, and the principle is as follows:
a. case where the pixel working electrode is high voltage: TP1 is in the on state and TN1 is in the off state. The current in the on state of TP1 is much larger than the leakage current of the droplet, so the increase of the leakage current of the droplet does not affect the Q-point voltage of the pixel;
b. case where the pixel operation electrode is low voltage: TP1 is in the OFF state and TN1 is in the ON state. The current in the on state of TN1 is much larger than the leakage current of the droplet, so the increase in the droplet side leakage current does not affect the Q-point voltage of the pixel.
In the exemplary embodiment of the present application, when the first control signal is given to high level (higher voltage signal), the TP1 tube is turned off, the TN1 tube is turned on, and the Q point of the pixel working electrode will become low level (common electrode voltage). When the first control signal is low (lower voltage signal), the source and drain of TP1 are in electrical communication. The voltage at the pixel working electrode of the microfluidic chip (which may contain the microfluidic pixel circuit) will be in electrical communication with the second control signal via TP 1. When the second control signal is high voltage, the pixel working electrode of the microfluidic chip is at high voltage; when the second control signal is given to low voltage, the pixel working electrode of the microfluidic chip is in a low voltage state. The voltage on the pixel electrode of the microfluidic chip can be regulated and controlled by matching the first control signal with the second control signal.
In the exemplary embodiment of the present application, for a microfluidic chip with m rows and n columns, there is a droplet in the area of the pixel region (x, y), (x + i, y + j), and the operation of the microfluidic chip with the pixel circuit is illustrated by taking the case where the droplet moves to the right by h columns as an example. The first control signals of the x-th row to the x + j-th row are given a low level, and the first control signals of the other rows are all given a high level. The second control signals of the y-th and y + h-th columns are applied to a low voltage, and the second control signals of the y + j +1 to y + j + h-th columns are applied to a high voltage. Thus, the high voltage area will move from (x, y), (x + i, y + j) to (x, y + h), (x + i, y + j + h), and the droplet will move from (x, y), (x + i, y + j) to (x, y + h), (x, y + j + h) because the droplet will move from the low voltage area to the high voltage area, thereby achieving the purpose that the droplet moves to the right for h rows.
Scheme II: (when the voltage regulator circuit includes a plurality of P-type TFTs)
In an exemplary embodiment of the present application, the plurality of TFTs may be two TFTs, and may include: a second P-type TFT and a third P-type TFT;
as shown in fig. 7 (P-type Zero-Vgs type pixel driving circuit):
the gate of the second P-type TFT (TP2) is configured to receive a first control signal;
the source of the second P-type TFT (TP2) is configured to receive a second control signal;
the drain electrode of the second P-type TFT (TP2) is connected with the first end (Q end) of the pixel working electrode;
the grid electrode and the source electrode of the third P type TFT (TP3) are connected, and the third P type TFT is connected with the first end of the pixel working electrode;
a drain electrode of the third P-type TFT (TP3) and a second end of the pixel working electrode are connected to a first common electrode;
alternatively, as shown in fig. 8 (P-type Load-type pixel driving circuit):
the grid electrode of the second P-type TFT (TP2) is connected with the drain electrode of the second P-type TFT (TP2) and is connected with the first end of the pixel working electrode;
the source electrode of the second P-type TFT (TP2) is connected with a second common electrode (VDD);
the gate of the third P-type TFT (TP3) is configured to receive a first control signal;
the source electrode of the third P-type TFT (TP3) is connected with the drain electrode of the second P-type TFT (TP2) and the first end of the pixel working electrode;
the drain of said third P-type TFT (TP3) is connected to the second terminal of said pixel working electrode and arranged to receive a second control signal.
In the exemplary embodiment of the present application, the operation principle of the circuit shown in fig. 7 (Zero-Vgs type pixel driving circuit) is described below by taking as an example the circuit:
1. pixel Q-point high voltage write:
the first control signal is low (lower voltage signal), the tube TP2 is turned on, the second control signal is high, and the Q point will also become high.
2. Pixel Q-point low voltage write:
a. the first control signal goes high (higher voltage signal), the tube TP2 is turned off, and the Q point of the pixel is low voltage (COM).
b. The first control signal is low (lower voltage signal), the tube TP2 is turned on, the second control signal is low, and the Q point becomes low.
3. Droplet movement: through signal configuration, the pixel working electrode Q point of one area pixel on the array can be set to be at a high voltage, and the pixel working electrode Q point of other area pixels can be set to be at a low voltage, so that liquid drops are positioned on the high voltage area. Taking the driving of the droplet moving to the right as an example, the signal configuration is changed to change the high voltage to the pixel adjacent to the right side of the high voltage from the low voltage to the high voltage, and to change the high voltage to the low voltage to the pixel on the left side of the high voltage, so that the high voltage area moves to the right, and the droplet moves to the right along with the high voltage area because the droplet moves along with the high voltage area.
In the exemplary embodiment of the present application, the stability improvement principle of the second scheme is as follows:
1. case where leakage of TFT increases: for the conventional 1T1C pixel circuit, after the leakage of the TFT tube increases, the voltage at the Q point of the pixel working point will be attenuated, so that the liquid drop cannot move. The pixel architecture provided by the scheme of the embodiment can improve the influence of leakage on voltage retention, and the principle is as follows:
a. case where the pixel working electrode is high voltage: TP2 is in the on state and TP3 is in the off state. Since the current in the on state of TP2 is much larger than the leakage current of TP2/TP3, the increase of TP2/TP3 leakage does not affect the Q point voltage of the pixel.
b. Case where the pixel operation electrode is low voltage: TP2 is in the OFF state and TP3 is in the ON state. Since the current of TP3 in the on state is much larger than the leakage current of TP2/TP3, the increase of TP2/TP3 leakage does not affect the Q point voltage of the pixel.
2. Considering the situation of increased droplet leakage current, for the conventional 1T1C pixel circuit, after the droplet leakage current is increased, the voltage at the Q point of the pixel operating point will be attenuated, so that the droplet cannot move. The pixel architecture provided by the scheme of the embodiment can improve the influence of leakage on voltage retention, and the principle is as follows:
a. case where the pixel electrode is high voltage: at this time, the tube TP2 is in the on state, and the on-state current of TP2 is much larger than the leakage current of the droplet side, so the increase of the droplet leakage does not affect the Q-point voltage of the pixel.
b. Case where the pixel electrode is at a low voltage: at this time, the TP2 transistor is in the off state, and since the current of TP3 is much larger than the leakage current of the droplet, the increase of the leakage current of the droplet does not affect the Q-point voltage of the pixel.
In the exemplary embodiment of the present application, taking the P-type Zero-Vgs as an example, when the first control signal gives a certain voltage signal, the certain voltage signal can make TP2 turn off, and at this time, the source and drain of TP2 will be in a non-conductive state. The pixel electrode of the micro-fluidic chip transfers charges to the first common electrode COM through TP3, and finally the voltage of the pixel working electrode approaches or equals to the voltage of the first common electrode, so that the purpose of writing low voltage into the pixel working electrode is realized. When the first control signal gives another determined voltage signal, the determined voltage signal can enable TP2 to be switched on, and the source and the drain of TP2 are in an electric communication state. The voltage at the pixel working electrode of the microfluidic chip will be in electrical communication with the second control signal via TP 2. When the second control signal is high voltage, the pixel working electrode of the microfluidic chip is at high voltage; when the second control signal is given to low voltage, the pixel working electrode of the microfluidic chip is in a low voltage state. The voltage on the pixel working electrode of the micro-fluidic chip can be regulated and controlled by matching the first control signal with the second control signal.
In the exemplary embodiment of the present application, taking P-type Zero-Vgs as an example, for a microfluidic chip with m rows and n columns, a droplet exists in the area of the pixel region (x, y), (x + i, y + j), and the operation of the microfluidic chip with the pixel circuit is illustrated by taking the case that the droplet moves to the right h. The first control signals capable of enabling the TFTs in the pixels to be turned on are supplied to the x-th row to the x + j-th row, and the first control signals capable of enabling the TFTs in the pixels to be turned off are supplied to the other rows. The y-th and y + h-th columns supply the low voltage second control signal, and the y + j +1 to y + j + h-th columns supply the high voltage second control signal. Thus, the high voltage area will move from (x, y), (x + i, y + j) to (x, y + h), (x + i, y + j + h), and the droplet will move from (x, y), (x + i, y + j) to (x, y + h), (x, y + j + h) because the droplet will move from the low voltage area to the high voltage area, thereby achieving the purpose that the droplet moves to the right for h rows.
The third scheme is as follows: (when the voltage regulator circuit includes a plurality of N-type TFTs)
In the exemplary embodiment of the present application, the second scheme is a P-type TFT configuration, and the second scheme is an N-type TFT configuration.
In an exemplary embodiment of the present application, the plurality of TFTs is two TFTs, and may include: a second N-type TFT (TN2) and a third N-type TFT (TN 3);
as shown in fig. 9 (N-type Zero-Vgs type pixel circuit):
the grid electrode of the second N-type TFT (TN2) is connected with the source electrode of the second N-type TFT (TN2), and is connected with the first end of the pixel working electrode;
the drain electrode of the second N-type TFT (TN2) is connected to a second common electrode (VDD);
the gate of the third N-type TFT (TN2) is configured to receive a first control signal;
a drain electrode of the third N-type TFT (TN3) is connected to a source electrode of the second N-type TFT (TN2) and a first end (Q end) of the pixel working electrode;
the source of the third N-type TFT (TN3) is coupled to the second terminal of the pixel working electrode and is configured to receive a second control signal.
Alternatively, as shown in fig. 10 (N-type load type pixel circuit):
the grid electrode of the second N-type TFT (TN2) is connected with the drain electrode of the second N-type TFT (TN2) and is connected with a second common electrode (VDD);
the source electrode of the second N-type TFT (TN2) is connected to the first end (Q end) of the pixel working electrode;
the gate of the third N-type TFT (TN3) is configured to receive a first control signal;
the drain electrode of the third N-type TFT (TN3) is connected to the source electrode of the second N-type TFT (TN2) and the first end of the pixel working electrode;
the source of the third N-type TFT (TN3) is coupled to the second terminal of the pixel working electrode and is configured to receive a second control signal.
In the exemplary embodiment of the present application, the principle of the third scheme is substantially the same as that of the second scheme, and details are not repeated here.
And the scheme is as follows: (when the voltage stabilizing circuit comprises a plurality of P-type TFTs)
In an exemplary embodiment of the present application, the plurality of TFTs may be four TFTs, and may include: a fourth P-type TFT (TP4), a fifth P-type TFT (TP5), a sixth P-type TFT (TP6), and a seventh P-type TFT (TP 7);
as shown in fig. 11 (structure diagram of P-type 4T-Zero-Vgs type pixel):
the gates of the fourth P-type TFT (TP4) and the sixth P-type TFT (TP6) are connected and configured to receive a first control signal;
the sources of the fourth P-type TFT (TP4) and the sixth P-type TFT (TP6) are arranged to receive a second control signal;
the drain electrode of the fourth P type TFT (TP4) is connected with the gate electrode of the seventh P type TFT (TP 7);
a gate electrode of the fifth P-type TFT (TP5) is connected to a source electrode of the fifth P-type TFT (TP5), and is connected to a drain electrode of the fourth P-type TFT and a gate electrode of the seventh P-type TFT;
the drain electrode of the fifth P type TFT (TP5) is connected with the first common electrode;
the drain electrode of the sixth P-type TFT (TP6) is connected to the source electrode of the seventh P-type TFT (TP7), and is connected to the first end (Q-end) of the pixel working electrode;
the drain electrode of the seventh P-type TFT (TP7) is connected with the first common electrode (COM);
alternatively, as shown in fig. 12 (P-type 4T-load type pixel structure diagram):
the gates of the fourth P-type TFT (TP4) and the sixth P-type TFT (TP6) are connected and configured to receive a first control signal;
the sources of the fourth P-type TFT (TP4) and the sixth P-type TFT (TP6) are arranged to receive a second control signal;
the drain electrode of the fourth P type TFT (TP4) is connected with the gate electrode of the seventh P type TFT (TP 7);
the gate electrode of the fifth P-type TFT (TP5) is connected to the drain electrode of the fifth P-type TFT (TP5) and to the second common electrode;
the source electrode of the fifth P-type TFT (TP5) is connected with the drain electrode of the fourth P-type TFT (TP4) and is connected with the gate electrode of the seventh P-type TFT (TP 7);
the drain electrode of the sixth P-type TFT (TP6) is connected with the source electrode of the seventh P-type TFT (TP7) and is connected with the first end of the pixel working electrode;
the drain electrode of the seventh P-type TFT (TP7) is connected to the first common electrode (COM).
In an exemplary embodiment of the present application, as shown in fig. 13 (P-type 4T1C-Zero-Vgs type pixel structure diagram) and fig. 12 (P-type 4T1C-load type pixel structure diagram), in the schemes of fig. 11 and 12, the voltage stabilizing circuit may further include: a first capacitance C1;
one substrate of the first capacitor C1 is connected to the gate of the seventh P-type TFT (TP7), the drain of the fourth P-type TFT (TP4) and the source of the fifth P-type TFT (TP5), and the other substrate is configured to receive the first control signal.
In the exemplary embodiment of the present application, the operation principle of the circuit shown in fig. 11 (P-type 4T1C-Zero-Vgs type pixel circuit) is described below by way of example:
1. pixel Q-point high voltage write:
the first control signal is low, TP6 is on, TP7 is off, the second control signal is high, and the Q point will also become high.
2. Pixel Q-point low voltage write:
a. when the first control signal goes high, TP6 is turned off, TP7 is turned on, and the Q point of the pixel is at a low voltage (COM).
b. The first control signal is low, TP6 is on, TP7 is off, the second control signal is low, and the Q point becomes low.
3. Droplet movement: through signal configuration, the pixel working electrode Q point of one area pixel on the array can be set to be at a high voltage, and the pixel working electrode Q point of other area pixels can be set to be at a low voltage, so that liquid drops can be positioned on a high voltage area. Taking the driving of the droplet moving to the right as an example, the signal configuration is changed to change the high voltage to the pixel adjacent to the right side of the high voltage from the low voltage to the high voltage, and to change the high voltage to the low voltage to the pixel on the left side of the high voltage, so that the high voltage area moves to the right, and the droplet moves to the right along with the high voltage area because the droplet moves along with the high voltage area.
In an exemplary embodiment of the present application, the principle of the stability improvement of scheme four may include:
1. case where leakage of TFT increases: for the conventional 1T1C pixel circuit, after the leakage of the TFT tube increases, the voltage at the Q point of the pixel working point will be attenuated, so that the liquid drop cannot move. The pixel architecture provided by the scheme of the embodiment can improve the influence of leakage on voltage retention, and the principle is as follows:
a. case where the pixel electrode is high voltage: TP4/TP6 is in an on state, because the current of the on state of TP4/TP6 is far larger than the leakage current of TP4/TP6, the increase of the leakage current of TP4/TP6 does not affect the Q point voltage of the pixel.
b. Case where the pixel electrode is at a low voltage: TP4/TP6 was in the OFF state, and TP5/TP7 was in the ON state. Since the current in the on state of TP5/TP7 is much larger than the leakage current of TP4/TP6, the leakage current increase of TP4/TP6 does not affect the Q point voltage of the pixel.
2. Considering the situation of increased droplet leakage current, for the conventional 1T1C pixel circuit, after the droplet leakage current is increased, the voltage at the Q point of the pixel operating point will be attenuated, so that the droplet cannot move. The pixel architecture that this patent put forward can improve the influence of electric leakage to voltage holding, and its principle does:
a. case where the pixel electrode is high voltage: at this time, the tube TP4/TP6 is in an ON state, and the ON current of TP4/TP6 is much larger than the leakage current of the droplet/capacitor, so the increase of the droplet/capacitor leakage does not affect the Q point voltage of the pixel.
b. Case where the pixel electrode is at a low voltage: at this time, the tube TP5/TP7 is in an on state, and since the current of the tube TP5/TP7 in the on state is much larger than the leakage current of the droplet/capacitor, the increase of the leakage current of the droplet/capacitor does not affect the Q point voltage of the pixel.
In the exemplary embodiment of the present application, taking P-type 4T1C Zero-Vgs as an example, when the first control signal provides a certain voltage signal, the certain voltage signal can turn off TP4, and at this time, the sources and drains of TP4 and TP6 will be in a non-conductive state, and TP4 will be in a conductive state. The pixel working electrode of the micro-fluidic chip transfers charges to the first common electrode COM through TP4, and finally the voltage of the pixel working electrode approaches or equals to the voltage of the first common electrode, so that the purpose of writing low voltage into the pixel working electrode is achieved. When the first control signal gives another determined voltage signal, the determined voltage signal can enable TP4 to be switched on, at the time, the sources and the drains of TP4 and TP6 are in an electric communication state, and TP4 is in a closed state. The voltage at the pixel working electrode of the microfluidic chip will be in electrical communication with the second control signal via TP 6. When the second control signal is high voltage, the pixel working electrode of the microfluidic chip is at high voltage; when the second control signal is given to low voltage, the pixel working electrode of the microfluidic chip is in a low voltage state. The voltage on the pixel working electrode of the micro-fluidic chip can be regulated and controlled by matching the first control signal and the second control signal.
In the exemplary embodiment of the present application, taking P-type 4T1C Zero-Vgs as an example, for a microfluidic chip with m rows and n columns, there is a droplet in the area of the pixel region (x, y), (x + i, y + j), and the operation of the microfluidic chip with the pixel circuit is illustrated by taking the droplet moving to the right h as an example. The first control signals capable of enabling the TFTs in the pixels to be turned on are supplied to the x-th row to the x + j-th row, and the first control signals capable of enabling the TFTs in the pixels to be turned off are supplied to the other rows. The y-th and y + h-th columns supply the low voltage second control signal, and the y + j +1 to y + j + h-th columns supply the high voltage second control signal. Thus, the high voltage area will move from (x, y), (x + i, y + j) to (x, y + h), (x + i, y + j + h), and the droplet will move from (x, y), (x + i, y + j) to (x, y + h), (x, y + j + h) because the droplet will move from the low voltage area to the high voltage area, thereby achieving the purpose that the droplet moves to the right for h rows.
And a fifth scheme: (when the voltage regulator circuit includes a plurality of P-type TFTs)
In the exemplary embodiment of the present application, the scheme four is a P-type TFT configuration, and the scheme is an N-type TFT configuration.
In an exemplary embodiment of the present application, the plurality of TFTs may be four TFTs, and may include: a fourth N-type TFT, a fifth N-type TFT, a sixth N-type TFT, and a seventh N-type TFT;
as shown in fig. 15 (N-type 4T-Zero-Vgs type pixel structure diagram):
the gates of the fourth N-type TFT (TP4) and the sixth N-type TFT (TP6) are connected and configured to receive a first control signal;
the drains of the fourth N-type TFT (TP4) and the sixth N-type TFT (TP6) are configured to receive a second control signal;
the source electrode of the fourth N-type TFT (TP4) is connected with the gate electrode of the seventh N-type TFT (TP 7);
a gate electrode of the fifth N-type TFT (TP5) is connected to a source electrode of the fifth N-type TFT (TP5) and to a second common electrode;
the drain electrode of the fifth N-type TFT (TP5) is connected with the source electrode of the fourth N-type TFT (TP4) and is connected with the gate electrode of the seventh N-type TFT (TP 7);
a source electrode of the sixth N-type TFT (TP6) is connected to a drain electrode of the seventh N-type TFT (TP7), and is connected to a first end (Q-end) of the pixel working electrode;
a source electrode of the seventh N-type TFT (TP7) and a second end of the pixel working electrode are connected to a first common electrode (COM);
alternatively, as shown in fig. 16 (N-type 4T-load type pixel structure diagram):
the gates of the fourth N-type TFT (TP4) and the sixth N-type TFT (TP6) are connected and configured to receive a first control signal;
the drains of the fourth N-type TFT (TP4) and the sixth N-type TFT (TP6) are configured to receive a second control signal;
the source electrode of the fourth N-type TFT (TP4) is connected with the gate electrode of the seventh N-type TFT (TP 7);
the gate of the fifth N-type TFT (TP5) is connected to the drain of the fifth N-type TFT (TP5) and to the gate of the seventh N-type TFT (TP 7);
the source electrode of the fifth N-type TFT (TP5) is connected with the second common electrode;
the source electrode of the sixth N-type TFT (TP6) is connected with the drain electrode of the seventh N-type TFT (TP7) and is connected with the first end of the pixel working electrode;
a source electrode of the seventh N-type TFT (TP7) is connected to the second terminal of the pixel working electrode and to a second common electrode (VDD).
In an exemplary embodiment of the present application, as shown in fig. 17 (N-type 4T1C-Zero-Vgs type pixel structure diagram) and fig. 18 (N-type 4T1C-load type pixel structure diagram), the voltage stabilizing circuit may further include: a second capacitance C2;
one substrate of the second capacitor C2 is connected to the gate of the seventh P-type TFT (TP7), the source of the fourth P-type TFT (TP4) and the drain of the fifth P-type TFT (TP5), and the other substrate is configured to receive the first control signal.
In the exemplary embodiment of the present application, the principle of the fifth scheme is substantially the same as that of the fourth scheme, and details are not repeated here.
The embodiment of the present application further provides a microfluidic pixel chip, which may include: a microfluidic pixel circuit as claimed in any one of the above.
It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.
Claims (3)
1. A microfluidic pixel circuit, comprising: a voltage stabilizing circuit;
the voltage stabilizing circuit is connected to two ends of the pixel working electrode and used for providing driving voltage for the pixel working electrode and stabilizing the driving voltage;
the voltage stabilizing circuit is a level inverter circuit; the level inverter circuit comprises a first input end, a second input end and an output end, wherein the first input end is directly connected with a first control signal, the second input end is directly connected with a second control signal, and the output end is directly connected with the pixel working electrode; when the first control signal is at low level and the second control signal is at high level, the output is at high level; when the first control signal is at a high level, the output is at a low level; when the first control signal is at low level, the second control signal is at low level, and the output is at low level; the high voltage is a voltage with a voltage value larger than or equal to a first preset threshold value; the low voltage is a voltage with a voltage value less than or equal to a second preset threshold value; the first preset threshold is greater than or equal to the second preset threshold;
the voltage stabilizing circuit comprises: a plurality of power supply thin film transistors TFT; or, the voltage stabilizing circuit includes: at least one TFT and at least one resistor;
the plurality of TFTs are two TFTs including: a first P-type TFT and a first N-type TFT;
the grid electrodes of the first P-type TFT and the first N-type TFT are set to receive a first control signal;
the source electrode of the first P-type TFT is set to receive a second control signal;
the drain electrode of the first P-type TFT is connected with the first end of the pixel working electrode;
the source electrode of the first N-type TFT is connected with the first end of the pixel working electrode;
the drain electrode of the first N-type TFT and the second end of the pixel working electrode are connected with a first common electrode;
or,
the grid electrodes of the first P-type TFT and the first N-type TFT are set to receive a first control signal;
the drain electrode of the first N-type TFT is connected with a second common electrode;
the source electrode of the first N-type TFT is connected with the first end of the pixel working electrode;
the drain electrode of the first P-type TFT is connected with the first end of the pixel working electrode;
the source electrode of the first P-type TFT is connected with the second end of the pixel working electrode and is configured to receive a second control signal; or
The plurality of TFTs are two TFTs including: a second P-type TFT and a third P-type TFT;
the grid electrode of the second P-type TFT is set to receive a first control signal;
the source electrode of the second P-type TFT is set to receive a second control signal;
the drain electrode of the second P-type TFT is connected with the pixel working electrode;
the grid electrode and the source electrode of the third P-type TFT are connected and are connected with the first end of the pixel working electrode;
the drain electrode of the third P-type TFT and the second end of the pixel working electrode are connected with a first common electrode;
or,
the grid electrode of the second P-type TFT is connected with the drain electrode of the second P-type TFT and is connected with the first end of the pixel working electrode;
the source electrode of the second P-type TFT is connected with a second common electrode;
the grid electrode of the third P-type TFT is set to receive a first control signal;
the source electrode of the third P-type TFT is connected with the drain electrode of the second P-type TFT and the first end of the pixel working electrode;
the drain electrode of the third P-type TFT is connected with the second end of the pixel working electrode and is configured to receive a second control signal; or
The plurality of TFTs are two TFTs including: a second N-type TFT and a third N-type TFT;
the grid electrode of the second N-type TFT is connected with the source electrode of the second N-type TFT and is connected with the first end of the pixel working electrode;
the drain electrode of the second N-type TFT is connected with a second common electrode;
a gate of the third N-type TFT is configured to receive a first control signal;
the drain electrode of the third N-type TFT is connected with the source electrode of the second N-type TFT and the first end of the pixel working electrode;
the source electrode of the third N-type TFT is connected with the second end of the pixel working electrode and is configured to receive a second control signal;
or,
the grid electrode of the second N-type TFT is connected with the drain electrode of the second N-type TFT and is connected with a second common electrode;
the source electrode of the second N-type TFT is connected with the first end of the pixel working electrode;
a gate of the third N-type TFT is configured to receive a first control signal;
the drain electrode of the third N-type TFT is connected with the source electrode of the second N-type TFT and the first end of the pixel working electrode;
the source electrode of the third N-type TFT is connected with the second end of the pixel working electrode and is configured to receive a second control signal; or
The plurality of TFTs are four TFTs including: a fourth P-type TFT, a fifth P-type TFT, a sixth P-type TFT, and a seventh P-type TFT;
the grid electrodes of the fourth P-type TFT and the sixth P-type TFT are connected and are set to receive a first control signal;
the source electrodes of the fourth P-type TFT and the sixth P-type TFT are arranged to receive a second control signal;
the drain electrode of the fourth P-type TFT is connected with the grid electrode of the seventh P-type TFT;
the grid electrode of the fifth P-type TFT is connected with the source electrode of the fifth P-type TFT, and is connected with the drain electrode of the fourth P-type TFT and the grid electrode of the seventh P-type TFT;
the drain electrode of the fifth P-type TFT is connected with the first common electrode;
the drain electrode of the sixth P-type TFT is connected with the source electrode of the seventh P-type TFT and is connected with the first end of the pixel working electrode;
the drain electrode of the seventh P-type TFT is connected with the first common electrode;
or,
the fourth P-type TFT is connected with the grid electrode of the sixth P-type TFT and is set to receive a first control signal;
the source electrodes of the fourth P-type TFT and the sixth P-type TFT are arranged to receive a second control signal;
the drain electrode of the fourth P-type TFT is connected with the grid electrode of the seventh P-type TFT;
the grid electrode of the fifth P-type TFT is connected with the drain electrode of the fifth P-type TFT and is connected with a second common electrode;
the source electrode of the fifth P-type TFT is connected with the drain electrode of the fourth P-type TFT and is connected with the grid electrode of the seventh P-type TFT;
the drain electrode of the sixth P-type TFT is connected with the source electrode of the seventh P-type TFT and is connected with the first end of the pixel working electrode;
the drain electrode of the seventh P-type TFT is connected with the first common electrode; or
The plurality of TFTs are four TFTs including: a fourth N-type TFT, a fifth N-type TFT, a sixth N-type TFT, and a seventh N-type TFT;
the fourth N-type TFT is connected with the grid electrode of the sixth N-type TFT and is set to receive a first control signal;
drains of the fourth N-type TFT and the sixth N-type TFT are configured to receive a second control signal;
the source electrode of the fourth N-type TFT is connected with the grid electrode of the seventh N-type TFT;
the grid electrode of the fifth N-type TFT is connected with the source electrode of the fifth N-type TFT and is connected with a second common electrode;
the drain electrode of the fifth N-type TFT is connected with the source electrode of the fourth N-type TFT and is connected with the grid electrode of the seventh N-type TFT;
the source electrode of the sixth N-type TFT is connected with the drain electrode of the seventh N-type TFT and is connected with the first end of the pixel working electrode;
the source electrode of the seventh N-type TFT and the second end of the pixel working electrode are connected with the first common electrode;
or,
the fourth N-type TFT is connected with the grid electrode of the sixth N-type TFT and is set to receive a first control signal;
drains of the fourth N-type TFT and the sixth N-type TFT are configured to receive a second control signal;
the source electrode of the fourth N-type TFT is connected with the grid electrode of the seventh N-type TFT;
a grid electrode of the fifth N-type TFT is connected with a drain electrode of the fifth N-type TFT and is connected with a grid electrode of the seventh N-type TFT;
the source electrode second common electrode of the fifth N-type TFT is connected;
the source electrode of the sixth N-type TFT is connected with the drain electrode of the seventh N-type TFT and is connected with the first end of the pixel working electrode;
and the source electrode of the seventh N-type TFT is connected with the second end of the pixel working electrode and is connected with the second common electrode.
2. The microfluidic pixel circuit of claim 1, wherein the voltage regulation circuit further comprises: a first capacitor;
one substrate of the first capacitor is connected with the gate electrode of the seventh P-type TFT, the drain electrode of the fourth P-type TFT, and the source electrode of the fifth P-type TFT, and the other substrate is configured to receive the first control signal.
3. A microfluidic pixel chip, comprising: a microfluidic pixel circuit according to any one of claims 1-2.
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| CN113674707B (en) * | 2021-08-31 | 2023-03-24 | 上海天马微电子有限公司 | Driving circuit, driving method and microfluidic substrate |
| CN114677977B (en) * | 2022-03-10 | 2024-04-09 | 广东奥素液芯微纳科技有限公司 | Micro-fluidic pixel circuit and chip based on phase inverter |
| CN114582293B (en) * | 2022-03-10 | 2023-08-04 | 广东奥素液芯微纳科技有限公司 | Microfluidic active matrix driving circuit and microfluidic device |
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| CN110060631B (en) * | 2018-06-27 | 2021-09-03 | 友达光电股份有限公司 | Pixel circuit |
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