CN111430324B - Semiconductor structure and forming method thereof, semiconductor device and chip - Google Patents
Semiconductor structure and forming method thereof, semiconductor device and chip Download PDFInfo
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- CN111430324B CN111430324B CN202010276330.9A CN202010276330A CN111430324B CN 111430324 B CN111430324 B CN 111430324B CN 202010276330 A CN202010276330 A CN 202010276330A CN 111430324 B CN111430324 B CN 111430324B
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 230000002093 peripheral effect Effects 0.000 claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 claims abstract description 15
- 239000010410 layer Substances 0.000 claims description 143
- 229910052751 metal Inorganic materials 0.000 claims description 82
- 239000002184 metal Substances 0.000 claims description 66
- 239000011229 interlayer Substances 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 3
- 230000006353 environmental stress Effects 0.000 abstract description 7
- 230000035882 stress Effects 0.000 abstract description 7
- 238000005336 cracking Methods 0.000 abstract description 5
- 239000010949 copper Substances 0.000 description 10
- 239000000758 substrate Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 239000004020 conductor Substances 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 238000005530 etching Methods 0.000 description 5
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- 238000000151 deposition Methods 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
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- 239000010408 film Substances 0.000 description 3
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/564—Details not otherwise provided for, e.g. protection against moisture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1011—Structure
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The semiconductor structure comprises a bonding pad and a vertical dam structure arranged beside the bonding pad; a semiconductor device comprising the semiconductor structure of one or more embodiments of the present disclosure; a chip comprising the semiconductor device of one or more embodiments of the present disclosure; a method for forming a semiconductor structure, comprising the steps of: providing a virtual active area; and forming a vertical dam structure arranged around the bonding pad in at least one of a bit line forming process, a peripheral contact manufacturing process and a bonding pad manufacturing process performed above the dummy active region. Compared with the prior art, the vertical dam structure is innovatively arranged beside the bonding pad, so that the electrical stress and the environmental stress of the bonding pad are reduced, the moisture is prevented from permeating into the bonding pad, the possibility of film cracking is reduced, and the reliability of a semiconductor device are improved.
Description
Technical Field
The present disclosure relates to the field of semiconductor device technologies, and more particularly, to a semiconductor structure, a method for forming the same, a semiconductor device, and a chip.
Background
A PAD (PAD) region of a semiconductor Chip (Chip) is subjected to Electrical Stress (Electrical Stress) and Environmental Stress (Environmental Stress) in a subsequent Wire bonding (Wire bonding) operation, and a PAD (PAD) portion is sensitive to Environmental factors such as electricity and water, for example, problems such as film cracking (Chip) or water permeation may occur when a semiconductor Chip product is continuously used, and normal use of a main Chip (main Chip) may be affected.
Disclosure of Invention
In order to solve the problems that a bonding pad area of an existing semiconductor chip is easily affected by electrical stress and environmental stress, is sensitive to environmental factors and the like, the disclosure innovatively provides a semiconductor Structure, a forming method thereof, a semiconductor device and a chip, a Vertical DAM Structure (DAM Vertical Structure) is uniquely arranged around a bonding pad, the environmental stress and the electrical stress can be released through the Vertical DAM Structure, moisture can be prevented from entering the bonding pad area, the possibility of membrane cracking is remarkably reduced, and therefore various problems existing in the bonding pad area of the existing semiconductor chip are thoroughly solved.
According to one or more embodiments of the present disclosure, a semiconductor Structure includes a PAD (PAD), and a Vertical DAM Structure (DAM Vertical Structure) disposed beside the PAD.
According to one or more embodiments of the present disclosure, a semiconductor device includes the semiconductor structure of one or more embodiments of the present disclosure.
According to one or more embodiments of the present disclosure, a chip includes the semiconductor device of one or more embodiments of the present disclosure.
According to one or more embodiments of the present disclosure, a method of forming a semiconductor structure includes the steps of: providing a virtual active area; and forming a vertical dam structure arranged around the bonding pad in at least one of a bit line forming process, a peripheral contact manufacturing process and a bonding pad manufacturing process performed above the virtual active region.
The beneficial effect of this disclosure does: compared with the prior art, the vertical dam structure is innovatively arranged beside the bonding pad, so that the electrical stress and the environmental stress of the bonding pad are reduced, the moisture is prevented from permeating into the bonding pad, the possibility of film cracking is reduced, and the reliability of a semiconductor device are improved.
The method and the device can effectively protect the pad area of the chip and ensure that the chip avoids the failure caused by the pad problem.
Drawings
Fig. 1 is a schematic longitudinal sectional structure of a dummy active region.
Fig. 2 is a schematic diagram showing a vertical cross-sectional structure of a dummy active region, a dummy bit line contact, and a dummy bit line.
Fig. 3 is a schematic longitudinal sectional view of a dummy active region, a dummy bit line contact, a dummy bit line, and a dummy peripheral contact.
Fig. 4 is a schematic longitudinal cross-sectional view of a dummy active region, a dummy bit line contact, a dummy bit line, a dummy peripheral contact, and a first dummy metal layer.
Fig. 5 is a schematic longitudinal cross-sectional view of a dummy active region, a dummy bit line contact, a dummy bit line, a dummy peripheral contact, a first dummy metal layer, a first dummy via layer, and a second dummy metal layer.
Fig. 6 is a schematic longitudinal cross-sectional view of a dummy active region, a dummy bit line contact, a dummy bit line, a dummy peripheral contact, a first dummy metal layer, a first dummy via layer, a second dummy metal layer, and a second dummy via layer.
Fig. 7 is a schematic longitudinal sectional view of the vertical dam structure.
Fig. 8 is a schematic diagram illustrating a positional relationship between the third dummy metal layer and the pad.
Fig. 9 is a flow chart illustrating a method of forming a vertical dam structure.
In the figure, the position of the upper end of the main shaft,
100. a virtual active region;
200. a dummy bit line contact;
300. a dummy bit line;
400. a virtual peripheral contact;
500. a first dummy metal layer;
501. a second dummy metal layer;
600. a first virtual via layer;
601. a second virtual via layer;
700. a third dummy metal layer;
800. an insulating region;
900. and a bonding pad.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
The semiconductor device has a multilayer interconnection structure, wherein, the conductor layer is formed by depositing an insulating layer on a substrate, etching a contact window opening on the insulating layer, and then depositing a conductor material in the contact slot opening, the conductor layer is applied on the insulating layer and is patterned, and the conductor interconnection is formed between the contact points of the device, thereby forming the first layer of the basic integrated circuit, the interconnection is further carried out by utilizing an additional conductor layer, the additional conductor layer is positioned on the additional insulating layer with a conductive through hole, and the interconnection can be carried out by utilizing a plurality of layers of conductors as the complexity of the integrated circuit increases; at the top layer, the wires terminate at PADs (PADs), such as metal PADs, to which the external wires of the chip are bonded.
PAD (PAD)900 may be formed on an interlevel dielectric layer, and may be made of, but not limited to, tungsten, aluminum, copper, or combinations thereof. The interlayer dielectric layer is disposed on a semiconductor substrate, which may be, for example, a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, a silicon germanium substrate, a III-V compound semiconductor substrate, or an epitaxial thin film substrate obtained by performing Selective Epitaxial Growth (SEG), on which an interlayer Insulating Layer (ILD) may be disposed.
As shown in fig. 7, the vertical dam structure extends in the vertical direction, is disposed beside the pad, and surrounds the pad to protect the pad area, and the vertical dam structure includes: a virtual peripheral contact 400.
The dummy peripheral contact 400 may be made of tungsten (W) to achieve effective support and pressure resistance, and may have a cylindrical cross section, for example, a ring-shaped cross section (ringtype), and surround the outer side of the pad, i.e., be disposed at the periphery of the pad.
As shown in fig. 2, the vertical dam structure further includes: a dummy bit line 300 and a dummy bit line contact 200.
The dummy bit line 300 is disposed under the dummy peripheral contact 400 and connected to the dummy peripheral contact 400.
The dummy bit line contact 200 is disposed below the dummy bit line 300 and above the dummy active region 100, the dummy bit line contact 200 is connected to the dummy bit line 300, and an isolation metal layer may be directly disposed between the dummy bit line contact 200 and the dummy active region 100.
As shown in fig. 4 and 5, the vertical dam structure further includes: a first dummy metal layer 500, a first dummy via layer 600, and a second dummy metal layer 501; a first dummy metal layer 500 disposed above the dummy peripheral contact 400 and connected to the dummy peripheral contact 400; the first dummy metal layer 500 and the second dummy metal layer 501 may form a metal interconnection structure, the second dummy metal layer 501 is connected to the first dummy metal layer 500 through the first dummy via layer 600, and may be formed by a conventional copper damascene method, for example, a single damascene (single damascene) or dual damascene (dual damascene) method, and the second dummy metal layer 501 is disposed above the first dummy metal layer 500 and the first dummy via layer 600.
As shown in fig. 6 and 7, the vertical dam structure further includes: a third dummy metal layer 700 and a second dummy via layer 601; the third dummy metal layer 700 is connected to the second dummy metal layer 501 through the second dummy via layer 601, and is disposed above the second dummy metal layer 501 and the second via layer. In some embodiments of the present disclosure, the dummy peripheral contact 400, the first dummy metal layer 500, the first dummy via layer 600, the second dummy metal layer 501, and the second dummy via layer 601 are all disposed in the insulating region 800, the insulating region 800 may be formed by stacking a plurality of interlayer insulating layers, the insulating layers may include, but are not limited to, one or more of silicon oxide, silicon nitride, silicon oxynitride, and the like, and the third dummy metal layer 700 is disposed above the insulating region 800.
The present disclosure also provides a semiconductor device including the semiconductor structure of one or more embodiments of the present disclosure, which may be, for example, a semiconductor memory device. The present disclosure may also provide a chip including the semiconductor device of one or more embodiments of the present disclosure. The chip of one or more embodiments of the present disclosure may be, for example, a Dynamic Random Access Memory (DRAM) chip, including: similar to the DAM (DAM) shaped vertical structure at the outermost periphery of the chip. The chip may be connected to the package substrate by a connection member, which may be a metal pillar, a bump, a solder, a bump including a solder ball, or a wire formed by a wire bonding device, and may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), or gold (Au).
One or more embodiments of the present disclosure may provide a method for forming a semiconductor structure, which is different from the prior art in that a method for forming a Vertical DAM structure is provided, so that a Vertical (Vertical) structure in a DAM (DAM) form may be easily formed without a complicated process, thereby preventing a problem of poor reliability of a PAD (PAD) caused by a current or an environmental pressure, and the like, reducing an electrical stress and an environmental stress applied to the PAD, preventing moisture from penetrating into the PAD, reducing a possibility of film cracking, and further improving reliability of a semiconductor device.
The method can add integrated circuit layout (layout) wiring at a bonding pad position, and synchronously complete the manufacturing process of the vertical dam structure provided by the method in the process of other processes, and the conventional processing steps of a semiconductor device can be selected according to actual conditions, but the improved forming method provided by the method can comprise the following steps of providing a virtual active area 100, and forming the vertical dam structure arranged around a bonding pad 900 in at least one of a bit line forming process, a peripheral contact manufacturing process and a bonding pad 900 manufacturing process which are carried out above the virtual active area 100, wherein in the bonding pad 900 manufacturing process, a first virtual metal layer 500, a first virtual through hole layer 600 and a second virtual metal layer 501 of the vertical dam structure can be manufactured by adopting an embedding process; specifically, the forming method may include the following steps.
Referring to fig. 1, fig. 1 is a schematic diagram illustrating a vertical cross-sectional structure of a dummy active region 100; in the process of fabricating an Active area (Active) region of a semiconductor device, an Active area of a Dummy (Dummy) form, i.e., the Dummy Active area 100 of the present disclosure, is fabricated at a PAD 900(PAD) location. Specifically, in one or more embodiments of the present disclosure, the dummy active regions 100 may be distributed, for example, at the periphery of the PAD 900 (PAD).
Referring to fig. 2, fig. 2 is a schematic diagram illustrating a vertical cross-sectional structure of a dummy active region 100, a dummy bit line contact and a dummy bit line; a dummy Bit line contact (DC contact)200 and a dummy Bit line (Bit-line)300 may be formed in the dummy active region 100 region around the pad 900 during the active region Bit line forming process, the dummy Bit line 300 being connected to the dummy Bit line contact 200, and in some embodiments of the present disclosure, the dummy Bit line contact 200 is disposed below the dummy Bit line 300 and above the dummy active region 100.
Referring to fig. 3, fig. 3 is a schematic diagram illustrating a vertical cross-sectional structure of the dummy active region 100, the dummy bit line contact, the dummy bit line and the dummy peripheral contact 400; after Chemical Mechanical Planarization (CMP) is performed in an Inter Level Dielectric (ILD) process, when a peripheral contact (MC contact) manufacturing process is performed, a dummy peripheral contact 400 is disposed above a dummy bit line 300, the dummy peripheral contact 400 is connected to the dummy bit line 300, and the dummy peripheral contact 400 in some embodiments of the present disclosure has a cylindrical cross section and is disposed on the periphery of the pad 900; the dummy peripheral contact 400 may be made of metal such as tungsten, and the dummy peripheral contact 400 may be formed in the insulating region 800.
Referring to fig. 4, fig. 4 is a schematic longitudinal cross-sectional view of a dummy active region 100, a dummy bit line contact, a dummy bit line, a dummy peripheral contact 400, and a first dummy metal layer 500; a first dummy metal layer 500(M1) is formed on the periphery of the pad 900 by etching, deposition, etc. and is disposed above the dummy peripheral contact 400 and connected to the dummy peripheral contact 400, and the material of the first dummy metal layer 500 may be, for example, copper or nickel.
Referring to fig. 5, fig. 5 is a schematic diagram showing a vertical cross-sectional structure of the dummy active region 100, the dummy bit line contact, the dummy bit line, the dummy peripheral contact 400, the first dummy metal layer 500, the first dummy via layer 600, and the second dummy metal layer 501; in one or more embodiments of the present disclosure, a damascene process is adopted to fabricate the first Dummy Metal layer 500, and a first Dummy VIA layer 600(VIA1) and a second Dummy Metal layer 501(M2) are formed above the first Dummy Metal layer 500 by Metal etching (Metal Etch), deposition, and the like, and when the first Dummy Metal layer 500, the first Dummy VIA layer 600, and the second Dummy Metal layer 501 are made of copper, a Dummy Pattern (Dummy Pattern) may be formed by a Cu Chemical Mechanical Planarization (Cu CMP) manner of a copper layer, that is, the first Dummy Metal layer 500, the first Dummy VIA layer 600, and the second Dummy Metal layer 501; the second dummy metal layer 501 is connected to the first dummy metal layer 500 through the first dummy via layer 600, and is disposed above the first dummy metal layer 500 and the first dummy via layer 600. In one or more embodiments of the present disclosure, the first dummy via layer 600 is filled with copper metal.
Referring to fig. 6, fig. 6 is a schematic diagram illustrating a vertical cross-sectional structure of the dummy active region 100, the dummy bit line contact, the dummy bit line, the dummy peripheral contact 400, the first dummy metal layer 500, the first dummy via layer 600, the second dummy metal layer 501, and the second dummy via layer 601. A second Dummy VIA layer 601 is formed on the periphery of the pad 900 (VIA2), the second Dummy VIA layer 601 is disposed above the second Dummy metal layer 501 and connected to the second Dummy metal layer 501, in one or more embodiments of the present disclosure, the second Dummy VIA layer 601 is filled with tungsten metal to form a Dummy Pattern (Dummy Pattern).
Referring to fig. 7, fig. 7 is a schematic longitudinal sectional view of the vertical dam structure. Finally, a third Dummy metal layer 700 is manufactured, in one or more embodiments of the present disclosure, a Dummy Pattern (Dummy Pattern) of the third Dummy metal layer 700 may be manufactured on the periphery of the pad 900 by etching with aluminum metal, etc., the third Dummy metal layer 700 may be made of aluminum, and the third Dummy metal layer 700 is connected to the second Dummy metal layer 501 through the second Dummy via layer 601 and is disposed above the second Dummy metal layer 501 and above the second via layer; in some embodiments of the present disclosure, the dummy peripheral contact 400, the first dummy metal layer 500, the first dummy via layer 600, the second dummy metal layer 501, and the second dummy via layer 601 are all disposed in the insulating region 800, the third dummy metal layer 700 is disposed above the insulating region 800, and the pad 900 may be surrounded by the third dummy metal layer 700, please refer to fig. 8, where fig. 8 is a schematic diagram illustrating a position relationship between the third dummy metal layer 700 and the pad 900.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.
Claims (5)
1. A semiconductor structure, comprising:
a pad;
the vertical dam structure is arranged beside the bonding pad;
vertical dam structure extends along the vertical direction, includes: the cross section of the virtual peripheral contact piece is cylindrical and is arranged on the periphery of the bonding pad;
vertical dam structure still includes: a dummy bit line and a dummy bit line contact; the dummy bit line is arranged below the dummy peripheral contact piece and is connected with the dummy peripheral contact piece; the dummy bit line contact part is arranged below the dummy bit line and above the dummy active region and is connected with the dummy bit line;
vertical dam structure still includes: the first dummy metal layer, the first dummy via layer and the second dummy metal layer; the first virtual metal layer is arranged above the virtual peripheral contact element and is connected with the virtual peripheral contact element; the second virtual metal layer is connected with the first virtual metal layer through the first virtual via layer and is arranged above the first virtual metal layer and the first virtual via layer;
vertical dam structure still includes: a third virtual metal layer and a second virtual via layer; the third virtual metal layer is connected with the second virtual metal layer through the second virtual via layer and is arranged above the second virtual metal layer and the second virtual via layer.
2. The semiconductor structure of claim 1,
the virtual peripheral contact, the first virtual metal layer, the first virtual via layer, the second virtual metal layer, and the second virtual via layer are all disposed in an insulating region, and the third virtual metal layer is disposed above the insulating region.
3. A semiconductor device comprising the semiconductor structure of any one of claims 1 to 2.
4. A chip comprising the semiconductor device of claim 3.
5. A method of forming a semiconductor structure, comprising:
providing a virtual active area;
forming a vertical dam structure arranged around a bonding pad in at least one of a bit line forming process, a peripheral contact manufacturing process and a bonding pad manufacturing process performed above the dummy active region;
when a peripheral contact manufacturing process is carried out, a virtual peripheral contact is arranged; after chemical mechanical planarization is carried out in an interlayer dielectric process and when a peripheral contact manufacturing process is carried out, a virtual peripheral contact is arranged above a virtual bit line and is connected with the virtual bit line; the vertical dam structure includes a virtual peripheral contact;
forming a dummy bit line contact part and a dummy bit line in a dummy active region at the periphery of the pad, the dummy bit line being connected to the dummy bit line contact part; the vertical dam structure further comprises a dummy bit line and a dummy bit line contact part;
in the manufacturing process of the bonding pad, a first virtual metal layer, a first virtual through hole layer and a second virtual metal layer of the vertical dam structure are manufactured by adopting an embedding process; the vertical dam structure further comprises a third virtual metal layer and a second virtual through hole layer.
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| JP2004153015A (en) * | 2002-10-30 | 2004-05-27 | Fujitsu Ltd | Semiconductor device and its manufacturing method |
| JP4659355B2 (en) * | 2003-12-11 | 2011-03-30 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method thereof |
| US8410571B2 (en) * | 2006-07-12 | 2013-04-02 | United Microelectronics Corp. | Layout of dummy patterns |
| CN108428670B (en) * | 2017-02-14 | 2020-06-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and electronic device |
| CN109285822B (en) * | 2017-07-21 | 2021-02-26 | 中芯国际集成电路制造(北京)有限公司 | Bonding pad, semiconductor device, manufacturing method of semiconductor device and electronic device |
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