CN111327334A

CN111327334A - Narrow-band DDC time division multiplexing method based on FPGA

Info

Publication number: CN111327334A
Application number: CN201811542183.4A
Authority: CN
Inventors: 李鑫儒; 曹晓冬; 李羚梅; 范玉进
Original assignee: Tianjin Optical Electrical Communication Technology Co Ltd
Current assignee: Tianjin Optical Electrical Communication Technology Co Ltd
Priority date: 2018-12-17
Filing date: 2018-12-17
Publication date: 2020-06-23

Abstract

The invention provides a narrow-band DDC time division multiplexing method based on FPGA, which comprises the following steps: 1. sampling the acquired analog signals; 2. carrying out down-conversion on the collected analog signals; 3. carrying out secondary sampling on the acquired analog signal; 4. carrying out narrow-band filtering processing on the signal subjected to secondary sampling through a low-pass filter; 5. and framing the processed data. The method can be applied to a radio signal detection system, can also be applied to the field of radio communication by combining other basic radio processing technologies, and has good application prospect.

Description

Narrow-band DDC time division multiplexing method based on FPGA

Technical Field

The invention relates to the field of communication, in particular to a narrow-band DDC time division multiplexing method based on an FPGA.

Background

At present, the short wave and ultrashort wave channelized processing technology is a very promising receiving system in the radio baseband processing technology in the communication field. Due to the characteristics of multiple channels and multiple sub-bands of the receiving system and supporting high data transmission bandwidth, the resource utilization rate can become a great bottleneck, so that a time division multiplexing technology with high resource multiplexing is needed to share resource consumption, and parallel operation among sub-band channels is realized. Therefore, it is an urgent problem to be solved to develop a narrow-band DDC time division multiplexing method based on an FPGA.

Disclosure of Invention

The invention aims to solve the technical problems and provides a narrow-band DDC time division multiplexing method based on an FPGA (field programmable gate array), so that parallel operation can be realized among sub-band channels, and the characteristic of efficient resource multiplexing is fully embodied.

In order to solve the technical problems, the invention adopts the technical scheme that:

a narrow-band DDC time division multiplexing method based on FPGA comprises the following steps:

1. sampling the acquired analog signals;

2. carrying out down-conversion on the collected analog signals;

3. carrying out secondary sampling on the acquired analog signal;

4. carrying out narrow-band filtering processing on the signal subjected to secondary sampling through a low-pass filter;

5. and framing the processed data.

Further, in the first step, the AD directly samples the acquired intermediate frequency analog signal, the sampling rate is 200MHz, and the signal bit width is 16 bits.

Further, in the second step, a carrier mixing mode is used for down-conversion, and a multiplier is adopted to mix with the carrier generated by the DDS core, so that the delay in the processing process is reduced.

Further, in step three, the subsampling is implemented by using a cascade of a CIC filter and an FIR filter. The method specifically comprises the following steps: the first stage filter selects CIC decimation filtering, and the decimation multiple is set to be 40. The second-stage filter selects FIR extraction filtering, the second-stage extraction multiple is 5, the working frequency is 5MHz, the passband cut-off frequency is 400KHz, the stopband cut-off point is 600KHz, the in-band flatness is 1dB, and the group band attenuation is 80 dB.

Further, in step five, after the data processing is completed, framing is performed on the data according to the number of processing paths, the maximum interface rate is calculated, and a proper transmission mode is selected to transmit out the framed data.

The invention has the advantages and positive effects that: the channelized data processing has a wide instantaneous frequency coverage bandwidth to accommodate processing of highly dense signals. Based on the resource reuse correlation theory, the programmable logic device is adopted to complete the engineering realization, and the resource consumption is reduced. The technology can be applied to a radio signal detection system, can also be applied to the field of radio communication by combining other basic radio processing technologies, and has good application prospect.

Drawings

FIG. 1 is a flow chart of the present method;

FIG. 2 is a graph of the FIR decimation filter amplitude frequency response;

fig. 3 is an overall link resource consumption graph.

Detailed Description

The following detailed description of specific embodiments of the invention refers to the accompanying drawings.

The radio baseband processing technology mainly comprises four parts: the first part is to carry out corresponding waveform preprocessing on the acquired analog signals, and mainly carries out relevant operations such as filtering and shaping on the signals; the second part is to adjust the signal frequency, namely, the broadband DDC processing and the signal preprocessing; the third part is to perform rate adjustment on the signal, namely, the secondary sampling comprises anti-aliasing filtering and decimation; the fourth part is to filter the narrow band signal, identify the same signal, group frame and control the data flow arrangement, which aims to filter the narrow band signal and complete the transmission of the platform processing data.

As shown in fig. 1, a narrow-band DDC time division multiplexing method based on FPGA includes the following steps:

firstly, sampling the collected analog signal

The intermediate frequency signal is directly sampled by AD, the sampling rate is 200MHz, the signal bit width is 16 bits

Secondly, down-conversion is carried out on the collected analog signals

The first process after sampling is down conversion, which aims to shift the corresponding frequency points in the broadband signal to the baseband and generate I, Q two paths of baseband signals. The frequency conversion link adopts a carrier frequency mixing mode, and the direct multiplier mixes frequency with the carrier generated by the DDS core, so that the delay in the processing process is reduced.

Thirdly, performing secondary sampling on the acquired analog signal

Because the sampling rate is 200MHz, the final narrow-band bandwidth is 800kHz, the order of a filter for direct filtering is too high to design, secondary sampling is needed, and the rate is reduced to a designable range by extracting 200 times. Additionally, designing a 800kHz narrowband signal over a wider frequency band requires a large amount of multiplexing to ensure resource allocation.

The extraction filter of the secondary sampling link comprises a CIC filter, an HB filter and a most basic FIR filter, the CIC can extract any multiple, but the performance of flatness in a band is poor, the flatness of the HB in the band is superior to that of the CIC filter, but only the nth power of 2 can be extracted, the 2 filters are superior to the FIR in the resource utilization rate, but the performances of out-of-band suppression and over-band steepness are inferior to that of the FIR. Since the decimation multiple is 5 and the requirements on out-of-band suppression and over-band steepness are high, the link uses CIC and FIR cascade to realize secondary sampling.

The first stage of decimation will face three options: 1) and directly performing 2-time decimation without filtering. Because the sampling rate is 200MHz, the maximum frequency point of the frequency-converted signal is 126MHz, the direct extraction can not cause the aliasing of the effective signal. 2) Using the CIC filter directly, a decimation of 5 times by 2n times is performed. 3) The decimation is performed by a FIR filter directly to the power of 2. And selecting 5-order cascade CIC, setting the delay as 1, starting to reduce the passband characteristic and the stop band attenuation characteristic when the extraction multiple reaches 80, and sharply reducing the passband characteristic and the stop band characteristic when the extraction multiple reaches 80, so that the equipment requirements cannot be met, therefore, the first-stage filter selects CIC for extraction and filtering, and the extraction multiple is set as 40.

The second-stage extraction multiple is 5, the working frequency is 5MHz, the passband cut-off frequency is 400KHz, the stopband cut-off point is 600KHz, the in-band flatness is 1dB, the group band attenuation is 80dB, and the amplitude-frequency response is shown in figure 2.

The whole secondary sampling link uses a lot of logic resources and DSP resources, time division multiplexing must be used, and the design and implementation of multiplexing are mainly discussed below.

Fourthly, narrow-band filtering processing is carried out on the signals after the secondary sampling through a low-pass filter

The purpose of narrow-band filtering is to extract 800kHz signals, sample rate bit 1MHz after secondary sampling, optimize flatness in band and attenuation out of band as much as possible at the same time, and pass FIR.

Fifthly, framing the processed data

After the data processing is finished, framing is carried out on the data according to the processing path number, the maximum interface rate is calculated, and a proper transmission mode is selected to transmit out the framed data.

The following description is given in conjunction with specific embodiments.

1) sampling

Sampling needs to select an AD conversion chip with a sampling rate of more than 200MSPS and a bit width of 16 bits, and the SFDR and SNR performances of the chip also need to be considered.

2) Down conversion

The DDS mixing mode is selected, and the resources consumed by single-path processing are shown in the table 1:

TABLE 1 Down-conversion resource usage

3) Sub-sampling

The multiplexing mode can reduce resource consumption and effectively process a multi-channel multi-narrow-band information system. The multiplexing mode may be used when the system clock has a large multiple of the processing clock, which amounts to time shifting resources. The data rate is 5MHz, 32-path and 40-path multiplexing can be realized under a sampling clock of 200MHz, and the decimation filtering is shown in Table 2:

TABLE 2FIR decimation filter multiplexing resource usage

Decimating FIR	Reg	LUTs	RAM	DSP
					Multiplexing
32 channels	286	245	0	6
					Multiplexing 40 channels	294	435	0	6

After decimation filtering, the data rate is 1MHz, and under a sampling clock of 200MHz, the low-pass filter can realize multiplexing of 32 paths, 40 paths, 50 paths and 64 paths, and the resource consumption is as follows:

4) low pass filtering

TABLE 3 Low pass Filter multiplexing resource usage

Low pass FIR	Reg	LUTs	RAM	DSP
					Multiplexing
32 channels	394	302	3	6
					Multiplexing 40 channels	450	535	3	7
Multiplex 50 channels	563	685	4	9
					Multiplexing 64 channels	697	1269	6	12

As the number of multiplexing paths increases, the logic resources and DSP increase rapidly, especially from 50 to 64 paths, with 685 rising to 1269 for logic resources and 9 rising to 12 for DSP resources. 50-path multiplexing is selected by balancing the number of actual channels and sub-bands.

5) Framing

After the data processing is finished, framing is carried out according to the processing path number, the interface rate is 16b (bit width) 200 (path number) 1M/s (sub-band rate) 3.2Gb/s, and a proper transmission mode is selected to transmit the framed data.

The system clock is twice of the sampling clock, the multiplier and the CIC of the down-conversion module can be multiplexed for two paths, so that the resources can be saved, and finally the resource occupancy rate of the whole link on a V7690t chip of XILINX company is shown in figure 3 through the high multiplexing of the resources.

The narrow-band DDC time division multiplexing method based on the FPGA adopts a programmable logic device to complete engineering realization. Has the following characteristics:

1) the resource utilization rate of the filter is improved;

2) the resource consumption is reduced, and real-time processing can be better realized;

3) parallel operation can be realized among all sub-band channels, and the characteristic of efficient resource multiplexing is fully embodied.

The embodiments of the present invention have been described in detail, but the description is only for the preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. All equivalent changes and modifications made within the scope of the present invention should be covered by the present patent.

Claims

1. A narrow-band DDC time division multiplexing method based on FPGA is characterized in that the process is as follows:

1) sampling the acquired analog signals;

2) carrying out down-conversion on the collected analog signals;

3) carrying out secondary sampling on the acquired analog signal;

4) carrying out narrow-band filtering processing on the signal subjected to secondary sampling through a low-pass filter;

5) and framing the processed data.

2. The narrow-band DDC time division multiplexing method based on FPGA of claim 1, characterized in that: in the first step, the AD directly samples the collected intermediate frequency analog signals, the sampling rate is 200MHz, and the signal bit width is 16 bits.

3. The narrow-band DDC time-division multiplexing method based on FPGA of claim 1 or 2, characterized in that: in the second step, a carrier mixing mode is used for down-conversion, and a multiplier is adopted for mixing with the carrier generated by the DDS core.

4. The narrow-band DDC time division multiplexing method based on FPGA of claim 3, characterized in that: in step three, the secondary sampling is realized by using a CIC filter and an FIR filter in cascade.

5. The narrow-band DDC time division multiplexing method based on FPGA of claim 4, characterized in that: the method specifically comprises the following steps: the first stage filter selects CIC decimation filtering, and the decimation multiple is set to be 40. The second-stage filter selects FIR extraction filtering, the second-stage extraction multiple is 5, the working frequency is 5MHz, the passband cut-off frequency is 400KHz, the stopband cut-off point is 600KHz, the in-band flatness is 1dB, and the group band attenuation is 80 dB.

6. The narrow-band DDC time division multiplexing method based on FPGA of claim 4, characterized in that: in the fifth step, after the data processing is finished, framing is carried out according to the processing path number, the maximum interface speed is calculated, and a proper transmission mode is selected to transmit out the framed data.