CN111327312B

CN111327312B - Edge type high-resistance digital phase discriminator suitable for time-lag VCO group ring

Info

Publication number: CN111327312B
Application number: CN201811528020.0A
Authority: CN
Inventors: 张伟林
Original assignee: Individual
Current assignee: Individual
Priority date: 2018-12-14
Filing date: 2018-12-14
Publication date: 2024-04-19
Anticipated expiration: 2038-12-14
Also published as: CN111327312A

Abstract

Based on the specification in the design scheme of the structural principle scheme of the standardized design high-resistance digital phase discriminator, namely the content shown in fig. 1, the novel design of the edge type high-resistance digital phase discriminator is realized, and all definitions of the existing edge type high-resistance digital phase discriminator are covered.

Description

Edge type high-resistance digital phase discriminator suitable for time-lag VCO group ring

Technical Field

The invention relates to a brand new design method of an edge type high-resistance digital phase detector (hereinafter referred to as edge type phase detector for short), the design mode adopts a design method specified in a structural principle scheme of a standardized design high-resistance digital phase detector with a patent application number 2015106449019, and an interface circuit matched with the invention can adopt an interface circuit specified in a standard interface circuit of an output stage of the high-resistance digital phase detector with a patent application number 2015106448849 and a standard interface circuit of a non-FET switch class of an output stage of the high-resistance phase detector with a patent application number 2017104018440. The circuit form related by the invention is not only suitable for a digital phase detector built by a general digital or analog IC chip, but also suitable for an edge type phase detector circuit designed by an integrated circuit.

Background

In a phase locked loop of an electronic VCO bank loop, the VCO control characteristics have immediate characteristics that do not affect the phase locked loop operating characteristics, i.e., there is typically no delay problem. However, for a type of VCO, for example, consisting of a motor, the VCO control characteristics have significant delay characteristics and are often accompanied by the need for high current drive. The invention relates to an edge type phase detector (hereinafter referred to as the detector) based on a brand new state transition diagram on the basis of an edge type high-resistance digital phase detector (hereinafter referred to as the front detector) with brand new design and patent application number 2015106462973, and aims to increase the retention time when the output of the phase detector is in a power supply potential state.

The specific working principle is as follows: for the state transition diagram shown in fig. 1, if only one of the two input signals has a positive edge in the state transition diagram, the output state of the phase detector returns to the high-resistance state of the initial state; in the state transition diagram shown in fig. 2, only the phase detector in the "GND" state keeps the characteristic that one of the two original input signals has the positive edge and the output state of the phase detector returns to the initial high-resistance state, while the phase detector in the power supply potential state has the positive edge and the output state of the phase detector returns to the initial high-resistance state. Thus, the phase detector increases the chance of leaving the power supply potential output state.

Disclosure of Invention

Based on the present invention under the state transition diagram shown in fig. 2, a specific circuit block diagram is shown in fig. 3, and one specific circuit achieved based on the design method specified in the "structural principle scheme of standardized design high-resistance digital phase discriminator" with patent application number 2015106449019 is shown in fig. 4, and the above diagrams are shown in the above figures.

Drawings

Fig. 1 is a state transition diagram of a phase detector, namely a "completely new design edge type high-resistance digital phase detector", with patent application number 2015106462973.

Fig. 2 is a state transition diagram of the edge type high-resistance digital phase detector of the present invention.

Fig. 3 is a circuit block diagram of an edge type phase detector of the present invention.

Fig. 4 is a circuit diagram of a block diagram implementation according to fig. 3.

The device maintains the working characteristics of the front end (different from the prior 4046 series edge type high-resistance digital phase discriminator)

For the treatment method of the high resistance state returning to or departing from the initial state:

a. In the working period of phase-locked loop starting and two phase discriminator input signals with larger phase difference

The phase discriminator in the 'GND' state returns to the high-resistance state, and the time taken for one of the phase discriminator to start reset is three gate working times.

The time taken by the phase discriminator in the power supply potential state to return to the high-resistance state and start reset is three gate working times.

B. In the working period of phase-locked loop with smaller phase difference between the input signals of two phase detectors

The time taken for the phase detector in any state to return to the high-resistance state is the working time of two gates.

C. The circuit pattern for ensuring the effective reset of the flip-flop is identical.

D. To ensure that the phase detector is out of the high resistance state the same circuit form.

The device has different working characteristics from the front device (different from the prior 4046 series edge type high-resistance digital phase detector)

Firstly, in the processing method of the high-resistance state returning to the initial state, when the phase-locked loop is started and the two phase detectors input signals have a working period with a larger phase difference, the time taken for returning to the high-resistance state by the phase detector in the 'GND' state and the other starting and resetting is four gate working times.

Second, the phase detector in the power supply potential state will effectively mask the phase detector input signal that caused it to enter the power supply potential state.

Detailed Description

The various numbered devices in fig. 3 are described below.

A. edge detection identified as 1, 9: the rising edge of the edge example of the input signal is detected, and the output terminal Q is "1" when the edge is detected. When the reset terminal r=1, the reset function is performed, the output terminal Q is set to "0", and the Q terminal is the inverting output terminal of the Q terminal.

B. s1, identified as 2: the two optional access ports of the switch are respectively connected to the power supply connection end in a solidifying mode, when the switch control end a= "1", the common end of the switch, namely the output end, is connected with the Vcc end, and when the switch control end a= "0", the common end of the switch is connected with the GND end.

C. S2, identified as 3: the unidirectional analog switch has two ports as input and output ends of the switch. The switch is turned off when the switch control terminal a= "1", and the switch is turned on when a= "0".

D. S2, identified as 8: the unidirectional digital switch has two ports as input and output ends of the switch. The switch is turned off when the switch control terminal a= "1", and the switch is turned on when a= "0".

E. High level detection identified as 4: its function is like a digital multiplier identified as 6.

F. Marked 6×: the digital multiplier outputs "1" when both input signals are "1", and outputs "0" when the other input signals are "0".

G. + identified as 5, 7: the digital adder outputs "0" when both input signals are "0", and "1" when the other input signals are "1".

H. Delayed inversion identified as 10: the delay and inversion of the input signal ensures that the flip-flop is effectively reset once the segment of the reset signal is enabled.

I. Delay identified as 11: the input signal is delayed, the delay time is slightly longer than the delay time in the delay inversion phase, and the circuit functions to effectively shield the high-resistance phase discriminator in the initial state from the effective effect of 10 delay inversion.

J. Marked 12×: the digital multiplier outputs '1' when the two input signals are '1', and outputs '0' when the two input signals are '1', and the circuit function is that the phase detector in the power supply potential state effectively shields the input signals of the phase detector which are caused to enter the power supply potential state.

Fig. 4 is a circuit diagram of an implementation of the block diagram of fig. 3, in which various numbered devices are described below.

D2, D3 are two D flip-flops, corresponding to the "rising edge detection" of the input signals labeled 1 (D2) and 9 (D3) in the block diagram of fig. 3.

D1 is an alternative digital to analog switch, for example, an IC of 74hc 4053; corresponding to the two analog switches identified as 2,3 in the block diagram of fig. 2, this is an exemplary output interface circuit made in accordance with the standard type interface circuit of the high-resistance digital phase detector output stage of patent application number 201510644884.9 and the standard type interface circuit of the non-FET switch class of the high-resistance phase detector output stage of patent application number 201710401844.0.

U1, U7 are and gates corresponding to a "high detection" labeled 4 and a "x" labeled 12 in the block diagram of fig. 3, which function to output "H" if both input signals are "H", otherwise "L".

The "high level detection" completes the function of forming two conditions of the reset signal: the two input signals are synchronous with the rising edge, and the two input signals arriving before and after the rising edge are in the same H state.

The "x" completes the effective shielding when the phase detector is already in the power supply potential state, and the rising edge of the input signal which causes the phase detector to enter the power supply potential state is effective again.

U2, U4 are or gates, corresponding to "+" identified as 5 (U2) and 7 (U4) in the block diagram of fig. 3. The function of U2 is that as long as the reset valid signal exists, the function of U4 is that as long as the "H" signal containing the rising edge information exists in the two phase detector input signals, one "H" signal containing the rising edge information exists, and if both the two phase detector input signals are in the "L" state, the output of U4 returns to the normal "L" state.

U3 is a three-input and gate corresponding to the two functions of the one-way digital switch labeled 8 and the "x" digital multiplier labeled 6 in the block diagram of fig. 3. The effect is that the "+" device, identified as 7, outputs a reset valid signal when it is active to output two consecutive rising edge signals.

U5 is a combination of the final inverter functions, corresponding to a "delayed inversion" identified as 10 in the block diagram of fig. 3, the length of the delay time being one duty cycle to ensure that the output of U3 forms a valid reset signal.

U6 is a combination of the final in-phase function, corresponding to the "delay" identified as 11 in the block diagram of fig. 3, the length of the delay time being slightly greater than the delay time of U5.

The high-resistance phase detector of the invention outputs as the initial state after the reset of the edge type phase detector, the implementation mode is that the circuit block diagram of the edge type phase detector shown in figure 3 (hereinafter referred to as block diagram) of the invention marks 5"+" to form the reset signal, load on the reset end of the edge detection trigger of marks 1, 9. After reset, the trigger reverse phase output end value of the mark 9 is an 'H' state value, a control end signal of the unidirectional analog switch S2 is loaded, and if the trigger reverse phase output end value is the 'H' state value, the switch is disconnected. And meanwhile, after reset, the flip-flop reverse output end value of the mark 1 is an 'H' -state value, and the digital switch of the open mark 12 waits for the arrival of an input edge signal. The circuit diagram of the specific implementation, namely the Q reverse end output of D3 in the internal circuit diagram of the edge type phase discriminator (hereinafter referred to simply as circuit diagram) of the invention shown in fig. 4, is "H", and the output of the alternative analog switch is shielded under the action of INH signal as D1, namely the output of the phase discriminator is in a high-resistance state. The reset signal is formed in the following three modes:

a. The rising edges of the two input signals arrive synchronously, the synchronous edge signal is detected by the high level detection of the identification number 4 in the block diagram, namely U1 in the circuit diagram, and a reset signal is sent out by the digital adder of the identification number 5 in the block diagram, namely U2 in the circuit diagram.

B. The edge of any one input signal arrives, and the edge of the other input signal arrives during the period when the signal is maintained at the 'H' potential, and a reset signal is sent out by the same U2 in the previous a.

C. Wherein the rising edge of any input signal reaches and returns to the L-potential (0 ≡10 signal form), and the edge of any input signal (0 ≡1 signal form) continues to reach. The input signal is also valid if the digital switch of the tag 12 continues to remain in the open state, whereas the input signal is masked if the digital switch of the tag 12 is in the closed state. Once the second two rising edge signals are detected by the digital adder denoted 7 in the block diagram, i.e. by U4 in the circuit diagram, respectively, a reset signal is sent via U2, and the valid duration of the reset signal is determined by the delay time denoted 10, i.e. by the delayed inversion, since the output state denoted 10 in the block diagram, i.e. the output state denoted 9 in the block diagram, i.e. the output state denoted H at the Q terminal of D3 in the circuit diagram, is denoted 6, i.e. the switch is turned on by the unidirectional digital switch denoted 8 in the block diagram, or by the digital switch control terminal signal of U3 in the circuit diagram.

The reset signal formed by u1 has priority.

The working principle of the edge type high-resistance digital phase discriminator according to the invention is now described in detail with reference to fig. 4 as follows:

1. High resistance state of initial state (after reset)

At the initial state WrWc = - (-is any code, and the following is the same), the Q-terminal reverse terminal output of D2 is "1", and then U7 of the digital switch is opened. Since inh=1, the output of the phase detector is masked, i.e. assumes a high resistance state. Therefore, the definition is met: wrWc = -PDo = high resistance state.

2. An input signal rising edge in the initial state arrives

For example, when the rising edge signal of Wr arrives alone, at this time, since the digital switch U7 is in the on state, and the U4 filtered to the rising edge signal sends out a rising edge signal, the Q terminal output of D3 is switched from the "0" state to the "1" state at the initial state, and the control right formed by the reset signal of U3 is delayed. Since the delay time of U6 is longer than the delay time of U5, that is, the reset signal forming control right of U3 has been turned off by the output signal of U5 before being opened, the reset signal output of U3 is not formed after the rising edge signal arrives. When the rising edge signal returns to the initial state "L", the control right is opened due to the reset signal formation of U3, which is the output of U5 being "H".

When the rising edge signal of Wr arrives, the Q-terminal reverse terminal forming D2 outputs "0", i.e., the digital switch U7 is turned off to no longer output the rising edge signal of Wr. Meanwhile, the Q end output of the D2 is switched from the 0 state to the 1 state, and at the moment, as the Q end reverse end output of the D2, namely INH signal is 0, the output end of the one-out-of-two switch of the D1 is connected with Vcc, the output of the phase discriminator is Vcc, and the definition is met: wrWc = ≡ PDo = 1 (H) state. Conversely, when Wc's rising edge signal alone arrives, the aforementioned D3 operating state change continues to be valid as U4 filters the rising edge signal. But D2 without rising edge signal remains unchanged in the initial state, and the output end of the alternative switch labeled 2 is connected with GND, so that the output of the phase discriminator is GND, and the definition is met: PDo =0 (L) state when WrWc = - ≡.

3. An input signal rising edge in the non-initial state arrives

For the phase detector output in PDo =1 (H) state, the digital switch U7 is in the off state, i.e. the input signal, i.e. the positive going edge signal, is also an inactive signal. Once U4 filters out that one of the two input signals arrives, the rising edge signal of its output will trigger U3 to output a reset signal, and its validity will be guaranteed by the delay time of U5 and the sustain time of the rising edge signal.

The phase detector in the non-initial state returns to the initial state under the action of the reset signal, and meets the definition, namely the specification of the state transition diagram of fig. 2.

S1 of the symbol 2 in fig. 3 and S2 of the symbol 3 conform to one form of standard type interface circuit in the standard type interface circuit of the output stage of the high-resistance digital phase detector of patent application number 2015106448849, namely, an application example of the output signal "a" of the symbol 1 in fig. 3 and the output signal "INH" of the symbol 9 in fig. 3.

By combining the above, based on the provision in the design method of the structural principle scheme of the standardized design high-resistance digital phase discriminator with the patent application number 2015106449019, the brand new design and development work of the edge type high-resistance digital phase discriminator can be realized.

Claims

1. An edge type high-resistance digital phase detector, which is provided with an input port Wr, an input port Wc and an output port PDo of the phase detector, comprising: the first D trigger, the second D trigger, the alternative digital analog switch, the first AND gate, the second AND gate, the first OR gate, the second OR gate, the three-input AND gate, the delay inversion and the delay, wherein the alternative digital analog switch is 74HC4053; the digital signal processing circuit is characterized in that the D ends of a first D trigger and a second D trigger are simultaneously connected with a Vcc end, an input port Wr is simultaneously connected with a clock input end of the first D trigger, a first input end of a first AND gate and a first input end of a second AND gate, an input port Wc is simultaneously connected with a second input end of the first AND gate and a second input end of the first OR gate, an inverted output end of the first D trigger is connected with a second input end of the second AND gate, an output end of the second AND gate is connected with a first input end of the first OR gate, and an output end of the first AND gate is connected with a first input end of the second OR gate; the first AND gate meets the condition of high level detection, wherein the high level detection is configured to be that two input signals are synchronous with rising edges, and two input signals arriving before and after the rising edges are in the same H state, and the output end of the first OR gate is simultaneously connected with the first input end of the three-input AND gate, the input end of the delay inversion and the clock input end of the second D trigger; the first or gate satisfies the following conditions: the input signal only needs to send an 'H' signal containing rising edge information, the output end of the delay inversion is connected with the third input end of the three-input AND gate, the positive output end of the second D trigger is connected with the delayed input end, the delayed output end is connected with the second input end of the three-input AND gate, and the output end of the three-input AND gate is connected with the second input end of the second OR gate; the three-input AND gate is configured to effectively output two continuous rising edge signals, and then send a reset effective signal, the output end of the second OR gate is simultaneously connected with the reset ends of the first D trigger and the second D trigger, the a end of the one-out-of-two digital analog switch is connected with the normal phase output end of the first D trigger, the INH end of the one-out-of-two digital analog switch is connected with the reverse phase output end of the second D trigger, the 1 end of the one-out-of-two digital analog switch is connected with the Vcc end, the 0 end of the one-out-of-two digital analog switch is connected with the GND end, and the COM end of the one-out-of-two digital analog switch is connected with the output port of the phase discriminator.