CN111324302B

CN111324302B - Data storage device and method of operating the same

Info

Publication number: CN111324302B
Application number: CN201911257307.9A
Authority: CN
Inventors: 金佑冽
Original assignee: SK Hynix Inc
Current assignee: Mimi Ip Co ltd
Priority date: 2018-12-13
Filing date: 2019-12-10
Publication date: 2023-09-01
Anticipated expiration: 2039-12-10
Also published as: KR20200073122A; CN111324302A

Abstract

The present application relates to a data storage device and a method of operating the same. The data storage device may include: a nonvolatile memory; and a controller configured to control an operation of the nonvolatile memory. When a command is received from a host, a controller transmits first state information to the host as a response to the command, the first state information including first time information from a time point when the command is received to a time point when a task corresponding to the command is generated and stored. When a task execution command is received from the host, the controller transmits second state information to the host as a response to the task execution command, the second state information including second time information from a point in time when the task execution command is received to a point in time when the task is completely executed.

Description

Data storage device and method of operating the same

Cross Reference to Related Applications

The present application claims priority from korean applications filed on the applicant of application nos. 10-2018-0161244 and 10-2019-0150235, both on 12/13 and 11/21/2019, which are incorporated herein by reference in their entirety.

Technical Field

Various embodiments relate generally to a semiconductor device, and more particularly, to a data memory device and a method of operating the data memory device.

Background

In general, the semiconductor memory device may be a volatile memory device such as a Dynamic Random Access Memory (DRAM) or a Static Random Access Memory (SRAM), or a nonvolatile memory device such as a flash memory, a Ferroelectric Random Access Memory (FRAM), a phase change random access memory (PRAM), or a Magnetic Random Access Memory (MRAM). Volatile memory devices lose data stored therein when power is removed, but nonvolatile memory devices retain stored data even when power is removed. In particular, a flash memory, which is a kind of nonvolatile memory device, has a high programming speed and low power consumption, and can store a large amount of data. Accordingly, the flash memory is widely used as a storage medium in various applications requiring low power and mass storage devices, such as MP3 players, digital cameras, solid State Drives (SSD), embedded multimedia cards (eMMC), and computer systems. eMMC, which is a data storage device using a nonvolatile memory, has a controller coupled thereto, and is mainly used in mobile products such as smart phones or tablet computers.

Disclosure of Invention

Various embodiments relate to a data storage device and an operating method of the data storage device capable of checking an accurate delay for command processing.

In an embodiment, a data storage device may include: a nonvolatile memory; and a controller configured to control an operation of the nonvolatile memory. When a command is received from the host device, the controller may transmit first state information to the host device as a response to the command, the first state information including first time information from a time point when the command is received to a time point when a task corresponding to the command is generated and stored. When a task execution command is received from the host device, the controller may transmit second state information including second time information from a point of time when the task execution command is received to a point of time when the task is completely executed to the host device as a response to the task execution command.

In an embodiment, a method of operating a data storage device is provided, the data storage device comprising a non-volatile storage device; and a controller configured to control an operation of the nonvolatile memory device. The method of operation may include: generating and storing a task corresponding to a command received from a host device; transmitting first state information to the host device as a response to the command, the first state information including first time information from a time point when the command is received to a time point when the task is stored; controlling the nonvolatile memory to execute an operation corresponding to a task according to a task execution command received from the host device; and transmitting second state information to the host device as a response to the task execution command, the second state information including second time information from a point of time when the task execution command is received to a point of time when the task is completely executed.

In an embodiment, a data storage device may include: a memory device; and a controller configured to provide the first processing time information and the second processing time information to the external element. The first processing time information indicates a time taken by the controller to generate a task in response to a first command provided from the external element, and the second processing time information indicates a time taken by the controller to complete execution of the task in response to a second command provided from the external element.

Drawings

Fig. 1 is a diagram showing a configuration of a data storage device according to an embodiment.

Fig. 2 is a diagram illustrating the memory of fig. 1.

Fig. 3 is a diagram showing a configuration of the host of fig. 1.

Fig. 4 is a diagram illustrating a host memory of fig. 3.

Fig. 5 is a diagram illustrating a configuration of a Command Queue (CQ) engine of fig. 3.

Fig. 6 is a flowchart illustrating an operation of a data storage device according to an embodiment.

FIG. 7 is a diagram illustrating a data processing system including a Solid State Drive (SSD), according to an embodiment.

Fig. 8 is a diagram showing a configuration of a controller such as the controller of fig. 7.

FIG. 9 is a diagram illustrating a data processing system including a data storage device according to an embodiment.

FIG. 10 is a diagram illustrating a data processing system including a data storage device according to an embodiment.

Fig. 11 is a diagram illustrating a network system including a data storage device according to an embodiment.

Fig. 12 is a block diagram illustrating a nonvolatile memory included in a data storage device according to an embodiment.

Detailed Description

The advantages, features and methods of accomplishing the same may become more apparent in the present application upon reading the following exemplary embodiments in conjunction with the accompanying drawings. This application may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be described in detail, to the extent that those skilled in the art to which the present disclosure pertains may readily implement the technical concept of the present disclosure. Note that reference to "an embodiment" is not necessarily to only one embodiment, and different references to "an embodiment" are not necessarily to the same embodiment.

In this context, it will be understood that embodiments of the application are not limited to the details shown in the drawings, and that the drawings are not necessarily to scale, and that in some cases the proportions may be exaggerated for the purpose of more clearly describing certain features of the application. Although specific terms are employed herein, it is to be understood that the terms used herein are used solely for the purpose of describing particular embodiments and are not intended to limit the scope of the present application.

As used herein, the phrase "and/or" includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "on," "connected to," or "coupled to" another element, it can be directly on, connected or coupled to the other element or intervening elements may be present. As used herein, the singular is also intended to include the plural unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of at least one stated feature, step, operation, and/or element, but do not preclude the presence or addition of one or more other features, steps, operations, and/or elements.

Hereinafter, various exemplary embodiments will be described in detail with reference to the accompanying drawings.

Fig. 1 is a diagram showing a configuration of a data storage device 10 according to an embodiment.

Referring to fig. 1, a data storage device 10 may store data accessed by a host 20 such as: mobile phones, MP3 players, laptop computers, desktop computers, gaming machines, TV or in-car infotainment systems. The data storage device 10 may also be referred to as a memory system.

The data storage device 10 may be manufactured or configured as any of a variety of types of storage devices, depending on the interface protocol coupled to the host 20. For example, the data storage device 10 may be configured as any one of the following: solid State Drives (SSD), multimedia cards (MMCs), such as eMMCs, RS-MMCs, or micro-MMCs, secure Digital (SD) cards, such as mini-SD or micro-SD cards, universal Serial Bus (USB) storage devices, universal flash memory (UFS) devices, personal Computer Memory Card International Association (PCMCIA) card storage devices, peripheral Component Interconnect (PCI) card storage devices, PCI express (PCI-E) card storage devices, compact Flash (CF) cards, smart media cards, and memory sticks.

The data storage device 10 may be manufactured in any of a variety of types of packages. For example, the data storage device 10 may be manufactured such as any one of the following: stacked package (POP), system In Package (SIP), system on a chip (SOC), multi-chip package (MCP), chip On Board (COB), wafer level fabrication package (WFP), and wafer level stacked package (WSP).

The data storage device 10 may include a nonvolatile memory 100 and a controller 200.

The nonvolatile memory 100 may operate as a storage medium of the data storage device 10. The nonvolatile memory 100 may be configured to include any of the following various types of nonvolatile memory devices: NAND flash memory devices, NOR flash memory devices, ferroelectric Random Access Memory (FRAM) using ferroelectric capacitors, magnetoresistive RAM (MRAM) using Tunnel Magnetoresistive (TMR) layers, phase Change RAM (PCRAM) using chalcogenide alloys, and resistive RAM (RERAM) using transition metal oxides.

Fig. 1 shows that the data storage device 10 includes a non-volatile memory 100. However, this is merely an example; in another embodiment, the data storage device 10 may include a plurality of non-volatile memories. As will be appreciated by those skilled in the art, the principles of the present disclosure described in the context of a data storage device 10 having one non-volatile memory may be applied in the same manner to a data storage device 10 comprising a plurality of non-volatile memories.

The nonvolatile memory 100 may include a memory cell array (not shown) having a plurality of memory cells arranged at respective intersections between a plurality of bit lines (not shown) and a plurality of word lines (not shown). The memory cell array may include a plurality of memory blocks, and each of the memory blocks may include a plurality of pages.

For example, each of the memory cells of the memory cell array may be configured as a single-layer cell (SLC) capable of storing 1-bit data or as a multi-layer cell (MLC) capable of storing 2-bit or more data. For example, an MLC may store 2-bit data, 3-bit data, 4-bit data, or more. In general, a memory cell storing 2-bit data may be referred to as MLC, a memory cell storing 3-bit data may be referred to as Triple Layer Cell (TLC), and a memory cell storing 4-bit data may be referred to as Quad Layer Cell (QLC). However, in the following discussion, memory cells storing 2 or more bits of data may be considered MLCs.

The memory cell array may include one or more of SLCs and MLCs. In addition, the memory cell array may include memory cells having a two-dimensional horizontal structure or memory cells having a three-dimensional vertical structure.

The controller 200 may control the overall operation of the data storage device 10 by driving firmware or software that is loaded into the memory 230. The controller 200 may decode and drive code-based instructions or algorithms, such as firmware or software. The controller 200 may be implemented in hardware or a combination of hardware and software.

The controller 200 may include a host interface 210, a processor 220, a memory 230, and a memory interface 240. Although not shown in fig. 1, the controller 200 may further include an Error Correction Code (ECC) engine that generates parity data by performing ECC encoding on write data provided from the host 20 and performs ECC decoding on read data read from the nonvolatile memory 100 using the parity data.

The host interface 210 may interface the host 120 and the data storage device 10 according to the protocol of the host 20. For example, host interface 210 may communicate with host 20 via various protocols such as: USB (universal serial bus), UFS (universal flash memory), MMC (multimedia card), PATA (parallel advanced technology attachment), SATA (serial advanced technology attachment), SCSI (small computer system interface), SAS (serial attached SCSI), PCI (peripheral component interconnect), and PCI-E (PCI express).

The processor 220 may include a Micro Control Unit (MCU) and/or a Central Processing Unit (CPU). The processor 220 may process requests transmitted from the host 20. To process requests transmitted from the host 20, the processor 220 may drive code-based instructions or algorithms, i.e., firmware, loaded into the memory 230 and control the nonvolatile memory 100 and internal functional blocks such as the host interface 210, the memory 230, and the memory interface 240.

The processor 220 may generate a control signal for controlling the operation of the nonvolatile memory 100 based on a request transmitted from the host 20, and provide the generated control signal to the nonvolatile memory 100 through the memory interface 240.

The memory 230 may be configured as a Random Access Memory (RAM) such as Dynamic RAM (DRAM) or Static RAM (SRAM). Memory 230 may store firmware driven by processor 220. In addition, the memory 230 may store data of the driving firmware, such as metadata. That is, the memory 230 may operate as a working memory of the processor 220.

The memory 230 may include a data buffer for temporarily storing write data to be transferred from the host 20 to the nonvolatile memory 100 or read data to be transferred from the nonvolatile memory 100 to the host 20. That is, the memory 230 may operate as a buffer memory.

The memory interface 240 may control the nonvolatile memory 100 under the control of the processor 220. The memory interface 240 may also be referred to as a memory controller. The memory interface 240 may provide control signals to the nonvolatile memory 100. The control signals may include command, address, and operation control signals for controlling the nonvolatile memory 100. The memory interface 240 may provide data stored in the data buffer to the nonvolatile memory 100 or store data transferred from the nonvolatile memory 100 in the data buffer.

Fig. 2 is a diagram illustrating the memory 230 of fig. 1.

Referring to fig. 2, the memory 230 according to the present embodiment may include a first area 231 storing a Flash Translation Layer (FTL) and a second area 233 serving as a task queue for queuing tasks generated based on commands received from the host 20.

When the non-volatile memory 100 is configured as a flash memory device, the processor 220 may control the native (unique) operation of the non-volatile memory 100 and drive software called FTL to provide device compatibility with the host 20. When the FTL is driven, the host 20 can identify the data storage device 10 and use the data storage device 10 as a general-purpose storage device such as a hard disk.

FTL stored in the first region R1 of the memory 230 may include modules for performing various functions and metadata required to drive the respective modules. FTLs may be stored in a system area (not shown) of non-volatile memory 100. When the data storage device 10 is powered on, the FTL may be read from the system area of the non-volatile memory 100 and loaded into the first region R1 of the memory 230.

Tasks may be generated by the processor 220 and stored in a second region of the memory 230. A task may include the same information as a command corresponding to the task. For example, the task may include the type of command received from the host, a starting logical address, and data size information (or length information of the logical address). When a command is received from the host 20, the processor 220 may generate a task corresponding to the received command and queue the generated task in the task queue 233 of the memory 230. The command received from the host 20 may be a command related to an operation performed by the nonvolatile memory 100 of the data storage device 10. For example, although the command may include a read command, a write command, an erase command, and the like, the embodiment is not limited thereto.

Referring to fig. 2, the memory 230 includes only a first region R1 storing FTLs and a second region R2 serving as a task queue. As will be appreciated by those skilled in the art, memory 230 need not be limited to these two regions; in contrast, the memory 230 may include other areas for various purposes, such as an area serving as a write data buffer for temporarily storing write data, an area serving as a read data buffer for temporarily storing read data, and an area serving as a map cache buffer for caching map data, in addition to the areas shown in fig. 2.

Fig. 3 is a diagram showing a configuration of the host 20 of fig. 1.

Referring to fig. 3, the host 20 may include a host controller 310, a host memory 320, and a Command Queue (CQ) engine 330.

The host controller 310 may be configured to control the overall operation of the host 20. For example, the host controller 310 may include a Micro Control Unit (MCU) and a Central Processing Unit (CPU).

The host controller 310 may generate a description for generating a command to be provided to the data storage device 10 and store the generated description in the host memory 320.

Fig. 4 is a diagram showing a configuration of the host memory 320 of fig. 3.

The host memory 320 may include a description area 321 for storing descriptions generated by the host controller 310. Fig. 4 shows that the host memory 320 includes only the description area 321. However, the present embodiment is not limited thereto, but it is apparent to those skilled in the art that the host memory 320 may further include areas for various purposes.

Fig. 5 is a diagram illustrating a configuration of the CQ engine of fig. 3.

CQ engine 330 may include a command generator 331, a first status register 333, and a second status register 335. Although not shown in fig. 5, CQ engine 330 may further include a controller (not shown) for controlling the overall operation of CQ engine 330.

The command generator 331 may acquire the description stored in the host memory 320 and generate a command to be provided to the data storage device 10 based on the acquired description. The controller of CQ engine 330 may provide the commands generated by command generator 331 to data storage device 10. The controller of CQ engine 330 may periodically check whether the new description is stored in description area 321 of host memory 320. When the new description is stored in the description area 321, the controller of the CQ engine 330 may acquire the stored new description and provide the acquired description to the command generator 331. For example, the controller of the CQ engine 330 may check whether the new description has been stored in the description area 321 by a polling method.

The first status register 333 may be configured to store first status information received from the data storage device 10. The first state information may include first time information and task generation state information indicating whether the data storage device 10 is fully ready to execute a task corresponding to a command received from the host 20. The first time information may include information indicating a time required from a point of time when the host 20 receives the command to a point of time when a task corresponding to the received command is queued in the task queue 233.

The processor 220 may calculate a time from a time point when the command is received from the host 20 to a time point of a task corresponding to the completely generated and stored command, and include the calculated time as first time information in the first state information. That is, the first state information may include first time information and task generation state information indicating whether generation of a task has been completed. For example, the first state information may include a plurality of bits, some of which may be set to indicate task generation state information, and others of which may be set to indicate first time information.

The second status register 335 may be configured to store second status information received from the data storage device 10. The second state information may include second time information and task execution state information indicating whether the task has been completely executed. The second time information may include information indicating a time required from a time point when the task execution command is received by the host 20 to a time point when the corresponding task is completely executed.

For example, when first state information is received from data storage device 10, host controller 310 may store the received first state information in a first state register of CQ engine 330 and transmit a task execution command to data storage device 10. The task execution command may be a command to execute one or more tasks queued in the task queue 233 of the data storage device 10.

When a task execution command is received from the host 20, the processor 220 of the data storage device 10 may dequeue a task corresponding to the received task execution command from the task queue 233 and control the nonvolatile memory 100 to perform an operation corresponding to the dequeued task. When the operation corresponding to the task is completely performed, the processor 220 may transmit second state information to the host 20, the second state information indicating that the task corresponding to the task execution command received from the host 20 has been completely processed.

The processor 220 may calculate a time from a time point when the host 20 receives the task execution command to a time point when the task corresponding to the received command is completely processed, and include the calculated time as second time information in the second state information. That is, the second state information may include second time information and task execution state information indicating whether the task has been completely executed. For example, the second state information may include a plurality of bits, some of which may be set to indicate task execution state information, and others of which may be set to indicate second time information.

Host controller 310 may store the second state information received from data storage device 10 in a second state register 335 within CQ engine 330.

Accordingly, the first time information and the second time information may be stored in the CQ engine 330 of the host 20. The first time information may indicate a processing time of the data storage device 10 from a time point when the CQ engine 330 of the host 20 receives a command to a time point when a task corresponding to the received command is generated and stored, and the second time information may indicate a processing time of the data storage device 10 from a time point when the CQ engine 330 of the host 20 receives a task execution command to a time point when the corresponding task is completely executed.

Accordingly, the data storage device 10 can provide the information on the time required to generate and store a task in response to a command and the time required to process the task in response to a task execution command to the host 20, which can accurately check the delay of command processing in the data storage device 10.

Fig. 6 is a flowchart illustrating a method of operation of the data storage device 10 according to an embodiment. To describe the method of operation of the data storage device 10 according to the present embodiment with reference to fig. 6, one or more of fig. 1 to 5 may be referred to.

In step S610, the host 20 may transmit a command to the data storage device 10. The command may be a command related to an operation performed by the nonvolatile memory 100 of the data storage device 10. For example, although the command may include a read command, a write command, an erase command, and the like, the embodiment is not limited thereto. For example, although the command may include information indicating the type of the command, a start logical address, and data size information (or length information of the logical address), the embodiment is not limited thereto. Since the process of generating and storing commands by the host 20 has been described above, a detailed description thereof will be omitted herein.

In step S620, the processor 220 of the data storage device 10 may record a first time corresponding to a point in time when a command is received from the host 20.

In step S630, the processor 220 may generate a task corresponding to the command received from the host 20 and queue (or store) the generated task in the task queue 233 in the memory 230. A task may be generated that includes the same information as that included in the command.

In step S640, the processor 220 may record a second time corresponding to a point in time at which the generated task is stored in the task queue 233. Although not shown in fig. 6, the processor 220 may generate first state information including first time information corresponding to a difference between the first time and the second time and task generation state information indicating that the task has been completely generated.

In step S650, the processor 220 may transmit the generated first state information to the host 20.

In step S660, the host 20 may transmit a task execution command to the data storage device 10. Although not shown in fig. 6, the host 20 may store the first status information received from the data storage device 10 in the first status register 333 within the CQ engine 330 in step S650 before transmitting the task execution command to the data storage device 10.

In this step, the task execution command transmitted to the data storage device 10 by the host 20 may be an execution command for a task corresponding to the command transmitted to the data storage device 10 in step S610, or an execution command for a task not corresponding to the command.

In step S670, the processor 220 of the data storage device 10 may record a third time corresponding to a point of time at which a task execution command is received from the host 20.

In step S680, the processor 220 may acquire a task corresponding to the task execution command received from the host 20 from the task queue 233 of the memory 230, and control the nonvolatile memory 100 to perform an operation corresponding to the acquired task.

In step S690, the processor 220 may record a fourth time corresponding to a point in time at which the task is completely executed. Although not shown in fig. 6, the processor 220 may generate second state information including second time information corresponding to a difference between the third time and the fourth time and task execution state information indicating an execution state of the task.

In step S700, the processor 220 may transmit the generated second state information to the host 20. Although not shown in fig. 6, host 20 may store the second state information received from data storage device 10 in a second state register 335 within CQ engine 330.

According to the present embodiment, the data storage device and the operating method can provide information corresponding to a delay for command processing within the data storage device to the host, thereby easily checking an accurate delay for command processing within the data storage device.

FIG. 7 shows a diagram of a data processing system including a Solid State Drive (SSD), according to an embodiment. Referring to fig. 7, a data processing system 2000 may include a host device 2100 and a solid state drive SSD 2200.

The SSD 2200 may include a controller 2210, a buffer memory device 2220, nonvolatile memory devices 2231 to 223n, a power supply 2240, a signal connector 2250, and a power supply connector 2260.

The controller 2210 may control the overall operation of the SSD 2200.

The buffer memory device 2220 may temporarily store data to be stored in the nonvolatile memory devices 2231 to 223n. Further, the buffer memory device 2220 may temporarily store data read from the nonvolatile memory devices 2231 to 223n. The data temporarily stored in the buffer memory device 2220 may be transferred to the host device 2100 or the nonvolatile memory devices 2231 to 223n under the control of the controller 2210.

The nonvolatile memory devices 2231 to 223n may be used as storage media of the SSD 2200. The nonvolatile memory devices 2231 through 223n may be coupled to the controller 2210 through a plurality of channels CH1 through CHn, respectively. Each of the reference numerals 2231 through 223n may represent one or more nonvolatile memory devices, and in the case where each of the reference numerals 2231 through 223n may represent a plurality of nonvolatile memory devices, more than one nonvolatile memory device may be coupled to the same channel. A non-volatile memory device coupled to one channel may be coupled to the same signal bus and data bus.

The power supply 2240 may provide the power PWR input through the power connector 2260 into the SSD 2200. The power supply 2240 may include an auxiliary power supply 2241. The auxiliary power source 2241 may provide power to normally turn off the SSD 2200 when a sudden power outage occurs. The auxiliary power supply 2241 may include a large capacitor capable of storing the power PWR.

The controller 2210 may exchange signals SGL with the host device 2100 through a signal connector 2250. The signal SGL may include commands, addresses, data, etc. The signal connector 2250 may be configured as any of various types of connectors according to an interface method between the host device 2100 and the SSD 2200.

Fig. 8 shows a configuration of the controller of fig. 7. Referring to fig. 8, a controller 2210 may include a host interface 2211, a control component 2212, a RAM 2213, an ECC component 2214, and a memory interface 2215.

The host interface 2211 may interface the host device 2100 and the SSD 2200 according to a protocol of the host device 2100. For example, the host interface 2211 may communicate with the host device 2100 through any of various protocols such as: secure digital, USB (universal serial bus), MMC (multimedia card), eMMC (embedded MMC), PCMCIA (personal computer memory card international association), PATA (parallel advanced technology attachment), SATA (serial advanced technology attachment), SCSI (small computer system interface), SAS (serial SCSI), PCI (peripheral component interconnect), PCI-E (PCI express), and UFS (universal flash memory). The host interface 2211 may perform a disk emulation function that supports the host device 2100 to recognize the SSD 2200 as a general-purpose data storage device such as a Hard Disk Drive (HDD).

The control component 2212 may analyze and process the signal SGL received from the host device 2100. The control component 2212 may control the operation of the internal functional blocks according to firmware or software for driving the SSD 2200. The RAM 2213 may be used as a working memory for driving the firmware or software.

The ECC component 2214 can generate parity data for the data to be transferred to the nonvolatile memory devices 2231 through 223n. The generated parity data and data may be stored in the nonvolatile memory devices 2231 through 223n. The ECC component 214 can detect errors in the data read from the nonvolatile memory devices 2231 through 223n based on the parity data. When the detected error is within a correctable range, the ECC component 2214 can correct the detected error.

The memory interface 2215 may provide control signals such as commands and addresses to the nonvolatile memory devices 2231 through 223n under the control of the control component 2212. The memory interface 2215 can exchange data with the nonvolatile memory devices 2231 to 223n under the control of the control component 2212. For example, the memory interface 2215 may provide data stored in the buffer memory device 2220 to the nonvolatile memory devices 2231 to 223n, or data read from the nonvolatile memory devices 2231 to 223n to the buffer memory device 2220.

FIG. 9 illustrates a data processing system including a data storage device according to an embodiment. Referring to FIG. 9, data processing system 3000 may include a host device 3100 and a data storage device 3200.

Host device 3100 can be configured as a board such as a PCB. Although not shown in fig. 9, the host device 3100 may include internal functional blocks for performing the functions of the host device.

Host device 3100 can include connection terminals 3110, such as sockets, slots, or connectors. The data storage device 3200 may be mounted on the connection terminal 3110.

The data storage device 3200 may be configured as a board such as a PCB. The data storage 3200 may be referred to as a memory module or a memory card. The data storage device 3200 may include a controller 3210, a buffer memory device 3220, nonvolatile memory devices 3231 and 3232, a Power Management Integrated Circuit (PMIC) 3240, and a connection terminal 3250.

The controller 3210 may control the overall operation of the data storage device 3200. The controller 3210 may be configured in the same manner as the controller 2210 shown in fig. 8.

The buffer memory device 3220 may temporarily store data to be stored in the nonvolatile memory devices 3231 and 3232. Further, the buffer memory device 3220 may temporarily store data read from the nonvolatile memory devices 3231 and 3232. Data temporarily stored in buffer memory device 3220 may be transferred to host device 3100 or nonvolatile memory devices 3231 and 2232 under the control of controller 3210.

The nonvolatile memory devices 3231 to 3232 may be used as a storage medium of the data storage device 3200.

The PMIC 3240 may provide power received through the connection terminal 3250 into the data storage device 3200. The PMIC 3240 may manage power of the data storage device 3200 under the control of the controller 3210.

The connection terminal 3250 may be coupled to a connection terminal 3110 of the host device. Signals and power, including commands, addresses, data, etc., may be transferred between host device 3100 and data storage device 3200 through connection terminal 3250. Connection terminal 3250 may be configured in any of a variety of ways according to the method of interfacing between host device 3100 and data storage device 3200. The connection terminal 3250 may be provided at any one side of the data storage device 3200.

FIG. 10 illustrates a data processing system including a data storage device according to an embodiment. Referring to fig. 10, data processing system 4000 may include a host device 4100 and a data storage device 4200.

The host device 4100 may be configured as a board such as a PCB. Although not shown in fig. 10, the host device 4100 may include internal functional blocks for performing functions of the host device.

Data storage 4200 may be configured as a surface mount package. The data storage device 4200 may be mounted on the host device 4100 by solder balls 4250. The data storage device 4200 may include a controller 4210, a buffer memory device 4220, and a non-volatile memory device 4230.

The controller 4210 may control the overall operation of the data storage 4200. The controller 4210 may have been configured in the same manner as the controller 2210 shown in fig. 8.

The buffer memory device 4220 may temporarily store data to be stored in the nonvolatile memory device 4230. Further, the buffer memory device 4220 may temporarily store data read from the nonvolatile memory device 4230. The data temporarily stored in the buffer memory device 4220 may be transferred to the host device 4100 or the nonvolatile memory device 4230 under the control of the controller 4210.

The nonvolatile memory device 4230 may be used as a storage medium of the data storage device 4200.

Fig. 11 illustrates a network system 5000 including a data storage device according to an embodiment of the application. Referring to fig. 11, the network system 5000 may include a server system 5300 and a plurality of client systems 5410, 5420, and 5430 which are connected through a network 5500.

The server system 5300 can provide data in response to requests by multiple client systems 5410, 5420, and 5430. For example, the server system 5300 may store data provided from a plurality of client systems 5410, 5420, and 5430. For another example, the server system 5300 can provide data to a plurality of client systems 5410, 5420, and 5430.

The server system 5300 may include a host device 5100 and a data storage device 5200. The data storage 5200 may be configured as the data storage 10 of fig. 1, the data storage 2200 of fig. 7, the data storage 3200 of fig. 9, or the data storage 4200 of fig. 10.

Fig. 12 is a block diagram illustrating a nonvolatile memory included in a data storage device according to an embodiment. Referring to fig. 12, the nonvolatile memory 100 may include a memory cell array 110, a row decoder 120, a column decoder 140, a data read/write block 130, a voltage generator 150, and control logic 160.

The memory cell array 110 may include memory cells MC arranged at respective intersections between word lines WL1 to WLm and bit lines BL1 to BLn.

The row decoder 120 may be coupled to the memory cell array 110 through word lines WL1 to WLm. The row decoder 120 may operate under the control of the control logic 160. The row decoder 120 may decode an address supplied from an external device (not shown). The row decoder 120 may select and drive the word lines WL1 to WLm based on the decoding result. For example, the row decoder 120 may supply the word line voltages supplied from the voltage generator 150 to the word lines WL1 to WLm.

The data read/write block 130 may be coupled to the memory cell array 110 through bit lines BL1 to BLn. The data read/write block 130 may include read/write circuits RW1 to RWn corresponding to the respective bit lines BL1 to BLn. The data read/write block 130 may operate under the control of the control logic 160. The data read/write block 130 may operate as a write driver or a sense amplifier according to an operation mode. For example, during a write operation, the data read/write block 130 may operate as a write driver that stores data provided from an external device in the memory cell array 110. For another example, during a read operation, the data read/write block 130 may operate as a sense amplifier that reads data from the memory cell array 110.

The column decoder 140 may operate under the control of the control logic 160. The column decoder 140 may decode an address supplied from an external device. The column decoder 140 may couple the read/write circuits RW1 to RWn of the data read/write block 130 corresponding to the respective bit lines BL1 to BLn with a data input/output line (or a data input/output buffer) according to the decoding result.

The voltage generator 150 may generate a voltage for internal operation of the nonvolatile memory 100. The voltage generated by the voltage generator 150 may be applied to the memory cells of the memory cell array 110. For example, a program voltage generated during a program operation may be applied to a word line of a memory cell to be subjected to the program operation. For another example, an erase voltage generated during an erase operation may be applied to a well region of a memory cell to be subjected to the erase operation. For another example, a read voltage generated during a read operation may be applied to a word line of a memory cell to which the read operation is to be performed.

The control logic 160 may control the overall operation of the nonvolatile memory 100 based on a control signal provided from an external device. For example, the control logic 160 may control operations of the nonvolatile memory 100, such as read operations, write operations, or erase operations of the nonvolatile memory 100.

According to embodiments of the present disclosure, the latency of a data storage device may be measured.

While various embodiments have been illustrated and described, it will be appreciated by those skilled in the art, in light of the present disclosure, that the disclosed embodiments are merely examples. Thus, the present application is not limited to any of the described embodiments; on the contrary, the application includes all changes and modifications coming within the scope of the claims and their equivalents.

Claims

1. A data storage device, comprising:

a nonvolatile memory; and

a controller controlling the operation of the nonvolatile memory,

wherein when a command is received from a host, the controller transmits first state information to the host as a response to the command, the first state information including first time information from a time point when the command is received to a time point when a task corresponding to the command is generated and stored,

wherein when a task execution command is received from the host, the controller transmits second state information to the host as a response to the task execution command, the second state information including second time information from a point of time when the task execution command is received to a point of time when the task is completely executed.

2. The data storage device of claim 1, further comprising a memory, the memory comprising a task queue, the task queue queuing the tasks generated by the controller.

3. The data storage device of claim 1, wherein the first time information comprises a time required for the controller to generate a task corresponding to a received command in response to the received command.

4. The data storage device of claim 1, wherein the second time information includes a time required for the controller to generate a control signal for performing an operation corresponding to the task in response to the received task execution command and to provide the generated control signal to the nonvolatile memory, and a time required for the nonvolatile memory to complete the operation corresponding to the task.

5. The data storage device of claim 1, wherein the first status information further comprises task generation status information indicating that generation of the task corresponding to a command received from the host has been completed.

6. The data storage device of claim 5, wherein the first status information comprises a plurality of bits, some first bits of the plurality of bits being set to indicate the first time information and other second bits of the plurality of bits being set to indicate the task generation status information.

7. The data storage device of claim 1, wherein the second status information further comprises task execution status information indicating that the task has been completely executed.

8. The data storage device of claim 7, wherein the second status information comprises a plurality of bits, some first bits of the plurality of bits being set to indicate the second time information and other second bits of the plurality of bits being set to indicate the task execution status information.

9. The data storage device of claim 1, wherein the command comprises a command related to an operation performed by the non-volatile memory.

10. The data storage device of claim 1, wherein the task execution command is a command that controls the nonvolatile memory to execute an operation corresponding to the task.

11. A method of operation of a data storage device, the data storage device comprising a non-volatile memory; and a controller controlling an operation of the nonvolatile memory, the operation method including:

generating and storing a task corresponding to a command received from a host;

transmitting first state information to the host as a response to the command, the first state information including first time information from a point in time when the command is received to a point in time when the task is stored;

controlling the nonvolatile memory to execute an operation corresponding to a task according to a task execution command received from the host; and is also provided with

Second state information is transmitted to the host as a response to the task execution command, the second state information including second time information from a point in time when the task execution command is received to a point in time when the task is completely executed.

12. The method of operation of claim 11, wherein the generating and storing of the task comprises:

recording a first time corresponding to a point in time at which the command was received;

recording a second time corresponding to a point in time at which the task is stored; and

generating the first state information, the first state information including the first time information corresponding to a difference between the first time and the second time.

13. The method of operation of claim 12 wherein the first status information comprises a plurality of bits, some first bits of the plurality of bits being set to indicate the first time information and other second bits of the plurality of bits being set to indicate the task generation status information.

14. The method of operation of claim 11, wherein controlling the non-volatile memory to perform operations corresponding to the tasks comprises:

recording a third time corresponding to a time point when the task execution command is received;

recording a fourth time corresponding to a point in time at which an operation corresponding to the task is completely performed; and

generating the second state information including the second time information corresponding to a difference between the third time and the fourth time.

15. The method of operation of claim 14, wherein the second status information comprises a plurality of bits, some first bits of the plurality of bits being set to indicate the second time information, and other second bits of the plurality of bits being set to indicate information indicating whether execution of the task has been completed.

16. The method of operation of claim 11, wherein the command comprises a command related to an operation performed by the non-volatile memory.

17. The operation method according to claim 11, wherein the task execution command is a command that controls the nonvolatile memory to execute an operation corresponding to the task.

18. A data storage device, comprising:

a memory device; and

a controller for providing the first processing time information and the second processing time information to an external element,

wherein the first processing time information represents a time taken by the controller to generate a task in response to a first command provided from the external element,

wherein the second processing time information represents a time taken by the controller to complete execution of the task in response to a second command provided from the external element.