CN111162125B

CN111162125B - Method for monitoring height of grid material in semiconductor device

Info

Publication number: CN111162125B
Application number: CN201811325528.0A
Authority: CN
Inventors: 肖魁; 方冬; 卞铮
Original assignee: CSMC Technologies Fab2 Co Ltd
Current assignee: CSMC Technologies Fab2 Co Ltd
Priority date: 2018-11-08
Filing date: 2018-11-08
Publication date: 2022-09-16
Anticipated expiration: 2038-11-08
Also published as: CN111162125A

Abstract

The present invention provides a method for monitoring the height of a gate material in a semiconductor device, the method comprising: providing a semiconductor substrate, forming a trench in the semiconductor substrate; filling the trench with a gate material; measuring Resistance between two points on the top surface of the gate material; calculate the height of the gate material. According to the method for monitoring the height of the gate material in the semiconductor device provided by the present invention, the height of the gate material is calculated by measuring the resistance between two points on the top surface of the gate material, so as to monitor the height of the gate material online, and the method measures the height of the gate material. The required area is small, the application range is wide, and the waste of silicon wafers is avoided.

Description

Method for monitoring height of grid material in semiconductor device

Technical Field

The invention relates to the technical field of semiconductors, in particular to a method for monitoring the height of a gate material in a semiconductor device.

Background

A VDMOS (Vertical Double-diffused Metal-Oxide-Semiconductor) transistor is one of the MOSFETs, has characteristics of high power, high breakdown voltage, and the like, and is one of the common power devices. The groove type VDMOS forms a channel by forming a longitudinal diffusion distance difference after source ions and bulk ions are injected, and is widely applied to the fields of switching power supplies and synchronous rectification.

The trench type VDMOS device includes a general trench type VDMOS device and a subsequently developed Split Gate (Split Gate) trench type VDMOS device. The grooves of the common groove VDMOS device are completely filled with the polysilicon gates isolated by the gate oxide, and the grooves of the split-gate VDMOS device are distributed and filled with the oxide layer, the polysilicon connected with the source electrode and the polysilicon gates.

The existing method for monitoring the height of the grid electrode material mainly relies on SEM to monitor the appearance, but the appearance monitoring through the SEM has the defects of long slicing period, waste of silicon wafers and the like. The prior art can also monitor the depth of a part of the groove by online measurement, but the online measurement needs a measurement position with a larger area, so that the application range of the method is smaller, and the online measurement precision is lower.

Therefore, there is a need to provide a new method for monitoring the height of gate material in a semiconductor device to solve at least one of the above problems.

Disclosure of Invention

In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

The invention provides a method for monitoring the height of a gate material in a semiconductor device, which comprises the following steps:

providing a semiconductor substrate, and forming a groove in the semiconductor substrate;

filling a gate material in the groove;

measuring the resistance between two points on the top surface of the grid material;

the height of the gate material is calculated.

Further, the resistance between any two points of the exposed top surface of the gate material is measured.

Furthermore, a plurality of contact holes are formed on the grid electrode material, and the resistance between any two contact holes is measured.

Further, the height of the gate material is calculated by using the resistance of the gate material, the resistivity of the gate material, the width of the gate material and the length of the gate material.

Further, the resistance of the gate material is measured as the resistance between two points on the top surface of the gate material.

Further, the length of the gate material is the distance between two points on the top surface of the gate material when measuring the resistance of the gate material.

Further, the width of the gate material is the width of the trench.

Further, the semiconductor device includes a general trench type VDMOS device.

Further, the semiconductor device comprises a split-gate trench type VDMOS device.

According to the method for monitoring the height of the gate material in the semiconductor device, the height of the gate material is calculated by measuring the resistance between two points on the top surface of the gate material, so that the height of the gate material is monitored on line.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent by describing in more detail embodiments of the present invention with reference to the attached drawings. The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings, like reference numbers generally indicate like parts or steps.

In the drawings:

fig. 1A is a schematic diagram of the structure of a general trench type VDMOS device;

fig. 1B is a schematic diagram of the structure of a split-gate trench type VDMOS device;

FIG. 2 is a schematic flow chart of a method of monitoring gate material height in a semiconductor device according to an exemplary embodiment of the present invention;

fig. 3A is a top view of a conventional trench-type VDMOS device according to a first embodiment of the invention;

FIG. 3B is a cross-sectional view taken along lines M1, M2 of FIG. 3A;

FIG. 3C is a cross-sectional view of FIG. 3B after forming an interlevel dielectric layer and contact holes;

fig. 4A is a top view of a split-gate trench VDMOS device according to a second embodiment of the invention;

FIG. 4B is a cross-sectional view taken along lines N1, N2 of FIG. 4A;

FIG. 4C is a cross-sectional view taken along lines M1, M2 of FIG. 4A;

FIG. 4D is a cross-sectional view of FIG. 4C after forming an interlevel dielectric layer and contact holes;

fig. 5A is a top view of a split-gate trench VDMOS device according to a third embodiment of the invention;

FIG. 5B is a cross-sectional view taken along lines M1, M2 of FIG. 5A;

fig. 6A is a top view of a split-gate trench VDMOS device according to a fourth embodiment of the invention;

FIG. 6B is a cross-sectional view taken along lines M1, M2 of FIG. 6A;

fig. 6C is a cross-sectional view of fig. 6B after forming an interlayer dielectric layer and a contact hole.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.

It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In order to provide a thorough understanding of the present invention, detailed steps and detailed structures will be set forth in the following description in order to explain the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.

Referring to fig. 2, the present invention provides a method for monitoring the height of a gate material in a semiconductor device, comprising the steps of:

s201: providing a semiconductor substrate, and forming a groove in the semiconductor substrate;

s202: filling a gate material in the groove;

s203: measuring the resistance between two points on the top surface of the grid material;

s204: the height of the gate material is calculated.

Example one

As shown in fig. 1A, the structure of a general trench type VDMOS device includes: the structure comprises a substrate 100, wherein an epitaxial layer 101 is formed on the substrate 100, and a gate structure is formed in the epitaxial layer 101 and comprises a gate dielectric layer 103 and a gate material layer 104. An interlayer dielectric layer (ILD)108 is formed on the gate structure, and a body region (body)102, a P-type ion doped region (PSD)105, an N-type ion doped region (NSD)106, and a contact hole (CT)107 are formed at both sides of the gate structure.

The semiconductor device of the present embodiment is the above-described ordinary trench type VDMOS device.

First, referring to fig. 1A, step S201 is performed to provide a semiconductor substrate 100, and a trench is formed in the semiconductor substrate 100.

Illustratively, the semiconductor substrate 100 may be at least one of the following materials: single crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. In the present embodiment, the semiconductor substrate 100 is a silicon substrate.

Further, an epitaxial layer 101 is formed on the semiconductor substrate 100. The epitaxial growth may employ one of Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), and Molecular Beam Epitaxy (MBE). Illustratively, the material of epitaxial layer 101 includes, but is not limited to, monocrystalline silicon.

Further, a P well is formed in the epitaxial layer 101 as a Body region (Body) 102. As an example, a standard well implantation process is used to form a P-well in a semiconductor substrate, which may be formed by a high-energy implantation process or by a low-energy implantation process in combination with a high-temperature thermal annealing process.

Further, a trench is formed in the epitaxial layer 101. As an example, the trench is formed using a dry etching process, which includes, but is not limited to: reactive Ion Etching (RIE), ion beam etching, plasma etching, laser ablation or any combination of these methods, preferably dry etching by one or more RIE steps in which the Reactive Ion Etching (RIE) can achieve faster etching rates and good anisotropy by controlling the reactive gas, gas pressure, flow rate and rf power.

Next, referring to fig. 1A, step S202 is performed to fill the trench with a gate material.

Illustratively, a gate structure is formed in the trench, the gate structure including a gate dielectric layer 103 and a gate material layer 104. The gate dielectric layer 103 and the gate material layer 104 may be formed by any conventional technique known to those skilled in the art, preferably by Chemical Vapor Deposition (CVD), such as Low Temperature Chemical Vapor Deposition (LTCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD).

Illustratively, the gate dielectric layer 103 includes an oxide layer, such as silicon dioxide (SiO) ₂ ) And (3) a layer. The gate material layer 104 includes one or more of a polysilicon layer, a metal layer, a conductive metal nitride layer, a conductive metal oxide layer, and a metal silicide layer. In this embodiment, the gate material is selected from polysilicon or doped polysilicon.

Next, referring to fig. 3A-3C, step S203 is performed to measure the resistance between two points on the top surface of the gate material.

Illustratively, referring to fig. 3B, after forming the gate material layer 304, the resistance between any two points of the exposed top surface of the gate material layer 304 is measured.

As an example, as shown in FIG. 3A, when A, B is selected as the two points on the top surface of the gate material, the method of measuring A, B resistance includes direct measurement or indirect measurement.

When A, B are located on the exposed top surface of the gate material layer 304, the resistance between A, B can be measured directly.

In order to reduce the influence of the measuring device on the measurement result, the resistance between A, B can also be measured indirectly, and the steps include:

selecting at least one point on an extension line of the AB connection line, marking the point as D, and selecting at least one point on an extension line of the BA connection line, marking the point as C;

passing a current I between C, D;

measuring A, B the voltage V between;

the resistance R between A, B is calculated.

Referring to fig. 3C, after forming the gate material layer 304, a step of forming an interlayer dielectric layer (ILD)308 on the gate material layer 304 and a step of forming a plurality of contact holes 307 in the interlayer dielectric layer (ILD)308 are further included. The method of depositing the inter-layer dielectric (ILD) layer 308 and forming the contact hole 307 may be any method known to those skilled in the art and will not be described herein.

Further, the contact hole 307 is in contact with the top surface of the gate material layer 304.

Illustratively, referring to fig. 3C, after forming the interlayer dielectric layer 308 and the plurality of contact holes 307, the resistance between any two contact holes 307 is measured. Further, the method for measuring the resistance between two contact holes comprises direct measurement or indirect measurement.

Next, step S204 is performed to calculate the height of the gate material.

Illustratively, the height of the gate material is calculated using the following formula:

h＝(ρL)/(Rw) (1)

wherein the height of the h-gate material

Resistance of R-gate material

Resistivity of rho-gate material

width of w-gate material

Length of L-gate material

The resistance R of the gate material is measured between two points on the top surface of the gate material; the length L of the gate material is the distance between two points on the top surface of the gate material when measuring the resistance R of the gate material.

The method provided by the embodiment has a small area required for measurement, and can be used for measuring the height of the gate material of the cellular region.

Example two

As shown in fig. 1B, the structure of the Split Gate (Split Gate) trench type VDMOS device includes: the structure comprises a substrate 100, wherein an epitaxial layer 101 is formed on the substrate 100, and a gate structure is formed in the epitaxial layer 101 and comprises a first gate dielectric layer 109, a first gate material layer 110, an oxide layer 111, a second gate dielectric layer 103 and a second gate material layer 104. An interlayer dielectric layer (ILD)108 is formed on the gate structure, and a body region (body)102, a P-type ion doped region (PSD)105, an N-type ion doped region (NSD)106, and a contact hole (CT)107 are formed at both sides of the gate structure.

The materials and the forming methods of the first gate dielectric layer 109 and the second gate dielectric layer 103 are the same, and the materials and the forming methods of the first gate material layer 110 and the second gate material layer 104 are the same.

The semiconductor device of the present embodiment is the above-described Split Gate (Split Gate) trench type VDMOS device.

In the present embodiment, as shown in fig. 4A-4B, the first gate material layer 410 does not completely fill the trench.

Illustratively, referring to fig. 4C, the resistance between any two points of the exposed top surface of the first gate material layer 410 is measured.

Exemplarily, referring to fig. 4D, after the interlayer dielectric layer 408 and the plurality of contact holes 407 are formed, the resistance between any two contact holes 407 is measured.

Next, the height of the first gate material layer 410 is calculated according to a method provided in the first embodiment.

EXAMPLE III

The semiconductor device of this embodiment is the same as the Split Gate (Split Gate) trench type VDMOS device provided in the second embodiment.

As shown in fig. 5A and 5B, two trenches, i.e., a first trench and a second trench, are formed in the semiconductor substrate, wherein a first gate 5101 is formed in the first trench, and a second gate 5102 is formed in the second trench.

As an example. The height h1 of gate number one 5101 is calculated according to the method provided in the first embodiment.

Illustratively, the height h2 of the gate No. two 5102 is calculated according to the method provided in embodiment one.

Further, the height difference of the gate No. one 5101 and the gate No. two 5102 is determined.

In another embodiment, the height h1 of the gate No. one 5101 can be used to represent the height of the gate before the back etching step, and the height h2 of the gate No. two 5102 can be used to represent the height of the gate after the back etching step, and the difference between the heights is the back etching depth.

Example four

As shown in fig. 6A-6C, an oxide layer 611 and a second gate material layer 604 are sequentially formed in the semiconductor substrate over the first gate material layer 610. The second gate material layer 104 and the first gate material layer 110 are made of the same material and formed by the same method. In other embodiments, the second gate material layer 104 and the first gate material layer 110 are formed of different materials and by different methods.

Illustratively, the constituent material of the oxide layer 611 includes borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), Tetraethylorthosilicate (TEOS), Undoped Silicate Glass (USG), spin-on glass (SOG), high-density plasma (HDP), or spin-on dielectric (SOD). In the present embodiment, the oxide layer 611 is HDP.

Illustratively, referring to fig. 6B, the resistance between any two points of the exposed top surface of the second gate material layer 604 is measured.

Exemplarily, referring to fig. 6C, after forming the interlayer dielectric layer 608 and the plurality of contact holes 607, the resistance between any two contact holes 607 is measured.

Next, the height of the second gate material layer 604 is calculated according to a method provided in the first embodiment.

The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. A method for monitoring the height of a gate material in a semiconductor device, comprising the steps of:

providing a semiconductor substrate, and forming a groove in the semiconductor substrate by adopting a dry etching process;

filling a gate material in the groove;

measuring the resistance between two points on the top surface of the gate material, namely the resistance of the gate material;

calculating the height of the gate material by using the resistance of the gate material, the resistivity of the gate material, the width of the gate material and the length of the gate material; the length of the gate material is the distance between two points on the top surface of the gate material when the resistance of the gate material is measured, and the width of the gate material is the width of the groove;

calculating the height of a first gate material and the height of a second gate material, and calculating the height difference between the height of the first gate material and the height of the second gate material; the height of the first grid material comprises the height of the grid material before the etching step, the height of the second grid material comprises the height of the grid material after the etching step, and the height difference is the etching depth of the grid material.

2. The method of claim 1, wherein the resistance between any two points on the exposed top surface of the gate material is measured.

3. The method of claim 1, wherein a plurality of contact holes are formed in the gate material, and wherein the resistance between any two of the contact holes is measured.

4. The method of claim 1, wherein the semiconductor device comprises a normal trench type VDMOS device or a split-gate trench type VDMOS device.