CN111082656A - Novel current rudder type charge pump circuit - Google Patents

Novel current rudder type charge pump circuit Download PDF

Info

Publication number
CN111082656A
CN111082656A CN201911082627.5A CN201911082627A CN111082656A CN 111082656 A CN111082656 A CN 111082656A CN 201911082627 A CN201911082627 A CN 201911082627A CN 111082656 A CN111082656 A CN 111082656A
Authority
CN
China
Prior art keywords
tube
pmos
nmos
nmos tube
pmos tube
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201911082627.5A
Other languages
Chinese (zh)
Inventor
苗澎
王迪
王欢
黎飞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Southeast University
Original Assignee
Southeast University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Southeast University filed Critical Southeast University
Priority to CN201911082627.5A priority Critical patent/CN111082656A/en
Publication of CN111082656A publication Critical patent/CN111082656A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

The invention discloses a novel current rudder type charge pump circuit which comprises a unit gain follower OPA1, an error amplifier OPA2, an NMOS tube M1, an NMOS tube M3, NMOS tubes M9-M12, a PMOS tube M2, a PMOS tube M13 and PMOS tubes M4-M8. The unit gain operational amplifier OPA1 and the error amplification operational amplifier OPA2 are added in the invention, the current matching dynamic range is effectively expanded, thereby avoiding that the VCO sacrifices the voltage tuning range, for the error operational amplifier structure, because the gain is higher than the unit gain operational amplifier, a better current matching result can be obtained, the switching speed of the charge pump is improved, and the burr in the output power spectrum of the phase-locked loop is reduced.

Description

Novel current rudder type charge pump circuit
Technical Field
The invention relates to the field of charge pumps, in particular to a novel current rudder type charge pump circuit.
Background
The Charge Pump (CP) is an electronic switch that distributes charge to the loop filter under the control of the digital signals UP and DW output from the Phase Frequency Detector (PFD). When the phase discrimination sensitivity of the PFD is high enough, the CP determines the performance of the phase locked loop to a large extent.
The charge pump can be seen as two current sources controlled by switches UP, DW, a simple charge pump circuit as shown in fig. 1.1. The charge pump has three states during operation: when the UP signal is "1" and the DW signal is "0", the switch S1 is closed, the switch S2 is opened, and the capacitorLBy electricityStream source IUPCharging, VctrlIncreasing; when the signal UP is "0" and the signal DW is "1", the switch Sl is opened, the switch S2 is closed, and the capacitorLBy means of a current source IDWDischarge, VctrlDecrease; when the signals UP and DW are both zero, the switches Sl and S2 are simultaneously opened, and the capacitorLPassing a current of zero, VctrlRemain unchanged.
The conventional CMOS charge pump circuit generally uses MOS transistors to implement the switching function, as shown in fig. 1.2, two signals, UP and DW, are directly applied to the gates of the MOS transistors to control the conduction or non-conduction of the MOS transistors.
The non-ideal effects of the conventional CMOS charge pump are:
(1) mismatch phenomenon
Mismatches in the charge pump include current mismatches and switching time mismatches. The current mismatch refers to unequal charging and discharging currents caused by the mismatching of the charging and discharging current sources, and mainly comprises three kinds of current mismatches, namely asymmetrical charging current source and discharging current drain design, different charging current source and discharging current drain variation trends along with output voltage, and charging and discharging current jitter at the moment of switch closing, wherein the mismatches are mainly determined by some process parameters of the transistor. The switching time mismatch is the condition that the durations of the narrow pulses UP and DW at the output end of the PFD are not equal when the phase difference between two input signals of the PFD is zero due to the non-ideality of the PFD.
(2) Charge sharing
Charge sharing refers to the phenomenon of incorrect output levels caused by switch parasitic capacitances.
(3) Charge injection
Assuming that the MOS transistor is turned on and the source and drain voltages are approximately equal, when the switch is turned off, part of the charges in the inversion layer will flow out and be injected into the capacitor, which is called "charge injection". The "charge injection" causes the voltage value stored on the capacitor to change and affect the control voltage that controls the VCO output.
(4) Clock feedthrough
When the rising and falling edges of the signal controlling the CP switch change rapidly, the signal may be coupled to the output capacitor through the gate-drain or gate-source overlap capacitor of the MOS switch, and this error effect on the output voltage is called clock feedthrough.
Therefore, in the design of the charge pump, in the indexes of the charge pump, the mismatch has the greatest influence on the performance of the phase-locked loop system, how to reduce the mismatch to improve the performance is mainly considered in the design of the charge pump, and the problem of current mismatch needs to be solved first, that is, how to improve the matching of the current in the output voltage range as wide as possible, and in addition, factors such as charge injection and switching speed also have influence on the performance of the charge pump, and the factors also need to be considered in the circuit design.
Disclosure of Invention
The invention aims to solve the problems and provides a novel current steering type charge pump circuit.
In order to achieve the purpose, the invention adopts the technical scheme that: a novel current rudder type charge pump circuit comprises a unit gain follower OPA1, an error amplifier OPA2, an NMOS tube M1, an NMOS tube M3, NMOS tubes M9-M12, a PMOS tube M2, a PMOS tube M13 and PMOS tubes M4-M8;
the positive input end of the unit gain follower OPA1 is respectively connected with the drain of an NMOS tube M3, the drain of a PMOS tube M4 and the positive input end of an error amplifier OPA2 through nodes, the negative input end of the unit gain follower OPA1 is connected with the output end, the output end of the unit gain follower OPA1 is respectively connected with the drain of an NMOS tube M1 and the drain of a PMOS tube M2 through nodes, the source of the NMOS tube M3 is connected with the source of an NMOS tube M1 and then commonly connected with the drain of the NMOS tube M10, the source of the PMOS tube M4 is connected with the source of the PMOS tube M2 and then commonly connected with the drain of the PMOS tube M7, and the gates of the NMOS tube M3, the NMOS tube M1, the PMOS tube M4 and the PMOS tube M2 are all vacant; the positive input end of the unit gain follower OPA1 and the drain of the NMOS tube M3 are connected with a Vout output terminal through a node;
the negative electrode input end of the error amplifier OPA2 is respectively connected with the drain electrode of an NMOS tube M12 and the drain electrode of a PMOS tube M13 through nodes, the output end of the error amplifier OPA2 is respectively connected with the grid electrodes of a PMOS tube M7 and a PMOS tube M8 through nodes, the drain electrode of the PMOS tube M8 is connected with the source electrode of the PMOS tube M13, the grid electrode of the PMOS tube M13 is connected with a power supply VDD, and the source electrodes of the PMOS tubes M5-M8 and the grid electrode of the NMOS tube M12 are grounded;
the source electrode of the NMOS tube M12 is connected with the drain electrode of the NMOS tube M11, the grid electrode of the NMOS tube M11 is connected with the grid electrodes of the NMOS tube M9 and the NMOS tube M10, the source electrodes of the NMOS tube M9, the NMOS tube M10 and the NMOS tube M11 are connected with a power supply VDD in common, the drain electrode of the NMOS tube M9 is connected with the grid electrode of the NMOS tube M9 and the drain electrode of the PMOS tube M6 through nodes, the grid electrode of the PMOS tube M6 is connected with the grid electrode of the PMOS tube M5 and the drain electrode of the PMOS tube M5 through nodes, and the drain electrode of the PMOS tube M5 is connected with a current source.
Further, the unity gain follower OPA1 and the error amplifier OPA2 both use rail-to-rail operational amplifiers.
Further, the Vout output terminal is connected to one end of a capacitor through a node, and the other end of the capacitor is grounded.
Further, the NMOS transistor M3 is a charging switch, and the gate of the NMOS transistor M3 is used for connecting the digital signal UP of the PFD; the NMOS transistor M1 is a complementary switch of the charging switch, and the grid of the NMOS transistor M1 is used for connecting the digital signal UPN of the PFD.
Further, the PMOS transistor M4 is a discharge switch, and the gate of the PMOS transistor M4 is used for connecting the digital signal DW of the PFD; the PMOS tube M2 is a complementary switch of the discharge switch, and the grid of the PMOS tube M2 is used for connecting the digital signal DWN of the PFD.
Has the advantages that:
the unit gain operational amplifier OPA1 and the error amplification operational amplifier OPA2 are added in the invention, the current matching dynamic range is effectively expanded, thereby avoiding that the VCO sacrifices the voltage tuning range, for the error operational amplifier structure, because the gain is higher than the unit gain operational amplifier, a better current matching result can be obtained, the switching speed of the charge pump is improved, and the burr in the output power spectrum of the phase-locked loop is reduced.
Drawings
Fig. 1.1 is a schematic diagram of a simple charge pump circuit.
Fig. 1.2 is a schematic diagram of a conventional CMOS charge pump circuit.
Fig. 2 is a schematic diagram of a novel current steering type charge pump circuit according to the present invention.
Fig. 3.1 is a schematic diagram showing the OPA1 ac small signal simulation with gain stabilized at about 50 db.
Fig. 3.2 is a schematic diagram showing the OPA2 ac small signal simulation with gain stabilized at about 50 db.
Fig. 4.1 is a circuit diagram of CP static matching simulation.
Fig. 4.2 is a CP static matching graph.
Fig. 5 is a circuit diagram of simulation before CP charge-discharge transient.
Fig. 6.1 is a simulation waveform diagram of the CP charging process.
Fig. 6.2 is a simulation waveform diagram of the CP discharge process.
FIG. 7 is a waveform of CP discharge at 1.4 mA.
Fig. 8 is a waveform diagram of CP current under 150ps narrow pulse.
Fig. 9.1 simulation conditions: and the PFD _ CP output characteristic curve at TT/27 ℃.
Fig. 9.2 simulation conditions: PFD _ CP output characteristic at SS/125 ℃.
Fig. 9.3 simulation conditions: and the PFD _ CP output characteristic curve at FF/-55 ℃.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
Example 1:
as shown in fig. 2, a novel current-steering charge pump circuit includes a unity gain follower OPA1, an error amplifier OPA2, an NMOS transistor M1, an NMOS transistor M3, NMOS transistors M9-M12, a PMOS transistor M2, a PMOS transistor M13, and PMOS transistors M4-M8;
the positive input end of the unit gain follower OPA1 is respectively connected with the drain of an NMOS tube M3, the drain of a PMOS tube M4 and the positive input end of an error amplifier OPA2 through nodes, the negative input end of the unit gain follower OPA1 is connected with the output end, the output end of the unit gain follower OPA1 is respectively connected with the drain of an NMOS tube M1 and the drain of a PMOS tube M2 through nodes, the source of the NMOS tube M3 is connected with the source of an NMOS tube M1 and then commonly connected with the drain of the NMOS tube M10, the source of the PMOS tube M4 is connected with the source of the PMOS tube M2 and then commonly connected with the drain of the PMOS tube M7, and the gates of the NMOS tube M3, the NMOS tube M1, the PMOS tube M4 and the PMOS tube M2 are all vacant; the positive electrode input end of the unit gain follower OPA1 and the drain electrode of the NMOS tube M3 are connected with a Vout output terminal through a node, the Vout output terminal is connected with one end of a capacitor through the node, and the other end of the capacitor is grounded;
the negative electrode input end of the error amplifier OPA2 is respectively connected with the drain electrode of an NMOS tube M12 and the drain electrode of a PMOS tube M13 through nodes, the output end of the error amplifier OPA2 is respectively connected with the grid electrodes of a PMOS tube M7 and a PMOS tube M8 through nodes, the drain electrode of the PMOS tube M8 is connected with the source electrode of the PMOS tube M13, the grid electrode of the PMOS tube M13 is connected with a power supply VDD, and the source electrodes of the PMOS tubes M5-M8 and the grid electrode of the NMOS tube M12 are grounded;
the source electrode of the NMOS tube M12 is connected with the drain electrode of the NMOS tube M11, the grid electrode of the NMOS tube M11 is connected with the grid electrodes of the NMOS tube M9 and the NMOS tube M10, the source electrodes of the NMOS tube M9, the NMOS tube M10 and the NMOS tube M11 are connected with a power supply VDD in common, the drain electrode of the NMOS tube M9 is connected with the grid electrode of the NMOS tube M9 and the drain electrode of the PMOS tube M6 through nodes, the grid electrode of the PMOS tube M6 is connected with the grid electrode of the PMOS tube M5 and the drain electrode of the PMOS tube M5 through nodes, and the drain electrode of the PMOS tube M5 is connected with a current source.
The unity gain follower OPA1 and the error amplifier OPA2 each employ a rail-to-rail operational amplifier.
The NMOS transistor M3 is a charging switch, and the grid of the NMOS transistor M3 is used for connecting the digital signal UP of the PFD; the NMOS transistor M1 is a complementary switch of the charging switch, and the gate of the NMOS transistor M1 is used for connecting the digital signal UPN of the PFD.
The PMOS tube M4 is a discharge switch, and the grid electrode of the PMOS tube M4 is used for connecting a digital signal DW of the PFD; the PMOS transistor M2 is a complementary switch of the discharge switch, and the grid of the PMOS transistor M2 is used for connecting the digital signal DWN of the PFD.
In the invention, the principle is as follows:
(1) the unity gain follower OPA1 is introduced at the Vout and the X end, and is at the same potential with Vctrl under the action of the unity gain follower OPA1, so that the charge sharing effect is eliminated, and the voltage jump phenomenon is eliminated.
(2) An error operational amplifier OPA2 is introduced at the Vout end and the Y end, the grid voltage of an NMOS tube M7 and an NMOS tube M8 is adjusted through the error value of the Vout point and the Y point of a voltage output point, the disturbance of the output voltage to the charge and discharge current is reduced, the current precision is greatly improved, and the current mismatch is reduced.
(3) The unit gain follower OPA1 and the error operational amplifier OPA2 both adopt an operational amplifier structure of a rail, a pair of PMOS tubes and a pair of NMOS tubes are used as the input of the operational amplifier, when the input voltage is close to 0, the PMOS input pair tubes can normally work, and when the output voltage is close to VDD, the NMOS input pair tubes can normally work, so that the common-mode input voltage range of the operational amplifier reaches the full swing.
(4) In order to achieve current matching, the purpose is achieved by increasing the output impedance of the mirror current source.
(5) In order to improve the current matching degree of the charge pump, the channel length modulation effect is reduced by setting the channel length to be larger.
(6) The maximum charge-discharge current of the charge pump can reach 2.4mA, the stepping is 160uA, and 150ps of switching pulse can be switched on at the fastest speed.
The following is a summary of simulation results and performance of the charge pump circuit of the present invention:
1.1 OPA AC small signal pre-simulation
Simulations have shown that the OPA1 and OPA2 op amps input from 0 to 3.3V, and the gain of both op amps can be stabilized at 50db, as shown in fig. 3.1 and 3.2.
1.2 Charge Pump static Pre-match simulation
Firstly, the charge-discharge current matching of the charge pump is verified in a simulated manner according to fig. 4.1. As can be seen, the charge and discharge current switches are all set to be in an on state: the charging switch UP is grounded, the discharging switch DW is connected to be high, a direct-current voltage source is connected to the output voltage Vout end, the value of the voltage source is set as a variable Vout, and during simulation, the Vout is scanned from 0V to 3.3V in a stepping mode of 0.1V, and a previous simulation output result is obtained.
Fig. 4.2 shows the simulation result before the static matching curve of the charge pump under the conditions of 3.3V power supply voltage, TT process angle and temperature of 27 ℃, and it can be seen that the charge pump charge-discharge currents are basically matched within the output voltage range of 0.3V to 3V, and the required performance index is satisfied.
1.3 Charge Pump Charge-discharge Pre-transient simulation
The CP circuit is connected according to fig. 5, the circuit is pre-simulated under the conditions of 3.3V power supply voltage, TT process angle, and temperature of 27 ℃, switching pulses with frequency of 100M are input, and the obtained discharge simulation waveforms are shown in fig. 6.1 and fig. 6.2, wherein the periodic waveform is a current waveform, and the other waveform is a charge pump output voltage waveform, and it can be seen that the charge and discharge functions of the frequency charge pump are good.
1.4 CP Current Charge/discharge precision
The discharge current is set to be 1.4mA, the discharge current obtained through simulation is 1.4095mA, and the error is less than 1%, as shown in FIG. 7.
1.5 CP switching speed
At 200uA charging and discharging current, the switch can be opened to 150ps pulse narrow pulse current waveform, as shown in figure 8.
1.6 phase frequency detector and charge pump joint simulation
The phase discrimination range of the PFD is set to be 100MHz, the phase difference of two paths of input is set to be 10 degrees, the PFD and the CP are simulated in a joint mode, and the waveforms in simulation graphs 9.1, 9.2 and 9.3 represent the output voltage change of the CP.
It can be seen that CP can be normally charged and discharged under three simulation conditions of TT/27 ℃, SS/125 ℃ and FF/-55 ℃ when the phase discrimination frequency is 100 MHz.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be considered to be within the technical scope of the present invention, and the technical solutions and the inventive concepts thereof according to the present invention should be equivalent or changed within the scope of the present invention.

Claims (5)

1. The utility model provides a novel current rudder type charge pump circuit which characterized in that: the single-channel amplifier circuit comprises a unit gain follower OPA1, an error amplifier OPA2, an NMOS tube M1, an NMOS tube M3, NMOS tubes M9-M12, a PMOS tube M2, a PMOS tube M13 and PMOS tubes M4-M8;
the positive input end of the unit gain follower OPA1 is respectively connected with the drain of an NMOS tube M3, the drain of a PMOS tube M4 and the positive input end of an error amplifier OPA2 through nodes, the negative input end of the unit gain follower OPA1 is connected with the output end, the output end of the unit gain follower OPA1 is respectively connected with the drain of an NMOS tube M1 and the drain of a PMOS tube M2 through nodes, the source of the NMOS tube M3 is connected with the source of an NMOS tube M1 and then commonly connected with the drain of the NMOS tube M10, the source of the PMOS tube M4 is connected with the source of the PMOS tube M2 and then commonly connected with the drain of the PMOS tube M7, and the gates of the NMOS tube M3, the NMOS tube M1, the PMOS tube M4 and the PMOS tube M2 are all vacant; the positive input end of the unit gain follower OPA1 and the drain of the NMOS tube M3 are connected with a Vout output terminal through a node;
the negative electrode input end of the error amplifier OPA2 is respectively connected with the drain electrode of an NMOS tube M12 and the drain electrode of a PMOS tube M13 through nodes, the output end of the error amplifier OPA2 is respectively connected with the grid electrodes of a PMOS tube M7 and a PMOS tube M8 through nodes, the drain electrode of the PMOS tube M8 is connected with the source electrode of the PMOS tube M13, the grid electrode of the PMOS tube M13 is connected with a power supply VDD, and the source electrodes of the PMOS tubes M5-M8 and the grid electrode of the NMOS tube M12 are grounded;
the source electrode of the NMOS tube M12 is connected with the drain electrode of the NMOS tube M11, the grid electrode of the NMOS tube M11 is connected with the grid electrodes of the NMOS tube M9 and the NMOS tube M10, the source electrodes of the NMOS tube M9, the NMOS tube M10 and the NMOS tube M11 are connected with a power supply VDD in common, the drain electrode of the NMOS tube M9 is connected with the grid electrode of the NMOS tube M9 and the drain electrode of the PMOS tube M6 through nodes, the grid electrode of the PMOS tube M6 is connected with the grid electrode of the PMOS tube M5 and the drain electrode of the PMOS tube M5 through nodes, and the drain electrode of the PMOS tube M5 is connected with a current source.
2. The novel current-steering type charge pump circuit according to claim 1, characterized in that: the unity gain follower OPA1 and the error amplifier OPA2 both use rail-to-rail operational amplifiers.
3. The novel current-steering charge pump circuit according to claim 1, wherein said Vout output terminal is connected to one end of a capacitor via a node, and the other end of said capacitor is grounded.
4. The novel current steering type charge pump circuit as claimed in claim 1, wherein the NMOS transistor M3 is a charge switch, and the gate of the NMOS transistor M3 is used for connecting the digital signal UP of the PFD; the NMOS transistor M1 is a complementary switch of the charging switch, and the grid of the NMOS transistor M1 is used for connecting the digital signal UPN of the PFD.
5. The novel current steering type charge pump circuit according to claim 1, wherein the PMOS transistor M4 is a discharge switch, and the gate of the PMOS transistor M4 is used for connecting a digital signal DW of the PFD; the PMOS tube M2 is a complementary switch of the discharge switch, and the grid of the PMOS tube M2 is used for connecting the digital signal DWN of the PFD.
CN201911082627.5A 2019-11-07 2019-11-07 Novel current rudder type charge pump circuit Pending CN111082656A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201911082627.5A CN111082656A (en) 2019-11-07 2019-11-07 Novel current rudder type charge pump circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201911082627.5A CN111082656A (en) 2019-11-07 2019-11-07 Novel current rudder type charge pump circuit

Publications (1)

Publication Number Publication Date
CN111082656A true CN111082656A (en) 2020-04-28

Family

ID=70310947

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201911082627.5A Pending CN111082656A (en) 2019-11-07 2019-11-07 Novel current rudder type charge pump circuit

Country Status (1)

Country Link
CN (1) CN111082656A (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030042949A1 (en) * 2001-09-04 2003-03-06 Atheros Communications, Inc. Current-steering charge pump circuit and method of switching
US7977984B1 (en) * 2007-10-13 2011-07-12 Altera Corporation High-speed charge pump circuits
CN104811189A (en) * 2015-05-14 2015-07-29 东南大学 Charge pump circuit in charge pump phase-locked loop
CN105827107A (en) * 2016-05-12 2016-08-03 中国电子科技集团公司第二十四研究所 Circuit of charge pump
CN106936310A (en) * 2017-04-11 2017-07-07 东南大学 A kind of low-voltage current Self Matching gate switch charge pump

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030042949A1 (en) * 2001-09-04 2003-03-06 Atheros Communications, Inc. Current-steering charge pump circuit and method of switching
US7977984B1 (en) * 2007-10-13 2011-07-12 Altera Corporation High-speed charge pump circuits
CN104811189A (en) * 2015-05-14 2015-07-29 东南大学 Charge pump circuit in charge pump phase-locked loop
CN105827107A (en) * 2016-05-12 2016-08-03 中国电子科技集团公司第二十四研究所 Circuit of charge pump
CN106936310A (en) * 2017-04-11 2017-07-07 东南大学 A kind of low-voltage current Self Matching gate switch charge pump

Similar Documents

Publication Publication Date Title
US4987387A (en) Phase locked loop circuit with digital control
KR920004335B1 (en) Voltage controled oscillator
CN109194327B (en) Low-mismatch-rate charge pump circuit for delay-locked loop
US4752703A (en) Current source polarity switching circuit
CN102710124B (en) Charge pump circuit
CN103036422A (en) Charge pump circuit used for charge pump phase-locked loop
CN107534436B (en) Circuit and method for implementing charge/discharge switch in integrated circuit
JPH08130422A (en) Low voltage switching capacitance circuit using switching operational amplifier with maximum voltage swing
CN103780212A (en) Operational amplifiers, level switching circuit and programmable gain amplifier
CN112383304B (en) Charge pump phase-locked loop based on unipolar thin film transistor, chip and method
CN111181553A (en) Ring oscillator delay unit based on active inductive load
CN112165249B (en) Design method and application of charge pump circuit with wide output voltage range and low current mismatch
CN102664520A (en) Phase-locked loop charge pump circuit with low current mismatch
CN112468137A (en) Voltage controlled oscillator, phase-locked loop circuit and clock chip
US20080042722A1 (en) High speed level shifter circuit and circuit using same
CN202617095U (en) Phase locked loop charge pump circuit with low current mismatch
CN109936362B (en) Charge pump applied to frequency synthesizer
CN110504958B (en) Differential charge pump circuit with operational amplifier
CN109167599A (en) A kind of quick response charge pump circuit for phaselocked loop
CN117214514A (en) Zero-crossing detection circuit
CN103036423B (en) Charge pump circuit used for phase-locked loop
CN102739043B (en) Charge pump circuit
CN204928798U (en) Developments are filled discharge current and are matchd charge pump circuit
CN111082656A (en) Novel current rudder type charge pump circuit
CN217133616U (en) Band-gap reference voltage generating circuit

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20200428

RJ01 Rejection of invention patent application after publication