CN111048424B - Packaging method and packaging structure of three-dimensional heterogeneous AIP chip - Google Patents
Packaging method and packaging structure of three-dimensional heterogeneous AIP chip Download PDFInfo
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 62
- 238000000034 method Methods 0.000 title claims abstract description 41
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 69
- 229910021389 graphene Inorganic materials 0.000 claims abstract description 69
- 239000011248 coating agent Substances 0.000 claims abstract description 14
- 238000000576 coating method Methods 0.000 claims abstract description 14
- 238000000227 grinding Methods 0.000 claims abstract description 12
- 239000002390 adhesive tape Substances 0.000 claims abstract description 10
- 229910000679 solder Inorganic materials 0.000 claims abstract description 7
- 239000000853 adhesive Substances 0.000 claims abstract 3
- 230000001070 adhesive effect Effects 0.000 claims abstract 3
- 239000010410 layer Substances 0.000 claims description 184
- 238000007639 printing Methods 0.000 claims description 8
- 239000003292 glue Substances 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 238000007747 plating Methods 0.000 claims description 6
- 238000003825 pressing Methods 0.000 claims description 6
- 239000002356 single layer Substances 0.000 claims description 6
- 238000005507 spraying Methods 0.000 claims description 6
- 238000009713 electroplating Methods 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 claims description 3
- 238000004080 punching Methods 0.000 claims description 3
- 239000002052 molecular layer Substances 0.000 claims 1
- 230000017525 heat dissipation Effects 0.000 abstract description 7
- 238000004519 manufacturing process Methods 0.000 abstract 2
- 229910002804 graphite Inorganic materials 0.000 description 6
- 239000010439 graphite Substances 0.000 description 6
- -1 graphite alkene Chemical class 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
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- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6661—High-frequency adaptations for passive devices
- H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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Abstract
The invention provides a packaging method and a packaging structure of a three-dimensional heterogeneous AIP chip, wherein the packaging method comprises the following steps: pasting a grinding adhesive tape on the front side of the wafer, and grinding and thinning the back side of the wafer; carrying out scribing treatment on the wafer to form a millimeter wave chip; pasting the millimeter wave chip on the temporary bonding adhesive, coating a first graphene layer on the upper surface of the millimeter wave chip, and coating a reflecting layer on the first graphene layer; plastically packaging the millimeter wave chip, the first graphene layer and the reflecting layer; forming a through hole in the first plastic package layer, and filling the through hole with Cu; manufacturing an upper circuit layer on the upper surface of the primary plastic package part; placing an IPD chip and an antenna layer on the upper line layer, coating a second graphene layer, and plastically packaging the upper line layer, the IPD chip, the antenna layer and the second graphene layer; and manufacturing a lower circuit layer on the lower surface of the secondary plastic package part, and planting solder balls on the lower circuit layer. The packaging method and the packaging structure of the three-dimensional heterogeneous AIP chip have good heat dissipation performance and stability.
Description
Technical Field
The invention relates to the technical field of fan-out type packaging, in particular to a packaging method and a packaging structure of a three-dimensional heterogeneous AIP chip.
Background
The package Antenna (AIP) is a technology for integrating an antenna and a chip in a package based on a package material and a process to realize a system-level wireless function. The AIP technology conforms to the trend of improving the integration level of a silicon-based semiconductor process, and provides a good antenna and packaging solution for a system-level wireless chip. According to the authoritative market analysis report, the AIP technology is a necessary technology for millimeter wave 5G communication and automotive radar chips, and therefore, the AIP technology is increasingly gaining attention in the industry.
The heat dissipation performance of the AIP is an important item, and it directly affects the performance and stability of the AIP. The heat dissipation of the common AIP is generally to transfer heat through a molding compound and then to conduct the heat to the outside, however, the heat dissipation method is not efficient, and heat is easily accumulated after the chip works for a long time, which leads to performance degradation or damage after the temperature of the AIP is raised.
Disclosure of Invention
The invention provides a packaging method and a packaging structure of a three-dimensional heterogeneous AIP chip, which can effectively improve the heat dissipation performance and stability of a three-dimensional heterogeneous packaged antenna chip.
The technical scheme adopted by the invention is as follows: a packaging method of a three-dimensional heterogeneous AIP chip comprises the following steps:
the method comprises the following steps: pasting a grinding adhesive tape on the front side of the wafer, and then grinding and thinning the back side of the wafer;
step two: scribing the wafer, namely removing the grinding adhesive tape, then sticking a scribing adhesive tape on the back surface of the wafer, and scribing the wafer to form a millimeter wave chip;
step three: providing a carrier plate pasted with temporary bonding glue, pasting the millimeter wave chip on the temporary bonding glue, printing a first graphene layer on the upper surface of the millimeter wave chip, and coating a reflecting layer on the first graphene layer; then, carrying out plastic package on the millimeter wave chip, the first graphene layer and the reflecting layer, and grinding the formed first plastic package layer after the plastic package is finished to form a primary plastic package part;
step four: coating a first dielectric layer on the first plastic packaging layer, then punching the first plastic packaging layer to form a through hole, and filling the through hole with Cu by adopting an electroplating method; sequentially plating Ti and Cu on the upper surface of the primary plastic package part by adopting a metal deposition method to form a first seed layer, and then exposing and developing the first seed layer by adopting an etching method to form an upper circuit layer;
step five: placing an IPD chip on the upper line layer, laying an antenna layer, printing a second graphene layer to cover the antenna layer and the upper line layer, and then carrying out plastic package on the upper line layer, the IPD chip, the antenna layer and the second graphene layer to form a secondary plastic package part;
step six: removing the temporary bonding glue, turning the secondary plastic packaging part up and down, laying a second dielectric layer on the lower surface of the secondary plastic packaging part, and then plating Ti and Cu in sequence to form a second seed layer; then, the second seed layer is exposed and developed by adopting an etching method to form a lower circuit layer; and planting solder balls on the lower circuit layer to complete the packaging of the AIP chip.
Further, in the third step, the coating mode of the first graphene layer is printing, spraying or mechanical pressing.
Further, in the third step, the first graphene layer is a structure in which single-layer or multi-layer graphene molecule layers are arranged.
Further, in the third step, the thickness of the first graphene layer is 0.1nm to 1000 nm.
Further, in the third step, the first graphene layer is graphene paste, and the thickness is 1000 nm-10 mm.
Further, in the fifth step, the second graphene layer is a structure in which single-layer or multi-layer graphene molecular layers are arranged, and the thickness is 0.1nm to 1000 nm.
Further, in the fifth step, the coating mode of the second graphene layer is printing, spraying or mechanical pressing.
Further, in the fifth step, the second graphene layer is graphene paste, and the thickness of the second graphene layer is 1000 nm-10 mm.
The invention further provides the following technical scheme: a three-dimensional heterogeneous AIP chip packaging structure is characterized by being manufactured by the packaging method.
The invention also provides the following technical scheme: a three-dimensional heterogeneous AIP chip package structure, comprising: the millimeter wave chip is characterized in that a first graphene layer and a reflecting layer are sequentially formed on the upper surface of the millimeter wave chip; a first plastic packaging layer is plastic-packaged outside the millimeter wave chip, the first graphene layer and the reflecting layer, a through hole is formed in the first plastic packaging layer, Cu is filled in the through hole to form a connecting column, the upper end of the connecting column is connected with an upper circuit layer, and the lower end of the connecting column is connected with a lower circuit layer; the upper circuit layer is connected with an IPD chip, and the lower circuit layer is connected with a solder ball;
an antenna layer and a second graphene layer are arranged on the upper surface of the first plastic packaging layer, and the second graphene layer is coated outside the antenna layer and the upper circuit layer; the IPD chip, the antenna layer, the upper circuit layer and the second graphene layer are coated with a second plastic packaging layer.
Compared with the prior art, the packaging method and the packaging structure of the three-dimensional heterogeneous AIP chip have the advantages that the first graphene layer is printed on the upper surface of the millimeter wave chip, and the second graphene layer is printed on the upper circuit layer to cover the antenna layer and the upper circuit layer, so that the heat dissipation performance of the AIP chip is effectively improved, and the stability of the AIP chip is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings, there is shown in the drawings,
FIG. 1: the invention relates to a step flow chart of a packaging method of a three-dimensional heterogeneous AIP chip;
FIG. 2: the invention discloses a step schematic diagram of a packaging method of a three-dimensional heterogeneous AIP chip;
FIG. 3: the invention discloses a schematic diagram of a three-dimensional heterogeneous AIP chip packaging structure.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.
As shown in fig. 1 to 3, the method for packaging a three-dimensional heterogeneous AIP chip of the present invention includes the following steps:
the method comprises the following steps: and adhering a grinding adhesive tape on the front side of the wafer, and then grinding and thinning the back side of the wafer by adopting wafer thinning equipment.
Step two: and scribing the wafer, namely removing the grinding adhesive tape, then sticking a scribing adhesive tape on the back surface of the wafer, and scribing the wafer by adopting laser wafer scribing equipment or blade scribing equipment to form the millimeter wave chip 1. In this step, when the laser wafer scribing apparatus is used, the wafer needs to be subjected to wafer expansion processing.
Step three: the utility model provides a support plate 3 that pastes temporary bonding glue 2, examine millimeter wave chip 1, adopt the chip mounter to paste qualified millimeter wave chip 1 on temporary bonding glue 2, first graphite alkene layer 4 is coated on millimeter wave chip 1's upper surface, scribble reflection stratum 5 on first graphite alkene layer 4, then to millimeter wave chip 1, plastic envelope is carried out on first graphite alkene layer 4 and reflection stratum 5, grind first plastic envelope layer 6 that forms after the plastic envelope is accomplished, make its flatness reach the predetermined scope, form once plastic envelope spare.
In this step, the first graphene layer 4 may be coated by, but not limited to, printing, spraying, or mechanical pressing. The first graphene layer 4 has a structure in which single-layer or multi-layer graphene molecule layers are arranged, and the thickness of the first graphene layer 4 is 0.1nm to 1000nm, preferably 3 nm. The first graphene layer 4 may also be graphene paste, with a thickness of 1000nm to 10 mm. The first molding layer 6 is slightly higher than the reflective layer 5.
Step four: coating a first dielectric layer 7 on the first plastic packaging layer 6, then punching the first plastic packaging layer 6 to form a through hole 8, and filling the through hole 8 with Cu by adopting an electroplating method; and sequentially plating Ti and Cu on the upper surface of the primary plastic package part by adopting a metal deposition method to form a first seed layer, and then exposing and developing the first seed layer by adopting an etching method to form an upper circuit layer 9 (an upper RDL layer).
Step five: placing an IPD chip 10 on the upper line layer 9, laying an antenna layer 11, coating a second graphene layer 12 to cover the antenna layer 11 and the upper line layer 9, then plastically packaging the upper line layer 9, the IPD chip 10, the antenna layer 11 and the second graphene layer 12, and coating a formed second plastic package layer 15 outside the upper line layer 9, the IPD chip 10, the antenna layer 11 and the second graphene layer 12 to form a secondary plastic package.
In this step, the second graphene layer 12 may be coated by, but not limited to, printing, spraying, or mechanical pressing. The second graphene layer 12 has a structure in which single-layer or multi-layer graphene molecule layers are arranged, and the thickness of the second graphene layer 12 is 0.1nm to 1000nm, preferably 3 nm. The second graphene layer 12 may also be graphene paste, with a thickness of 1000nm to 10 mm.
Step six: removing the temporary bonding glue 2, turning the secondary plastic packaging part up and down (inverting), laying a second dielectric layer on the lower surface of the secondary plastic packaging part, and then plating Ti and Cu in sequence to form a second seed layer; then, the second seed layer is exposed and developed by adopting an etching method to form a lower circuit layer 13 (a lower RDL layer); and planting solder balls 14 on the lower circuit layer 13 to complete the packaging of the AIP chip.
The three-dimensional heterogeneous AIP chip packaging structure comprises a millimeter wave chip 1, wherein a first graphene layer 4 and a reflecting layer 5 are sequentially formed on the upper surface of the millimeter wave chip 1. Millimeter wave chip 1, first graphite alkene layer 4 and 5 outer plastic envelope of reflection stratum have first plastic envelope layer 6, and through-hole 8 has been seted up on first plastic envelope layer 6, and through-hole 8 intussuseption is full of Cu, forms the spliced pole, and the upper end of spliced pole is connected with upper line layer 9, and the lower extreme is connected with lower line layer 13. Further, the upper wiring layer 9 is connected to the IPD chip 10, and the lower wiring layer 13 is connected to the solder ball 14.
Further, the upper surface of first plastic envelope layer 6 is equipped with antenna layer 11 and second graphite alkene layer 12, and second graphite alkene layer 12 cladding is outside antenna layer 11 and the 9 layers of last circuit. In addition, the IPD chip 10, the antenna layer 11, the upper line layer 9 and the second graphene layer 12 are coated with a second plastic package layer 15.
In summary, according to the packaging method and the packaging structure of the three-dimensional heterogeneous AIP chip of the present invention, the first graphene layer 4 is coated on the upper surface of the millimeter wave chip 1, and the second graphene layer 12 is coated on the upper circuit layer 9 to cover the antenna layer 11 and the upper circuit layer 9, so as to effectively improve the heat dissipation performance of the AIP chip and improve the stability of the AIP chip.
Any combination of the various embodiments of the present invention should be considered as disclosed in the present invention, unless the inventive concept is contrary to the present invention; within the scope of the technical idea of the invention, any combination of various simple modifications and different embodiments of the technical solution without departing from the inventive idea of the present invention shall fall within the protection scope of the present invention.
Claims (10)
1. A packaging method of a three-dimensional heterogeneous AIP chip is characterized by comprising the following steps:
the method comprises the following steps: pasting a grinding adhesive tape on the front side of the wafer, and then grinding and thinning the back side of the wafer;
step two: scribing the wafer, namely removing the grinding adhesive tape, then sticking a scribing adhesive tape on the back surface of the wafer, and scribing the wafer to form a millimeter wave chip (1);
step three: providing a carrier plate (3) pasted with a temporary bonding adhesive (2), pasting the millimeter wave chip (1) on the temporary bonding adhesive (2), coating a first graphene layer (4) on the upper surface of the millimeter wave chip (1), and coating a reflecting layer (5) on the first graphene layer (4); then, the millimeter wave chip (1), the first graphene layer (4) and the reflecting layer (5) are subjected to plastic packaging, and a formed first plastic packaging layer (6) is ground after the plastic packaging is finished to form a primary plastic packaging part;
step four: coating a first dielectric layer (7) on the first plastic packaging layer (6), then punching the first plastic packaging layer (6) to form a through hole (8), and filling the through hole (8) with Cu by adopting an electroplating method; sequentially plating Ti and Cu on the upper surface of the primary plastic package part by adopting a metal deposition method to form a first seed layer, and then exposing and developing the first seed layer by adopting an etching method to form an upper circuit layer (9);
step five: placing an IPD chip (10) on the upper line layer (9), laying an antenna layer (11), coating a second graphene layer (12) to cover the antenna layer (11) and the upper line layer (9), and then plastically packaging the upper line layer (9), the IPD chip (10), the antenna layer (11) and the second graphene layer (12) to form a secondary plastic packaging part;
step six: removing the temporary bonding glue (2), turning the secondary plastic packaging part up and down, laying a second dielectric layer on the lower surface of the secondary plastic packaging part, and then plating Ti and Cu in sequence to form a second seed layer; then, the second seed layer is exposed and developed by adopting an etching method to form a lower circuit layer (13); and (3) implanting solder balls (14) on the lower circuit layer (13) to complete the packaging of the AIP chip.
2. The method for encapsulating the three-dimensional heterogeneous AIP chip as claimed in claim 1, wherein: in the third step, the first graphene layer (4) is coated by printing, spraying or mechanical pressing.
3. The method for encapsulating the three-dimensional heterogeneous AIP chip as claimed in claim 1, wherein: in the third step, the first graphene layer (4) is a structure with single-layer or multi-layer graphene molecule layers arranged.
4. The method for encapsulating the three-dimensional heterogeneous AIP chip as claimed in claim 1, wherein: in the third step, the thickness of the first graphene layer (4) is 0.1 nm-1000 nm.
5. The method for encapsulating the three-dimensional heterogeneous AIP chip as claimed in claim 1, wherein: in the third step, the first graphene layer (4) is graphene paste with the thickness of 1000 nm-10 mm.
6. The method for encapsulating the three-dimensional heterogeneous AIP chip as claimed in claim 1, wherein: in the fifth step, the second graphene layer (12) is of a structure with single-layer or multi-layer graphene molecular layer arrangement, and the thickness is 0.1 nm-1000 nm.
7. The method for encapsulating the three-dimensional heterogeneous AIP chip as claimed in claim 1, wherein: in the fifth step, the second graphene layer (12) is coated by printing, spraying or mechanical pressing.
8. The method for encapsulating the three-dimensional heterogeneous AIP chip as claimed in claim 1, wherein: in the fifth step, the second graphene layer (12) is graphene paste with the thickness of 1000 nm-10 mm.
9. A three-dimensional heterogeneous AIP chip package structure fabricated by the packaging method of any one of claims 2 to 8.
10. A three-dimensional heterogeneous AIP chip packaging structure is characterized by comprising: the millimeter wave chip comprises a millimeter wave chip (1), wherein a first graphene layer (4) and a reflecting layer (5) are sequentially formed on the upper surface of the millimeter wave chip (1); a first plastic packaging layer (6) is plastically packaged outside the millimeter wave chip (1), the first graphene layer (4) and the reflecting layer (5), a through hole (8) is formed in the first plastic packaging layer (6), Cu is filled in the through hole (8) to form a connecting column, the upper end of the connecting column is connected with an upper circuit layer (9), and the lower end of the connecting column is connected with a lower circuit layer (13); the upper circuit layer (9) is connected with an IPD chip (10), and the lower circuit layer (13) is connected with a solder ball (14);
an antenna layer (11) and a second graphene layer (12) are arranged on the upper surface of the first plastic packaging layer (6), and the second graphene layer (12) covers the antenna layer (11) and the upper circuit layer (9); the IPD chip (10), the antenna layer (11), the upper circuit layer (9) and the second graphene layer (12) are coated with a second plastic packaging layer (15) in an outer wrapping mode.
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| CN201911043037.1A CN111048424B (en) | 2019-10-30 | 2019-10-30 | Packaging method and packaging structure of three-dimensional heterogeneous AIP chip |
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| US8648454B2 (en) * | 2012-02-14 | 2014-02-11 | International Business Machines Corporation | Wafer-scale package structures with integrated antennas |
| US10083923B2 (en) * | 2015-09-21 | 2018-09-25 | Intel Corporation | Platform with thermally stable wireless interconnects |
| US10756033B2 (en) * | 2016-06-03 | 2020-08-25 | Intel IP Corporation | Wireless module with antenna package and cap package |
| CN108631051B (en) * | 2017-03-21 | 2022-09-02 | 中兴通讯股份有限公司 | Antenna structure, intelligent terminal device and manufacturing method of antenna structure |
| CN107910311B (en) * | 2017-12-04 | 2024-06-14 | 盛合晶微半导体(江阴)有限公司 | Fan-out type antenna packaging structure and preparation method thereof |
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