CN110943756A - Parallel SPI bus-based line matrix type wave control system data transmission method - Google Patents
Parallel SPI bus-based line matrix type wave control system data transmission method Download PDFInfo
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- CN110943756A CN110943756A CN201911008814.9A CN201911008814A CN110943756A CN 110943756 A CN110943756 A CN 110943756A CN 201911008814 A CN201911008814 A CN 201911008814A CN 110943756 A CN110943756 A CN 110943756A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
- H04B1/401—Circuits for selecting or indicating operating mode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/27—Adaptation for use in or on movable bodies
- H01Q1/28—Adaptation for use in or on aircraft, missiles, satellites, or balloons
- H01Q1/288—Satellite antennas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q21/00—Antenna arrays or systems
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q3/00—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system
- H01Q3/26—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture
- H01Q3/30—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture varying the relative phase between the radiating elements of an array
- H01Q3/34—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture varying the relative phase between the radiating elements of an array by electrical means
Abstract
A row matrix type wave control system data transmission method based on a parallel SPI bus uses an n-channel parallel SPI bus and a time-sharing m-group working mode, wherein m paths of clock signals are grouped signals, n paths of data pass through m groups of group signals, a phase shifter and/or an attenuator of an m multiplied by n paths of radio frequency channels of a phased array antenna subarray are controlled through time-sharing operation, k paths of latch signals are used for carrying out area latch control, m multiplied by n paths of control data are latched every time, the k paths of latch can complete latch of (m multiplied by n) multiplied by k paths of control data of the radio frequency channels of phased array elements, and control of a large-scale array element phased array by using less control signals is achieved. The method can effectively control the data updating of the TR component of the phased array antenna, has optimal updating time/resource occupation ratio, and can be well applied to the application from the ultra-high-speed switching type phased array antenna which needs high data refreshing rate to the communication slow scanning phased array antenna which mainly aims at low resource utilization rate.
Description
Technical Field
The invention belongs to the field of wave control design of satellite phased array antennas, and relates to a data transmission method of a satellite-borne phased array antenna wave control system, which can effectively reduce the design complexity and the design difficulty of the phased array antenna wave control system.
Background
At present, because the number of array elements of a satellite-borne phased-array antenna is small, the conventional satellite-borne phased-array antenna wave control design mostly adopts SPI buses with the same number as the number of the array elements or directly controls phase shifters and (or) attenuators in radio frequency channels through lockable output parallel buses so as to realize the directional control of the phased-array antenna, and does not need to relate to complex matrix control of grouping distribution and row selection of the array elements.
In the searchable published documents, the study on driving control of the flexible display screen in the university of Wuhan engineering, Master academic thesis (2013, Huangdanxia) inquires about the fact that the line and column driving related discussion of the LCD driving in the flexible display screen is adopted, and the technical characteristics of the study are that the line and column gating driving is carried out on pixel points in the LCD by using driving voltage. The matrix gating TR component amplitude-phase based test method is technically characterized in that a matrix switch and a vector network analyzer are used for testing a phased array radio frequency channel, and the matrix gating principle is a method for gating the TR component through the matrix switch.
Both methods do not relate to the problem of positioning a radio frequency channel by using a matrix row and column principle and using a parallel grouping SPI bus for control, and cannot be used for grouping control data transmission of a phased array TR component.
Disclosure of Invention
The technical problem solved by the invention is as follows: the method comprises the steps of designing a matrix row-column gating mode, controlling grouped TR arrays to modify batch data, and completing data updating of the whole phased array in a mode that different groups of TR modules are injected in batches.
The technical solution of the invention is as follows: a line matrix type wave control system data transmission method based on a parallel SPI bus comprises the following steps:
(1) dividing a radio frequency channel of the phased array antenna into k sub-arrays by taking array surface rows and columns as a reference, wherein each sub-array is a matrix array element comprising n rows and m columns, and k, n and m are positive integers;
(2) in the phased array antenna wave control machine, according to the divided phased array antenna subarray matrix, a time-sharing parallel SPI bus is constructed by using an FPGA, output data signals of the time-sharing parallel SPI bus are n paths, and each path comprises a parallel-serial converter; the time-sharing clock signals of the time-sharing parallel SPI bus are m in number, the clock output control logic is set to output only one clock signal at a time, and therefore m multiplied by n paths of serial data of a single sub-array are output through the m clock signals;
(3) generating k paths of latching signals by using an FPGA (field programmable gate array) inside a phased array antenna wave control machine, wherein each path of latching signal corresponds to a sub-array of a phased array antenna, the latching output control logic is set to generate latching pulses by only one latching signal every time, the latching pulses are generated once every m clocks, and m multiplied by n paths of serial data corresponding to the sub-array of one phased array antenna are latched to the output end of a serial-parallel converter in a radio frequency channel;
(4) and after all the k paths of latching signals are latched once, all the k multiplied by m multiplied by n paths of latching serial data of the phased array antenna are obtained.
Preferably, m and n are not less than 4.
Preferably, n is an integer multiple of 2.
Preferably, m is 4, 5, 6, 7 or 8.
Preferably, the value of n is 4, 6 or 8.
Preferably, k is 1, 2, 3, 4, 5, 6, 7 or 8.
Preferably, the parallel-to-serial converter is 24 bits.
Compared with the prior art, the invention has the advantages that:
1. the method of the invention uses n-channel parallel SPI bus to output control data, reduces the scale of control SPI bus, reduces the common (m multiplied by n) multiplied by k bus into n bus, and reduces the design difficulty of wave control system;
2. the method uses m groups of packet clocks to form time-sharing output of control data, reduces the number of the SPI buses by m times, and improves the utilization rate of SPI bus data signals;
3. the method uses the regional latch to control the data input, forms time-sharing three-dimensional latch of each path of radio frequency channel data, and further improves the utilization rate of SPI bus data and clock signals.
Through practical verification, the method can effectively control the data updating of the TR component of the phased array antenna, has the optimal updating time/resource occupation ratio, is an excellent phased array antenna wave control solution, and can be well suitable for the application from the ultra-high speed switching type phased array antenna which needs high data refreshing rate to the communication slow scanning phased array antenna which mainly aims at low resource utilization rate.
Drawings
FIG. 1 is a schematic block diagram of an exemplary 512-array phased array design according to the present invention;
FIG. 2 is a schematic timing diagram of an 8-way time-sharing 8-channel parallel SPI bus according to the present invention;
FIG. 3 is a flow chart of control data distribution of the 512-array phased array wave control system according to the present invention;
FIG. 4 is a schematic diagram of the hardware configuration of an 8-way time-sharing 8-channel parallel SPI bus according to the present invention;
FIG. 5 is an overall flow chart of the method of the present invention.
Detailed Description
The biggest difference from the conventional wave control system design is that the invention adopts a matrix type time-sharing point-by-point scanning method, can greatly reduce the connecting lines inside the phased array antenna while controlling each TR component, and effectively reduces the electrical design difficulty of the wave control machine by adopting a standardized row-column structural form.
The realization principle is as follows:
the FPGA is used for constructing m groups of parallel n paths of SPI time-sharing buses for time sharing to distribute data, k paths of latching signals are used for carrying out regional control latching, the control of the radio frequency channels of the phased array antenna with the maximum (mxn) xk units is realized, the controllable channel number is allowed to be larger than the channel number which needs to be actually controlled, and certain control redundancy is formed.
The bus for data transmission of the phased array antenna wave control system is an SPI bus, the bus form is a time-sharing parallel bus form, and the m groups of parallel n paths of SPI time-sharing buses are formed as follows: the data signal of the time-sharing parallel SPI bus is n paths, each path of data signal is composed of a 24-bit parallel-serial converter, and 24-bit serial data is output by a primary clock; the total number of the clock signals of the time-sharing parallel SPI bus is m, and only one clock signal generates output each time by setting a clock output control logic to drive n paths of 24-bit serial data to be output.
Fig. 1 shows a design schematic diagram taking 512 array elements as an example, taking 512 array elements as an example to construct a row-column matrix and perform partition latching, where the 512 array elements can be decomposed into a row-column matrix partition control mode of 8 × 8 × 8, that is, an antenna array element is divided into 8 sub-arrays with 64 array elements as one sub-array, each sub-array constructs a control area data input of one phased array antenna sub-array with 8 parallel SPI bus data signals (DAT 1-DAT 8) and 8 SPI bus clock signals (CLK 1-CLK 8) output in a time-sharing manner, and the latching signals (log 1-log 8) are used for performing area data input latching on each phased array antenna sub-array.
The usage principle of the k-path latch signals for phased array antenna beam switching is that after a clock signal finishes outputting from 1 to m groups, one path of the k-path latch signals latches to generate a latch pulse, m × n paths of data are latched to a serial-parallel converter of a radio frequency module, then the clock signal is output from 1 to m groups again to generate data input of a second area, after m paths of clocks finish outputting in sequence and data input is finished, a second path of latch pulse is generated to latch the data of the second area, and the data input latching of all areas is finished after the k-path latch signals are all output once in sequence in a circulating manner, wherein the specific principle of the data input latching is shown in fig. 2, and the flow is shown in fig. 3. The design of a subarray time-sharing parallel SPI bus of m rows and n columns takes the design of a time-sharing SPI parallel bus of a 64-array subarray as an example, the 64-array subarray can be designed into an 8 x 8 matrix form, 8 paths of SPI bus clock signals (CLK 1-CLK 8) output in a time-sharing mode are taken as rows and 8 paths of SPI bus clock signals (DAT 1-DAT 8) output in a time-sharing mode to form subarray control data input control logic, a wave control module generates 8 groups of control data, each group of control data selects one path of clock signal to output, and each CLK signal is responsible for loading 8 paths of data into a corresponding radio frequency channel in a time-sharing operation mode.
When the column matrix and row matrix are designed in a partition latching mode, m, n and k are selected as the same number as possible to construct wave control data control, and when m, n and k are not completely equal, m and n can be selected to be equal firstly. Firstly, dividing a phased array antenna into k sub-arrays, wherein the power value of each sub-array is the best when the size of each sub-array is 2, the size of each sub-array is 16-64 array elements, and m and n are larger than 4; after the size of the subarray is determined, row and column design of the subarray is carried out, rows are formed by data signals (DAT) of the SPI bus, columns of the subarray are formed by time-sharing clock signals (CLK) of the SPI bus, the design of row data m is preferably multiple of 2, and the product of the rows m and the columns n is required to be larger than or equal to the number of elements of the subarray.
As shown in fig. 4, 8 24-bit parallel-to-serial converters are designed inside the FPGA, clocks of the parallel-to-serial converters are obtained by frequency division of an input clock of the FPGA, a frequency division ratio can be set through the outside, and an output port of the clock is controlled by a controllable splitter.
The overall process flow of the present invention is shown in fig. 5.
Those skilled in the art will appreciate that those matters not described in detail in the present specification are well known in the art.
Claims (7)
1. A line matrix type wave control system data transmission method based on a parallel SPI bus is characterized by comprising the following steps:
(1) dividing a radio frequency channel of the phased array antenna into k sub-arrays by taking array surface rows and columns as a reference, wherein each sub-array is a matrix array element comprising n rows and m columns, and k, n and m are positive integers;
(2) in the phased array antenna wave control machine, according to the divided phased array antenna subarray matrix, a time-sharing parallel SPI bus is constructed by using an FPGA, output data signals of the time-sharing parallel SPI bus are n paths, and each path comprises a parallel-serial converter; the time-sharing clock signals of the time-sharing parallel SPI bus are m in number, the clock output control logic is set to output only one clock signal at a time, and therefore m multiplied by n paths of serial data of a single sub-array are output through the m clock signals;
(3) generating k paths of latching signals by using an FPGA (field programmable gate array) inside a phased array antenna wave control machine, wherein each path of latching signal corresponds to a sub-array of a phased array antenna, the latching output control logic is set to generate latching pulses by only one latching signal every time, the latching pulses are generated once every m clocks, and m multiplied by n paths of serial data corresponding to the sub-array of one phased array antenna are latched to the output end of a serial-parallel converter in a radio frequency channel;
(4) and after all the k paths of latching signals are latched once, all the k multiplied by m multiplied by n paths of latching serial data of the phased array antenna are obtained.
2. The method according to claim 1, wherein the method comprises the following steps: and both m and n are not less than 4.
3. The method for transmitting data in a row-column matrix wave control system based on the parallel SPI bus according to claim 1 or 2, characterized in that: and n is an integral multiple of 2.
4. The method according to claim 3, wherein the method comprises the following steps: the value of m is 4, 5, 6, 7 or 8.
5. The method according to claim 3, wherein the method comprises the following steps: the value of n is 4, 6 or 8.
6. The method according to claim 3, wherein the method comprises the following steps: the value of k is 1, 2, 3, 4, 5, 6, 7 or 8.
7. The method for transmitting data in a row-column matrix wave control system based on the parallel SPI bus according to claim 1 or 2, characterized in that: the parallel-serial converter is 24 bits.
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Patent Citations (8)
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|---|---|---|---|---|
| CN1767048A (en) * | 2004-09-30 | 2006-05-03 | 三洋电机株式会社 | Latch clock generation circuit and serial-parallel conversion circuit |
| US20090129456A1 (en) * | 2007-11-21 | 2009-05-21 | Tetsuhiko Miyatani | Receiver with multiple antennas and method of receiving signals |
| CN101599930A (en) * | 2009-07-23 | 2009-12-09 | 西安空间无线电技术研究所 | High-speed parallel equalizer and equalization methods |
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