CN110808629A

CN110808629A - Dual-power switching circuit and dual-power switching controller

Info

Publication number: CN110808629A
Application number: CN201910979373.0A
Authority: CN
Inventors: 彭勃; 徐小军
Original assignee: Hefei Lianbao Information Technology Co Ltd
Current assignee: Hefei Lianbao Information Technology Co Ltd
Priority date: 2019-10-15
Filing date: 2019-10-15
Publication date: 2020-02-18
Anticipated expiration: 2039-10-15
Also published as: CN110808629B

Abstract

The invention discloses a double-power switching circuit and a double-power switching controller, wherein the double-power switching circuit comprises: the first power transmission circuit comprises two MOS tubes which are mutually conductive and blocked, the input end of the first power transmission circuit is connected with the output end of the first power adapter, the first end of the voltage division threshold value circuit and the first end of the current backflow preventing circuit, and the output end of the first power transmission circuit is connected with the second end of the current backflow preventing circuit and the power supply end; the second end of the voltage division threshold circuit is connected with one end of the delay circuit, and the other end of the delay circuit is connected with the third end of the current backflow preventing circuit; the third end of the current backflow prevention circuit is connected with the first end of the dual-power supply interlocking circuit; the second end of the dual-power supply interlocking circuit is connected with the third end of the voltage division threshold value circuit, and the third end of the dual-power supply interlocking circuit is connected with the first end of the second power transmission circuit; the second end of the second power transmission circuit is connected with the output end of the second power adapter, and the third end of the second power transmission circuit is connected with the second end of the current-preventing reverse-charging circuit and the power supply end.

Description

Dual-power switching circuit and dual-power switching controller

Technical Field

The invention relates to the field of control, in particular to a dual-power switching circuit and a dual-power switching controller.

Background

At present, a notebook computer needs to adopt a traditional Standard Adapter (namely a Standard Adapter, a small round port or a small square port) and a Type C (namely a universal serial bus Adapter) dual-power supply mode, when switching or hot plugging, a more complex control method is adopted, namely an EC (embedded Controller) is mainly adopted to detect the access conditions of two sources (power supply sources), a resistor is adopted to divide voltage to detect the access voltages of the two sources for comparison, and then the two sources are respectively controlled to be switched according to the comparison result.

However, in the process of controlling the switching of the two sources, if the switching is unsuccessful, the current of the system is reversely poured, so that various adverse conditions occur, and the performance of the system is damaged.

Disclosure of Invention

In view of this, the embodiment of the present invention provides a dual power switching circuit and a dual power switching controller, so as to solve the following problems in the prior art: in the process of controlling the switching of the two sources, if the switching is unsuccessful, the current of the system is reversely poured, so that various adverse conditions occur, and the performance of the system is damaged.

In one aspect, an embodiment of the present invention provides a dual power switching circuit, including: the power supply comprises a first power transmission circuit, a voltage division threshold value circuit, a delay circuit, a current backflow prevention circuit, a double-power supply interlocking circuit and a second power transmission circuit; the first power transmission circuit comprises two MOS tubes which are mutually conductive and blocked, the input end of the first power transmission circuit is connected with the output end of the first power adapter, the first end of the voltage division threshold value circuit and the first end of the current reverse-charging prevention circuit, and the output end of the first power transmission circuit is connected with the second end of the current reverse-charging prevention circuit and the power supply end and is used for transmitting power from the first power adapter to the power supply end; the second end of the voltage division threshold circuit is connected with one end of the delay circuit, the other end of the delay circuit is connected with the third end of the current backflow prevention circuit, and the voltage division threshold circuit is used for dividing voltage of the first power transmission circuit; the third end of the current backflow prevention circuit is connected with the first end of the dual-power supply interlocking circuit, and the current backflow prevention circuit is used for inhibiting the power supply end from performing current backflow to the first power adapter or the second power adapter when the first power adapter and the second power adapter are switched; the second end of the dual-power-supply interlocking circuit is connected with the third end of the voltage division threshold value circuit, the third end of the dual-power-supply interlocking circuit is connected with the first end of the second power transmission circuit, and the dual-power-supply interlocking circuit is used for disconnecting a passage corresponding to one power adapter and conducting a passage corresponding to the other power adapter when the first power adapter and the second power adapter are switched; the second end of the second power transmission circuit is connected with the output end of the second power adapter, the third end of the second power transmission circuit is connected with the second end of the current backflow prevention circuit and the power supply end, and the second power transmission circuit is used for transmitting power from the second power adapter to the power supply end.

In some embodiments, the first power transfer circuit comprises: two PMOS tubes with interconnected drains; the source electrode of the first PMOS tube is connected with the output end of the first power adapter and the first end of the voltage division threshold value circuit, and the source electrode and the grid electrode of the first PMOS tube are both connected with the first end of the current backflow preventing circuit; the source electrode of the second PMOS tube is connected with the power supply end, and the source electrode and the grid electrode of the second PMOS tube are both connected with the second end of the current reverse-flowing prevention circuit.

In some embodiments, the current backflow prevention circuit comprises: the first NMOS transistor comprises a first capacitor, a second capacitor, a first resistor, a second resistor, a fourth resistor, a first diode, a second diode and a third NMOS transistor; one end of the first capacitor is connected with the source electrode of the first PMOS tube, and the other end of the first capacitor is connected with the anode of the first diode; one end of the first resistor is connected with the source electrode of the first PMOS tube, and the other end of the first resistor is connected with the anode of the first diode; the anode of the first diode is also connected with the grid of the first PMOS tube; one end of the second capacitor is connected with the source electrode of the second PMOS tube, and the other end of the second capacitor is connected with the anode of the second diode; one end of the second resistor is connected with the source electrode of the second PMOS tube, and the other end of the second resistor is connected with the anode of the second diode; the anode of the second diode is also connected with the grid electrode of the second PMOS tube; the negative electrode of the first diode and the negative electrode of the second diode are both connected with one end of a fourth resistor, the other end of the fourth resistor is connected with the drain electrode of a third NMOS tube, the grid electrode of the third NMOS tube is connected with the other end of the delay circuit, and the source electrode of the third NMOS tube is grounded.

In some embodiments, the current backflow prevention circuit comprises: the first capacitor, the second capacitor, the first resistor, the second resistor, the fourth resistor, the ninth resistor, the third NMOS transistor and the seventh NMOS transistor; one end of the first capacitor is connected with the source electrode of the first PMOS tube, and the other end of the first capacitor is connected with one end of the fourth resistor; one end of the first resistor is connected with the source electrode of the first PMOS tube, and the other end of the first resistor is connected with one end of the fourth resistor; one end of the fourth resistor is also connected with the grid electrode of the first PMOS tube; one end of the second capacitor is connected with the source electrode of the second PMOS tube, and the other end of the second capacitor is connected with one end of the ninth resistor; one end of the second resistor is connected with the source electrode of the second PMOS tube, and the other end of the second resistor is connected with one end of the ninth resistor; one end of the ninth resistor is also connected with the grid electrode of the second PMOS tube; the other end of the fourth resistor is connected with the drain electrode of the third NMOS tube, the grid electrode of the third NMOS tube is connected with the other end of the delay circuit, and the source electrode of the third NMOS tube is grounded; the other end of the ninth resistor is connected with the drain electrode of the seventh NMOS tube, the grid electrode of the seventh NMOS tube is connected with the other end of the delay circuit, and the source electrode of the seventh NMOS tube is grounded.

In some embodiments, the voltage divider threshold circuit comprises: a third resistor, a sixth resistor and a third capacitor; one end of the third resistor is connected with the source electrode of the first PMOS tube, the other end of the third resistor is connected with one end of the sixth resistor and one end of the third capacitor, and the other end of the sixth resistor and the other end of the third capacitor are both grounded; the other end of the third resistor is also connected with the second end of the dual-power interlocking circuit and one end of the delay circuit.

In some embodiments, the delay circuit comprises: a fifth resistor and a fourth capacitor; one end of the fifth resistor is connected with the other end of the third resistor, and the other end of the fifth resistor is connected with one end of the fourth capacitor, the grid of the third NMOS tube and the second end of the dual-power interlocking circuit; the other end of the fourth capacitor is grounded.

In some embodiments, the dual power interlock circuit comprises: a fourth NMOS transistor and a sixth NMOS transistor; the drain electrode of the fourth NMOS tube is connected with the grid electrode of the third NMOS tube, the grid electrode of the fourth NMOS tube is connected with the drain electrode of the sixth NMOS tube, and the source electrode of the fourth NMOS tube is grounded; the drain electrode of the sixth NMOS tube is also connected with the first end of the second power transmission circuit, the grid electrode of the sixth NMOS tube is connected with the other end of the third resistor, and the source electrode of the sixth NMOS tube is grounded.

In some embodiments, the second power transfer circuit comprises: the seventh resistor, the power switch chip and the fifth NMOS tube; the first end of the power switch chip is connected with the output end of the second power adapter, the second end of the power switch chip is connected with the power supply end, the third end of the power switch chip is grounded, and the fourth end of the power switch chip is connected with one end of the seventh resistor and the drain electrode of the fifth NMOS tube; the grid electrode of the fifth NMOS tube is connected with the drain electrode of the sixth NMOS tube, and the source electrode of the fifth NMOS tube is grounded; the other end of the seventh resistor is connected with a fixed input voltage.

In some embodiments, further comprising: and one end of the eighth resistor is connected with the grid electrode of the fifth NMOS tube, and the other end of the eighth resistor is connected to the output end of the second power adapter.

On the other hand, an embodiment of the present invention provides a dual power supply switching controller, including: the dual power supply switching circuit of any embodiment of the invention.

The embodiment of the invention is provided with the current backflow prevention circuit, the circuit can be protected when two power adapters are switched, the problem of current backflow is prevented, in addition, when the circuit is designed, two MOS (metal oxide semiconductor) tubes which are mutually in conduction obstruction are arranged for the first power transmission circuit, the normal conduction of the first power transmission circuit is ensured through the voltage division threshold value circuit and the time delay circuit, in addition, the conduction is obstructed when the current backflow possibly exists, the first power transmission circuit and the current backflow prevention circuit ensure the switching process of two paths of source, no matter whether the switching can be successful or not, the system current backflow cannot be caused, and the system performance is stable.

Drawings

Fig. 1 is a schematic diagram of a dual power switching circuit according to a first embodiment of the invention;

fig. 2 is a first circuit diagram of a dual power switching circuit according to a first embodiment of the invention;

fig. 3 is a circuit diagram of a dual power switching circuit according to a first embodiment of the invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without any inventive step, are within the scope of protection of the invention.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

To maintain the following description of the embodiments of the present invention clear and concise, a detailed description of known functions and known components of the invention have been omitted.

A first embodiment of the present invention provides a dual power supply switching circuit, whose schematic structure is shown in fig. 1, including:

the circuit comprises a first power transmission circuit 1, a voltage division threshold value circuit 2, a delay circuit 3, a current backflow prevention circuit 4, a double-power-supply interlocking circuit 5 and a second power transmission circuit 6.

The first power transmission circuit 1 comprises two MOS tubes which are mutually conducted and blocked, the input end of the first power transmission circuit is connected with the output end of the first power adapter 7, the first end of the voltage division threshold value circuit 2 and the first end of the current reverse-filling prevention circuit 4, the output end of the first power transmission circuit is connected with the second end of the current reverse-filling prevention circuit 4 and the power supply end 8, and the first power transmission circuit is used for transmitting power from the first power adapter 7 to the power supply end 8; the second end of the voltage division threshold circuit 2 is connected with one end of the delay circuit 3, the other end of the delay circuit 3 is connected with the third end of the current backflow prevention circuit 4, and the voltage division threshold circuit 2 is used for dividing voltage of the first power transmission circuit 1; the third end of the current backflow prevention circuit 4 is connected with the first end of the dual-power supply interlocking circuit 5, and the current backflow prevention circuit 4 is used for inhibiting the power supply end from performing current backflow to the first power adapter 7 or the second power adapter 9 when the first power adapter 7 and the second power adapter 9 are switched; the second end of the dual-power-supply interlocking circuit 5 is connected with the third end of the voltage division threshold value circuit 2, the third end of the dual-power-supply interlocking circuit 5 is connected with the first end of the second power transmission circuit 6, and the dual-power-supply interlocking circuit 5 is used for disconnecting the passage corresponding to one power adapter and conducting the passage corresponding to the other power adapter when the first power adapter 7 and the second power adapter 9 are switched; the second end of the second power transmission circuit 6 is connected with the output end of the second power adapter 9, the third end of the second power transmission circuit 6 is connected with the second end of the current backflow prevention circuit 4 and the power supply end 8, and the second power transmission circuit 6 is used for transmitting power from the second power adapter 9 to the power supply end 8.

In the embodiment of the invention, the current backflow prevention circuit is arranged, the circuit can be protected when two power adapters are switched, the problem of current backflow is prevented, in addition, when the circuit is designed, two MOS (metal oxide semiconductor) tubes which are mutually in conduction obstruction are arranged for the first power transmission circuit, the normal conduction of the first power transmission circuit is ensured through the voltage division threshold value circuit and the time delay circuit, in addition, the conduction is obstructed when the current backflow possibly exists, the first power transmission circuit and the current backflow prevention circuit ensure that the system current backflow cannot be caused no matter whether the switching can be successfully carried out or not in the process of switching two paths of source, and the system performance is stable.

For the difference of the existing circuit design diagrams, there are many possible device combinations in the design of the circuit design diagrams, and there are also many design ways for the current backflow prevention circuit 4, and the embodiment of the present invention only schematically illustrates the circuit design diagrams with two circuit design diagrams, and those skilled in the art can design the circuit equally according to the requirements, and all of the design methods are within the scope covered by the embodiment of the present invention.

For the two circuit design diagrams of fig. 2 and fig. 3, the difference lies in the design of the current backflow prevention circuit 4, and a person skilled in the art may change the design according to the actual situation as long as the current backflow prevention effect can be achieved, which does not limit the embodiment of the present invention.

As shown in fig. 2, a specific circuit diagram of the dual power switching circuit is shown, and the size and type of each device are identified in the diagram for reference by those skilled in the art. Specific devices included in the respective circuits will be described below.

The first power transfer circuit includes: two PMOS tubes with interconnected drains; the source electrode of the first PMOS tube (PQ1) is connected with the output end of the first power adapter and the first end of the voltage division threshold value circuit, and the source electrode and the grid electrode of the first PMOS tube are both connected with the first end of the current backflow preventing circuit; the source electrode of the second PMOS tube (PQ2) is connected with the power supply end, and the source electrode and the grid electrode of the second PMOS tube are both connected with the second end of the current reverse-flowing prevention circuit.

The above-mentioned anti-current flows backward the circuit includes: the circuit comprises a first capacitor (PC1), a second capacitor (PC2), a first resistor (PR1), a second resistor (PR2), a fourth resistor (PR4), a first diode (PD1), a second diode (PD2) and a third NMOS tube (PQ 3).

One end of the first capacitor is connected with the source electrode of the first PMOS tube, and the other end of the first capacitor is connected with the anode of the first diode; one end of the first resistor is connected with the source electrode of the first PMOS tube, and the other end of the first resistor is connected with the anode of the first diode; the anode of the first diode is also connected with the grid of the first PMOS tube; one end of the second capacitor is connected with the source electrode of the second PMOS tube, and the other end of the second capacitor is connected with the anode of the second diode; one end of the second resistor is connected with the source electrode of the second PMOS tube, and the other end of the second resistor is connected with the anode of the second diode; the anode of the second diode is also connected with the grid electrode of the second PMOS tube; the negative electrode of the first diode and the negative electrode of the second diode are both connected with one end of a fourth resistor, the other end of the fourth resistor is connected with the drain electrode of a third NMOS tube, the grid electrode of the third NMOS tube is connected with the other end of the delay circuit, and the source electrode of the third NMOS tube is grounded.

The voltage division threshold circuit includes: a third resistor (PR3), a sixth resistor (PR6) and a third capacitor (PC 3); one end of the third resistor is connected with the source electrode of the first PMOS tube, the other end of the third resistor is connected with one end of the sixth resistor and one end of the third capacitor, and the other end of the sixth resistor and the other end of the third capacitor are both grounded; the other end of the third resistor is also connected with the second end of the dual-power interlocking circuit and one end of the delay circuit.

The delay circuit includes: a fifth resistor (PR5) and a fourth capacitor (PC 4); one end of the fifth resistor is connected with the other end of the third resistor, and the other end of the fifth resistor is connected with one end of the fourth capacitor, the grid of the third NMOS tube and the second end of the dual-power interlocking circuit; the other end of the fourth capacitor is grounded.

The dual power supply interlock circuit includes: a fourth NMOS transistor (PQ4) and a sixth NMOS transistor (PQ 6); the drain electrode of the fourth NMOS tube is connected with the grid electrode of the third NMOS tube, the grid electrode of the fourth NMOS tube is connected with the drain electrode of the sixth NMOS tube, and the source electrode of the fourth NMOS tube is grounded; the drain electrode of the sixth NMOS tube is also connected with the first end of the second power transmission circuit, the grid electrode of the sixth NMOS tube is connected with the other end of the third resistor, and the source electrode of the sixth NMOS tube is grounded.

The second power transmission circuit includes: a seventh resistor (PR7), a power switch chip (PU1) and a fifth NMOS transistor (PQ 5); the first end of the power switch chip is connected with the output end of the second power adapter, the second end of the power switch chip is connected with the power supply end, the third end of the power switch chip is grounded, and the fourth end of the power switch chip is connected with one end of the seventh resistor and the drain electrode of the fifth NMOS tube; the grid electrode of the fifth NMOS tube is connected with the drain electrode of the sixth NMOS tube, and the source electrode of the fifth NMOS tube is grounded; the other end of the seventh resistor is connected with a fixed input voltage.

The above-mentioned dual power supply switching circuit still includes: and one end of the eighth resistor (PR8) is connected with the grid electrode of the fifth NMOS tube, and the other end of the eighth resistor is connected to the output end of the second power adapter.

The principle of operation of the circuit shown in fig. 2 is as follows:

STANDARD ADAPTER represents a small round-mouth or a small square-mouth power supply, PQ1 and PQ2 are back-to-back PMOS as a traditional adapter power transmission route, PC1, PR1, PC2 and PR2 are RC combinations for controlling PQ1 and PQ2 soft start, PD1 and PD2 are reverse current prevention diodes, PR3, PR6 and PC3 are voltage division threshold circuits for controlling the adapter power transmission route to be opened, and PR5 and PC4 are delay time routes for adjusting the adapter power transmission route to be opened.

When STANDARD ADAPTER is switched IN, PQ3 is enabled to be conducted after PR3 and PR6 are used for voltage division and PR5 and PC4 are delayed, the S end and the G end of PQ1 are conducted through PR1, PD1, PR4 and PQ3 voltage division, the S end and the G end of PQ2 are conducted through PR2, PD2, PR4 and PQ3 voltage division, and STANDARD ADAPTER supplies power to CHARGER _ IN.

TYPE C ADAPTER represents a power supply supporting PDx protocol, PU1 is a TYPE C power switch chip with RCP (reverse current protection) function, PU1 is turned on, TYPE C ADAPTER supplies CHARGER _ IN when PD _ TYPE C _ EN # is H and ADAPTERIN is L and PD _ TYPE C _ EN # is L.

PQ4, PQ6 and ADAPTERIN, PD _ TYPE C _ EN # _ R signals form control STANDARD ADAPTER and TYPEC ADAPTER interlocking control, when ADAPTERIN is H, PQ6 locks PD _ TYPE C _ EN # _ R to be L, and when PD _ TYPE C _ EN # is H, TYPE C ADAPTER cannot be conducted, and only SANDARD ADAPTER supplies power to the system; when only TYPE CADAPTER is accessed, PD _ TYPE C _ EN # _ R is H, and PQ4 pulls ADAPTER _ EN L, STANDARD ADAPTER will not conduct, only TYPE C ADAPTER will supply power to the system.

When STANDARD ADAPTER supplies power to the system, the CHARGER _ IN will not flow back to TYPE C ADAPTER because PU1 has RCP function; when TYPE C ADAPTER powers the system, PQ2 and PD1 turn off IN reverse and CHARGER _ IN will not back-sink to STANDARD ADAPTER.

Fig. 3 shows another specific circuit diagram of the dual power switching circuit, in which the sizes and types of the devices are identified for reference by those skilled in the art. Specific devices included in the respective circuits will be described below.

The above-mentioned anti-current flows backward the circuit includes: the circuit comprises a first capacitor (PC1), a second capacitor (PC2), a first resistor (PR1), a second resistor (PR2), a fourth resistor (PR4), a ninth resistor (PR9), a third NMOS tube (PQ3) and a seventh NMOS tube (PQ 7).

One end of the first capacitor is connected with the source electrode of the first PMOS tube, and the other end of the first capacitor is connected with one end of the fourth resistor; one end of the first resistor is connected with the source electrode of the first PMOS tube, and the other end of the first resistor is connected with one end of the fourth resistor; one end of the fourth resistor is also connected with the grid electrode of the first PMOS tube; one end of the second capacitor is connected with the source electrode of the second PMOS tube, and the other end of the second capacitor is connected with one end of the ninth resistor; one end of the second resistor is connected with the source electrode of the second PMOS tube, and the other end of the second resistor is connected with one end of the ninth resistor; one end of the ninth resistor is also connected with the grid electrode of the second PMOS tube; the other end of the fourth resistor is connected with the drain electrode of the third NMOS tube, the grid electrode of the third NMOS tube is connected with the other end of the delay circuit, and the source electrode of the third NMOS tube is grounded; the other end of the ninth resistor is connected with the drain electrode of the seventh NMOS tube, the grid electrode of the seventh NMOS tube is connected with the other end of the delay circuit, and the source electrode of the seventh NMOS tube is grounded.

The principle of operation of the circuit shown in fig. 3 is as follows:

STANDARD ADAPTER represents a small round-mouth or a small square-mouth power supply, PQ1 and PQ2 are back-to-back PMOS as a traditional adapter power transmission route, PC1, PR1, PC2 and PR2 are RC combinations for controlling PQ1 and PQ2 soft start, PQ3 and PQ7 control PQ1 and PQ2 to be turned on and off, PR3, PR6 and PC3 are voltage division threshold lines for controlling the adapter power transmission line to be turned on, and PR5 and PC4 are delay time lines for adjusting the startup of the adapter power transmission line.

When STANDARD ADAPTER is switched IN, PQ3 and PQ7 are enabled to be conducted after PR3 and PR6 are used for voltage division and PR5 and PC4 are delayed, the S end and the G end of PQ1 are conducted through PR1, PQ3 and PR4 IN voltage division, the S end and the G end of PQ2 are conducted through PR2, PQ7 and PR9 IN voltage division, and STANDARD ADAPTER supplies power to CHARGER _ IN.

TYPE C ADAPTER represents a power supply supporting PDx protocol, PU1 is a TYPE C power switch chip with RCP function, when PD _ TYPE C _ IN is H and ADAPTERIN is L, and PD _ TYPE C _ EN # is L, PU1 is turned on, TYPE CADAPTER supplies electricity to CHARGER _ IN.

PQ4, PQ6 and ADAPTERIN, PD _ TYPE C _ EN # _ R signals form control STANDARD ADAPTER and TYPEC ADAPTER interlocking control, when ADAPTERIN is H, PQ6 locks PD _ TYPE C _ EN # _ R to be L, PD _ TYPE C _ EN # is H, TYPE C ADAPTER cannot be conducted, and only SANDARD ADAPTER supplies power to the system; when only TYPE CADAPTER is accessed, PD _ TYPE C _ EN # _ R is H, and PQ4 pulls ADAPTER _ EN L, STANDARD ADAPTER will not conduct, only TYPE C ADAPTER will supply power to the system.

When STANDARD ADAPTER supplies power to the system, the CHARGER _ IN will not flow back to TYPE C ADAPTER because PU1 has RCP function; when TYPE C ADAPTER powers the system, PQ2 and PQ7 turn off and CHARGER _ IN will not back-flow to STANDARD ADAPTER.

A second embodiment of the present invention further provides a dual power switching controller, where the controller includes the dual power switching circuit in the first embodiment, and the specific structure of the dual power switching circuit is the same as that in the first embodiment, and is not described herein again.

Moreover, although exemplary embodiments have been described herein, the scope thereof includes any and all embodiments based on the present invention with equivalent elements, modifications, omissions, combinations (e.g., of various embodiments across), adaptations or alterations. The elements of the claims are to be interpreted broadly based on the language employed in the claims and not limited to examples described in the present specification or during the prosecution of the application, which examples are to be construed as non-exclusive. It is intended, therefore, that the specification and examples be considered as exemplary only, with a true scope and spirit being indicated by the following claims and their full scope of equivalents.

The above description is intended to be illustrative and not restrictive. For example, the above-described examples (or one or more versions thereof) may be used in combination with each other. For example, other embodiments may be used by those of ordinary skill in the art upon reading the above description. In addition, in the above-described embodiments, various features may be grouped together to streamline the disclosure. This should not be interpreted as an intention that a disclosed feature not claimed is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the detailed description as examples or embodiments, with each claim standing on its own as a separate embodiment, and it is contemplated that these embodiments may be combined with each other in various combinations or permutations. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

While the embodiments of the present invention have been described in detail, the present invention is not limited to these specific embodiments, and those skilled in the art can make various modifications and modifications of the embodiments based on the concept of the present invention, which fall within the scope of the present invention as claimed.

Claims

1. A dual power switching circuit, comprising:

the power supply comprises a first power transmission circuit, a voltage division threshold value circuit, a delay circuit, a current backflow prevention circuit, a double-power supply interlocking circuit and a second power transmission circuit; wherein,

the first power transmission circuit comprises two MOS tubes which are mutually conductive and blocked, the input end of the first power transmission circuit is connected with the output end of the first power adapter, the first end of the voltage division threshold value circuit and the first end of the current backflow preventing circuit, and the output end of the first power transmission circuit is connected with the second end of the current backflow preventing circuit and the power supply end and is used for transmitting power from the first power adapter to the power supply end;

the second end of the voltage division threshold circuit is connected with one end of the delay circuit, the other end of the delay circuit is connected with the third end of the current backflow prevention circuit, and the voltage division threshold circuit is used for dividing voltage of the first power transmission circuit;

the third end of the current backflow prevention circuit is connected with the first end of the dual-power supply interlocking circuit, and the current backflow prevention circuit is used for inhibiting the power supply end from performing current backflow to the first power adapter or the second power adapter when the first power adapter and the second power adapter are switched;

the second end of the dual-power-supply interlocking circuit is connected with the third end of the voltage division threshold value circuit, the third end of the dual-power-supply interlocking circuit is connected with the first end of the second power transmission circuit, and the dual-power-supply interlocking circuit is used for disconnecting a passage corresponding to one power adapter and conducting a passage corresponding to the other power adapter when the first power adapter and the second power adapter are switched;

the second end of the second power transmission circuit is connected with the output end of the second power adapter, the third end of the second power transmission circuit is connected with the second end of the current backflow prevention circuit and the power supply end, and the second power transmission circuit is used for transmitting power from the second power adapter to the power supply end.

2. The dual power switching circuit of claim 1, wherein the first power transfer circuit comprises:

two PMOS tubes with interconnected drains; wherein,

the source electrode of the first PMOS tube is connected with the output end of the first power adapter and the first end of the voltage division threshold value circuit, and the source electrode and the grid electrode of the first PMOS tube are both connected with the first end of the current backflow preventing circuit;

the source electrode of the second PMOS tube is connected with the power supply end, and the source electrode and the grid electrode of the second PMOS tube are both connected with the second end of the current reverse-flowing prevention circuit.

3. The dual-power-supply switching circuit of claim 2, wherein the current-backflow prevention circuit comprises:

the first NMOS transistor comprises a first capacitor, a second capacitor, a first resistor, a second resistor, a fourth resistor, a first diode, a second diode and a third NMOS transistor; wherein,

one end of the first capacitor is connected with the source electrode of the first PMOS tube, and the other end of the first capacitor is connected with the anode of the first diode; one end of the first resistor is connected with the source electrode of the first PMOS tube, and the other end of the first resistor is connected with the anode of the first diode; the anode of the first diode is also connected with the grid of the first PMOS tube;

one end of the second capacitor is connected with the source electrode of the second PMOS tube, and the other end of the second capacitor is connected with the anode of the second diode; one end of the second resistor is connected with the source electrode of the second PMOS tube, and the other end of the second resistor is connected with the anode of the second diode; the anode of the second diode is also connected with the grid electrode of the second PMOS tube;

the negative electrode of the first diode and the negative electrode of the second diode are both connected with one end of a fourth resistor, the other end of the fourth resistor is connected with the drain electrode of a third NMOS tube, the grid electrode of the third NMOS tube is connected with the other end of the delay circuit, and the source electrode of the third NMOS tube is grounded.

4. The dual-power-supply switching circuit of claim 2, wherein the current-backflow prevention circuit comprises:

the first capacitor, the second capacitor, the first resistor, the second resistor, the fourth resistor, the ninth resistor, the third NMOS transistor and the seventh NMOS transistor; wherein,

one end of the first capacitor is connected with the source electrode of the first PMOS tube, and the other end of the first capacitor is connected with one end of the fourth resistor; one end of the first resistor is connected with the source electrode of the first PMOS tube, and the other end of the first resistor is connected with one end of the fourth resistor; one end of the fourth resistor is also connected with the grid electrode of the first PMOS tube;

one end of the second capacitor is connected with the source electrode of the second PMOS tube, and the other end of the second capacitor is connected with one end of the ninth resistor; one end of the second resistor is connected with the source electrode of the second PMOS tube, and the other end of the second resistor is connected with one end of the ninth resistor; one end of the ninth resistor is also connected with the grid electrode of the second PMOS tube;

the other end of the fourth resistor is connected with the drain electrode of the third NMOS tube, the grid electrode of the third NMOS tube is connected with the other end of the delay circuit, and the source electrode of the third NMOS tube is grounded;

the other end of the ninth resistor is connected with the drain electrode of the seventh NMOS tube, the grid electrode of the seventh NMOS tube is connected with the other end of the delay circuit, and the source electrode of the seventh NMOS tube is grounded.

5. The dual power switching circuit of claim 3 or 4, wherein the voltage divider threshold circuit comprises:

a third resistor, a sixth resistor and a third capacitor; wherein,

one end of a third resistor is connected with the source electrode of the first PMOS tube, the other end of the third resistor is connected with one end of a sixth resistor and one end of a third capacitor, and the other end of the sixth resistor and the other end of the third capacitor are both grounded; the other end of the third resistor is also connected with the second end of the dual-power interlocking circuit and one end of the delay circuit.

6. The dual power switching circuit of claim 5, wherein the delay circuit comprises:

a fifth resistor and a fourth capacitor; wherein,

one end of a fifth resistor is connected with the other end of the third resistor, and the other end of the fifth resistor is connected with one end of a fourth capacitor, a grid electrode of a third NMOS tube and a second end of the dual-power interlocking circuit; the other end of the fourth capacitor is grounded.

7. The dual power supply switching circuit of claim 6, wherein the dual power supply interlock circuit comprises:

a fourth NMOS transistor and a sixth NMOS transistor; wherein,

the drain electrode of the fourth NMOS tube is connected with the grid electrode of the third NMOS tube, the grid electrode of the fourth NMOS tube is connected with the drain electrode of the sixth NMOS tube, and the source electrode of the fourth NMOS tube is grounded;

the drain electrode of the sixth NMOS tube is also connected with the first end of the second power transmission circuit, the grid electrode of the sixth NMOS tube is connected with the other end of the third resistor, and the source electrode of the sixth NMOS tube is grounded.

8. The dual power switching circuit of claim 7, wherein the second power transfer circuit comprises:

the seventh resistor, the power switch chip and the fifth NMOS tube; wherein,

the first end of the power switch chip is connected with the output end of the second power adapter, the second end of the power switch chip is connected with the power supply end, the third end of the power switch chip is grounded, and the fourth end of the power switch chip is connected with one end of the seventh resistor and the drain electrode of the fifth NMOS tube; the grid electrode of the fifth NMOS tube is connected with the drain electrode of the sixth NMOS tube, and the source electrode of the fifth NMOS tube is grounded; the other end of the seventh resistor is connected with a fixed input voltage.

9. The dual power switching circuit of claim 8, further comprising:

and one end of the eighth resistor is connected with the grid electrode of the fifth NMOS tube, and the other end of the eighth resistor is connected to the output end of the second power adapter.

10. A dual power supply switching controller, comprising: the dual power switching circuit of any one of claims 1-9.