CN110700816A - Mining borehole logging cableless depth measurement device and method - Google Patents
Mining borehole logging cableless depth measurement device and method Download PDFInfo
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Abstract
The invention provides a mining borehole logging cableless depth measurement device and a mining borehole logging cableless depth measurement method, wherein the mining borehole logging cableless depth measurement device comprises a circuit board and an integrated circuit, and the integrated circuit comprises an acceleration measurement circuit, an analog-to-digital conversion circuit U4, a data temporary storage unit U14, a micro processing unit U1, a system clock circuit, a communication circuit U2 and a communication interface. The device is characterized in that an integrated circuit is arranged and welded on a circuit board to form a standard universal module, under the control of a microprocessing unit U1, the acceleration and the inclination angle measured by an inclination angle measuring circuit and the azimuth angle measured by an azimuth angle measuring circuit output analog quantities which are converted into digital quantities through an analog-to-digital conversion circuit U4, and the digital quantities are calculated and processed into a depth measuring depth corresponding to each sampling time point and stored in a data temporary storage unit U14. The mining borehole logging cableless depth measurement device and the mining borehole logging cableless depth measurement method are convenient to construct, low in cost and high in precision.
Description
Technical Field
The invention belongs to the technical field of borehole exploration logging, and particularly relates to a mining borehole logging cableless depth measurement device and a mining borehole logging depth measurement method.
Technical Field
In recent years, with the development of comprehensive mechanized coal mining technology, the development of effective underground exploration technology is urgently needed to ensure high yield and high efficiency of coal production. Drilling is used as a necessary exploration technical means, geological abnormity is detected under a coal mine well and widely used, but due to the common hole deviation phenomenon and difficulty in judging a horizon, borehole information is difficult to interpret. If the underground logging technology is combined with underground drilling, not only can the geological abnormal body be directly explored, but also the interpretation result of the mine geophysical prospecting can be verified. The underground logging technology can measure various logging parameters, is used for drilling hole guiding, correcting drilling hole deviation design, providing coal bed occurrence, dividing lithology and coal bed, performing coal bed comparison and the like, so the underground logging technology and a drilling detection instrument are indispensable.
The mining borehole depth measurement device is one of indispensable accessories of the underground well logging technology. The traditional mining drilling detection instrument adopts the length of a cable entering a drilled hole to calculate the depth of the drilled hole, obviously, the method cannot meet the continuous development, updating and perfection of the drilling detection instrument. At present, the length of a cable entering a drill hole is calculated by using a rotary encoder to determine the depth of the hole in the market, and the method comprises the following steps: the cable must be wound on the winch, one end of the cable is connected with a probe of the drilling detection instrument, the other end of the cable is connected with a main machine of the drilling detection instrument, and the main machine of the drilling detection instrument controls a rotary encoder arranged on the winch to realize depth measurement. Although the method meets the requirements of the existing drilling detection instrument, the following defects exist: (1) a winch is used, so that the instrument cost is increased; (2) the winch is very heavy and inconvenient to carry, and has high failure rate; (3) during depth measurement, a cable in a hole is tight and loose when the probe is operated to move forward and backward, and a section of cable between the hole opening and the winch is tight and loose, so that the measurement of the rotary encoder is inaccurate, the depth measurement error is large, and in addition, the precision of the rotary encoder also influences the measurement precision; (4) in the depth measurement process, the probe normally measures depth when advancing, and if backing up, the winch must take up the line in order to correct the reduction of depth measurement, and it is inconvenient to use. In addition, even when the cable is used, the cable is often twisted together, so that the depth measurement fails.
Aiming at the defects of the currently adopted drilling depth measurement mode, the invention abandons a winch, a cable and a coder, namely the cable drilling depth measurement mode, adopts a cable-free depth measurement device, forms a universal module, can be configured with various mining drilling well measurement instruments, can be popularized to other drilling well measurement instruments for matching use, and provides a depth measurement matching device without cables, which is convenient to construct, low in cost and high in precision.
Disclosure of Invention
Aiming at the technical problems, the invention provides a mining borehole logging cableless depth measurement device and a mining borehole logging cable-less depth measurement method which are convenient to carry, simple to construct, low in cost and high in depth measurement precision.
In order to achieve the purpose, the invention adopts the following technical means:
the mining borehole logging cableless depth measurement device comprises a circuit board and an integrated circuit, wherein the integrated circuit comprises an acceleration measurement circuit, an analog-digital conversion circuit U4, a data temporary storage unit U14, a micro processing unit U1, a system clock circuit, a communication circuit U2 and a communication interface. The device is characterized in that the integrated circuit is arranged and welded on a circuit board to form a standard universal module.
The signal output end of the acceleration measuring circuit is connected with the signal input end of an analog-to-digital conversion circuit U4; the digital output end of the analog-to-digital conversion circuit U4 is connected with the numerical input end of the micro processing unit U1; the data storage control end of the micro-processing unit U1 is connected with the data control end of the data temporary storage unit U14; the input clock end of the micro-processing unit U1 is connected with the clock output end of the system clock circuit; the data communication end of the micro-processing unit U1 is connected with the internal communication end of the communication circuit U2; the external communication end of the communication circuit U2 is connected with the inner end of the communication interface; the standard universal module is 80mm in length, 20mm in width and 15mm in height. The acceleration measurement, the analog-to-digital conversion, the data storage and the data transmission related by the invention all select proper low-power consumption industrial components and parts and are designed into independent and reliable circuits. The circuit board is designed by adopting a multilayer board and placing components on two sides. The device adopts high-speed standard serial communication with external communication. The design makes this device small, the low power dissipation, be convenient for with other drilling detecting instrument supporting.
Preferably, the acceleration measurement circuit includes a three-axis acceleration sensor U5, a filter U6, an X-axis buffer U7, a Y-axis buffer U8, and a Z-axis buffer U9. The filter U6 includes three independent X-axis, Y-axis, and Z-axis filters. The output end Voutx of the triaxial acceleration sensor U5 is connected with the input end + INA of the X-axis filter U6; the output end Vouty of the three-axis acceleration sensor U5 is connected with the input end + IND of the Y-axis filter U6; the output end Voutz of the three-axis acceleration sensor U5 is connected with the input end + INC of the Z-axis filtering U6; the output end OUA of the X-axis filter U6 is connected with the input end-INA and then is connected with the input end INP of the X-axis buffer U7; the output end OUD of the Y-axis filter U6 is connected with the input end-IND and then is connected with the input end INP of the Y-axis buffer U8; the output end OUTC of the Z-axis filter U6 is connected with the input end-INC and then is connected with the input end INP of the Z-axis buffer U9; the X-axis buffer U7, the Y-axis buffer U8 and the Z-axis buffer U9 are single-ended to differential buffer amplifiers. When the device is used for measuring depth, the three-axis acceleration sensor U5 generates acceleration analog signals in three directions of an X axis, a Y axis and a Z axis in the motion process, the acceleration analog signals are subjected to filtering processing by the three-way filter amplifier U6, high-frequency interference is filtered, and then the acceleration analog signals are transmitted to the analog-to-digital conversion circuit U4 through single-end slip of the three-way buffer amplifiers U7, U8 and U9 and are converted into digital signals. The resultant acceleration a (t) can be calculated according to the obtained acceleration component values of the X axis, the Y axis and the Z axis, and positive acceleration when the device moves forwards and negative acceleration when the device moves backwards are obtained.
Preferably, the ports AINP1 and AINN1 of the analog-to-digital conversion circuit U4 are respectively and correspondingly connected with the output end + OUT and OUT of the X-axis buffer U7 in the acceleration measurement circuit; the ports AINP2 and AINN2 of the analog-to-digital conversion circuit U4 are correspondingly connected with the output end + OUT and the output end-OUT of a Y-axis buffer U8 in the acceleration measuring circuit respectively; the ports AINP3 and AINN3 of the analog-to-digital conversion circuit U4 are correspondingly connected with output ends + OUT and OUT of a Z-axis buffer U9 in the acceleration measuring circuit respectively. The analog-digital conversion chip in the device has the following characteristics: the serial SPI control mode has 4 independent differential inputs, 4 independent digital serial outputs, 24 bits of conversion precision, conversion time less than 10uS and power consumption less than 100mW, so that the circuit designed by the analog-to-digital conversion chip has the characteristics of high speed, high precision, low power consumption and small size, and completely meets the design requirements of the device. 1 to 3 independent differential channel interfaces in the analog-to-digital conversion circuit U4 are distributed to an acceleration measurement circuit, and output quantities in the X-axis, Y-axis and Z-axis directions are converted into digital signals from analog signals; and the rest path of differential channel is reserved.
Preferably, the ports a _ SYNC, a _ SCLK, a _ DRDY, a _ PWDN1, a _ PWDN2 and a _ PWDN3 of the micro-processing unit U1 are respectively and correspondingly connected with the ports SYNC, SCLK, DRDY, PWDN1, PWDN2 and PWDN3 of the analog-to-digital conversion circuit U4; the data input ends A _ DOUT1, A _ DOUT2 and A _ DOUT3 of the microprocessing unit U1 are respectively and correspondingly connected with the data output ends DOUT1, DOUT2 and DOUT3 of the analog-to-digital conversion circuit U4; the clock CLK of the analog-to-digital conversion circuit U4 is connected with the clock output end Y of the shaping chip U3 in the system clock circuit. The microprocessing unit U1 of the device selects an FPGA microprocessing chip, wherein A _ SYNC is an acquisition starting control port of an analog-to-digital conversion circuit U4, A _ CLK provides an acquisition system clock for the analog-to-digital conversion circuit U4, A _ SCLK is a serial clock during acquisition of the analog-to-digital conversion circuit U4, one bit is output when one serial clock is executed, A _ DRDY is a state change port line when the analog-to-digital conversion of the analog-to-digital conversion circuit U4 is completed, A _ DOUT1, A _ DOUT2 and A _ DOUT3 are three conversion result output ports of the analog-to-digital conversion circuit U4, and A _ PWDN1, A _ PWDN2 and A _ PWDN3 are six low-power consumption control ports of the analog-to-digital conversion circuit U4.
Preferably, the control port W25_ CS, SPI _ SCLK, SPI _ MOSI, SPI _ MISO of the micro-processing unit U1 is connected to the controlled port CS, CLK, DI, DO of the data temporary storage unit U14. The data temporary storage unit U14 in the device selects the SPI interface memory chip with small volume, high storage speed and low power consumption, thus finishing the data storage function and meeting the design requirement of small volume.
Preferably, the system clock circuit comprises an active crystal oscillator, a shaping chip, a resistor and a capacitor. The active crystal oscillator enable end EN is connected with a power supply end VCC and then connected with a power supply VDD3.3, the active crystal oscillator ground end DGND is connected with a system ground GND, the C2 is connected between the active crystal oscillator power supply end VCC and the active crystal oscillator ground end DGND, the active crystal oscillator output end OUT is connected with the connection part of the C3 and the R1, and the connection part of the resistor R1 and the resistor R2 is connected with the system ground; the input end A of the shaping chip U3 is connected with the input end B and then connected with the connection position of the capacitor C3, the resistor R2 and the resistor R3, and the output end Y of the shaping chip U3 is connected with the clock port XATL of the microprocessing unit U1. The active crystal oscillator of the device selects a reliable crystal oscillator with high precision and low temperature drift, and the frequency is 27 MHz. After the frequency output by the active crystal oscillator is subjected to interference elimination processing by a shaping circuit consisting of a shaping chip U3 and a resistor capacitor thereof, a system clock frequency with high precision and good stability is output.
Preferably, the receiver RX of the microprocessor unit U1 is connected to the receiver R of the communication circuit U27; a transmitting end TX of the micro-processing unit U1 is connected with a transmitting end D of a communication circuit U27; the communication circuit U27 data receiving end RE is connected with the communication circuit U27 data transmitting end DE and then connected with the micro-processing unit U1 data direction control end DR; the input ends IO1, IO2 and IO3 of the parameter setting micro-processing unit U1 are correspondingly connected with the 1 st pin, the 2 nd pin and the 3 rd pin of the communication interface J1 respectively; the communication circuit U27 data transmission interface A is connected with the 4 th pin of the communication interface J1; the communication circuit U27 data transmission interface B is connected with the 5 th pin of the communication interface J1. When the parameter setting end IO1 of the microprocessing unit U1 in the device is 0, IO2 is 0, and IO3 is 0, the device records the depth measurement starting time to indicate that the depth measurement starts, and the matched drilling detection instrument works simultaneously, so that the parameter setting indicates synchronous operation, and the others are baud rate settings, as shown in table 1 below.
TABLE 1
| Serial number | IO3 | IO2 | IO1 | Baud rate (bps) |
| 1 | 0 | 0 | 1 | 28300 |
| 2 | 0 | 1 | 0 | 57600 |
| 3 | 0 | 1 | 1 | 115200 |
| 4 | 1 | 0 | 0 | 230400 |
| 5 | 1 | 0 | 1 | 460800 |
| 6 | 1 | 1 | 0 | 921600 |
| 7 | 1 | 1 | 1 | 1843200 |
The microprocessing unit U1 includes an FPGA core, a sample timer, and a control port. The FPGA cores IO4, IO5, A _ CYCLK, A _ CYCNT and A _ CYQD are correspondingly connected with CNT4, CNT5, CYCLK, CYCNT and CYQD of the sampling counter CLKCNT respectively. A _ CYCLK in the FPGA core is a sampling timer operation clock port line, A _ CYCNT is a sampling timer starting timing control line, and A _ CYQD informs the FPGA core to start a sampling state line; the FPGA cores IO4, IO5 are used to set the time interval between adjacent sampling points, as shown in table 2 below.
TABLE 2
| Serial number | IO5 | IO4 | Sampling interval (uS) |
| 1 | 0 | 0 | 50 |
| 2 | 0 | 1 | 100 |
| 3 | 1 | 0 | 150 |
| 4 | 1 | 1 | 200 |
A mining borehole logging cableless depth measurement method is based on a mining borehole logging cableless depth measurement device, and the method is used for achieving the purpose that the sum of acceleration signal transmission time, analog-to-digital conversion time, data storage time, data processing time and data communication time is required to be smaller than the time difference between adjacent sampling points. The implementation method comprises the following steps:
And 3, obtaining the displacement S (t) between the adjacent sampling points by utilizing the time difference △ t between the synthesized acceleration a (t) obtained in the step 3 and the set adjacent sampling points through secondary integration, wherein when the device moves forwards, the synthesized acceleration a (t) is a positive value, the calculated displacement S (t) is a positive value, and when the device moves backwards, the synthesized acceleration a (t) is a negative value, and the calculated displacement S (t) is a negative value.
The basic principle of the method is that the method is a novel product for replacing a depth measuring device in a mining borehole logging detecting instrument, the working process of the method is firstly known, before depth measurement, a host of the mining borehole logging detecting instrument sets a baud rate and a time difference △ t between adjacent sampling points through a communication interface J1 of the device, the time difference is called a sampling interval, the device continuously samples at equal sampling intervals according to the set sampling interval, the device can be ordered to carry out depth measurement at any time after parameters are set, after the device receives a depth measurement command transmitted from the communication interface J1, the host of the mining borehole logging detecting instrument immediately records the initial time of detection, and simultaneously the device also records the initial time t of depth measurement0The main machine detection of the mining borehole logging detecting instrument and the depth measurement of the device are synchronously carried out at the same time, and the time synchronization is required. In the depth measurement process, under the control of the microprocessing unit U1, the acceleration and the inclination angle measured by the inclination angle measurement circuit and the azimuth angle measured by the azimuth angle measurement circuit output analog quantities which are converted into digital quantities through the analog-to-digital conversion circuit U4, the data are calculated and processed into a depth measurement depth corresponding to each sampling time point and stored in the data temporary storage unit U14, and the depth measurement depth is sent to the host of the mining borehole logging detector through the communication circuit U2. Next, with the understanding of the basic workflow of the present apparatus, the data processing procedure is described below. When the device is arranged at the ith sampling point, the inclination angle measuring circuit obtains three axial acceleration components as a1i、a2i、a3iAnd calculating to obtain the synthetic acceleration a (t), wherein the calculation process is as follows:
the magnitude of the resultant acceleration a (t) is:
from the above measured acceleration as a (t), the rate of integration of the acceleration once is given by:
the displacement obtained by integrating the velocity signal once is:
the depth-sounding depth h at which n points are thus acquired is calculated as follows:
h＝s1+s2+…+sn
wherein: a (t) is a continuous time domain composite acceleration in m/s2
v (t) is the continuous time domain rate in m/s
s (t) is a continuous displacement in m
aiThe resultant acceleration sample value at time i
viRate value at time i
a0＝0，v0＝0
△ t is the time difference between two samples
The invention has the beneficial effects that:
the invention overcomes the defects of inflexible construction, inconvenient carrying, large depth measurement error, more faults and higher cost caused by the conventional common drilling depth measurement mode by utilizing a winch, a cable and an encoder, and forms a universal module by adopting the device and the method for the mining drilling depth measurement cableless depth measurement, can be used for configuring various mining drilling well measuring instruments and also can be popularized to other drilling well measuring instruments for matching use, thereby providing a cableless depth measurement matching device with convenient construction, low cost and high precision for the drilling depth measurement.
Drawings
FIG. 1 is a schematic structural diagram of a cableless depth measurement device for borehole logging in a mine;
FIG. 2 is a schematic diagram of a micro-processing unit U1 and a data temporary storage unit U14 of the cableless depth measurement device for borehole logging in a mine;
FIG. 3 is a schematic diagram of an acceleration measurement circuit of the mining borehole logging cableless depth measurement device of the present invention;
FIG. 4 is a schematic diagram of an analog-to-digital conversion circuit U4 of the cableless depth measurement device for borehole logging in a mine according to the present invention;
FIG. 5 is a schematic diagram of a communication circuit U2 of the cableless depth measurement device for borehole logging in a mine according to the present invention;
FIG. 6 is a schematic diagram of a system clock circuit principle of the cableless depth measurement device for borehole logging in a mine according to the present invention;
FIG. 7 is a schematic diagram of acceleration synthesis of a mining borehole logging cableless depth measurement method according to the present invention;
in the figure: the device comprises a circuit board 1, an acceleration measuring circuit 2, an analog-to-digital conversion circuit U4, a data temporary storage unit U14, a microprocessing unit U1, a system clock circuit 6 and a communication circuit U2 and 8, wherein the acceleration measuring circuit 3 is a data temporary storage unit U14, the microprocessing unit U1 is a microprocessing unit U3526, the communication circuit U2 is a communication circuit 7.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
As shown in fig. 1, the mining borehole logging cableless depth measurement device comprises a circuit board 1 and an integrated circuit, wherein the integrated circuit comprises an acceleration measurement circuit 2, an analog-to-digital conversion circuit U43, a data temporary storage unit U144, a microprocessor unit U15, a system clock circuit 6, a communication circuit U27 and a communication interface 8. The integrated circuit is a standard universal module formed by arranging and welding the integrated circuit on a circuit board 1.
The signal output end of the acceleration measuring circuit is connected with the signal input end of an analog-to-digital conversion circuit U43; the digital output end of the analog-to-digital conversion circuit U43 is connected with the numerical input end of the micro processing unit U15; the data storage control end of the micro-processing unit U15 is connected with the data control end of the data temporary storage unit U144; the input clock end of the micro-processing unit U15 is connected with the clock output end of the system clock circuit; the data communication end of the micro-processing unit U15 is connected with the internal communication end of the communication circuit U27; the external communication end of the communication circuit U27 is connected with the inner end of the communication interface; the standard universal module is 80mm in length, 20mm in width and 15mm in height.
In fig. 3, the acceleration measurement circuit 2 includes a three-axis acceleration sensor U5, a filter U6, an X-axis buffer U7, a Y-axis buffer U8, and a Z-axis buffer U9, while the filter U6 includes three independent X-axis, Y-axis, and Z-axis filters. The output end Voutx of the triaxial acceleration sensor U5 is connected with the input end + INA of the X-axis filter U6; the output end Vouty of the three-axis acceleration sensor U5 is connected with the input end + IND of the Y-axis filter U6; the output end Voutz of the three-axis acceleration sensor U5 is connected with the input end + INC of the Z-axis filtering U6; the output end OUA of the X-axis filter U6 is connected with the input end-INA and then is connected with the input end INP of the X-axis buffer U7; the output end OUD of the Y-axis filter U6 is connected with the input end-IND and then is connected with the input end INP of the Y-axis buffer U8; the output end OUTC of the Z-axis filter U6 is connected with the input end-INC and then is connected with the input end INP of the Z-axis buffer U9; the X-axis buffer U7, the Y-axis buffer U8 and the Z-axis buffer U9 are single-ended to differential buffer amplifiers. In this example, the three-axis acceleration sensor U5 selects the LIS344AIH, the filter U6 selects the four op amp OPA376, and the buffers U7, U8, and U9 all select the AD8476 single-ended differential high speed amplifier. When the device works, the three-axis acceleration sensor generates acceleration analog signals in the X-axis direction, the Y-axis direction and the Z-axis direction in the movement process, the acceleration analog signals are filtered by the three-way filter U6, high-frequency interference is filtered, and then the acceleration analog signals are transmitted to the analog-to-digital conversion circuit U433 to be converted into digital signals through the three-way buffers U7, U8 and U9 in a single-end slip mode. The acceleration component values of the X axis, the Y axis and the Z axis are obtained through the processing of the micro-processing unit U15, and the composite acceleration a (t) is calculated, wherein the acceleration is positive when the device moves forwards, and is negative when the device moves backwards.
In fig. 4, the input ports AINP1 and AINN1 of the analog-to-digital conversion circuit U43 are respectively and correspondingly connected with the output terminals + OUT and OUT of the X-axis buffer U7 in the acceleration measuring circuit 2; ports AINP2 and AINN2 of the analog-to-digital conversion circuit U43 are correspondingly connected with output ends + OUT and OUT of a Y-axis buffer U8 in the acceleration measuring circuit 2 respectively; the ports AINP3 and AINN3 of the analog-to-digital conversion circuit U43 are correspondingly connected with output ends + OUT and OUT of a Z-axis buffer U9 in the acceleration measuring circuit 2 respectively. The analog-to-digital conversion circuit U43 selects the ADS1274, and converts the acceleration component values in the three directions of the X axis, the Y axis and the Z axis transmitted from the acceleration measuring circuit 2 of fig. 3 from analog signals into digital signals under the control of the micro-processing unit U15.
In fig. 2, 4 and 6, the micro-processing unit U15 has ports a _ SYNC, a _ SCLK, a _ DRDY, a _ PWDN1, a _ PWDN2 and a _ PWDN3 respectively connected to ports SYNC, SCLK, DRDY, PWDN1, PWDN2 and PWDN3 in the analog-to-digital conversion circuit U43; the data input ends A _ DOUT1, A _ DOUT2 and A _ DOUT3 of the micro-processing unit U15 are respectively and correspondingly connected with the data output ends DOUT1, DOUT2 and DOUT3 of the analog-to-digital conversion circuit U43; the clock CLK of the analog-to-digital conversion circuit U43 is connected to the clock output terminal Y of the shaping chip U3 in the system clock circuit 6. The FPGA microprocessing chip of the embodiment is selected from EP4CE25F23I7 and the crystal oscillator is selected from BTO507AC3M508GA27.00. In this embodiment, a _ CLK is 27MHz, a _ SYNC is 0 at the time of analog-to-digital conversion, when a _ DRDY is 0, it is described that the analog-to-digital conversion is ended, data can be read, and a falling edge of a _ SCLK reads 1 bit, and reads 24 times consecutively, that is, the reading of 24 bits indicates that 1 point is finished by conversion, and then the next point is converted. The analog-to-digital conversion is performed three ways at the same time, so 3 points are read at a time.
The micro-processing unit U15 controls the ports W25_ CS, SPI _ SCLK, SPI _ MOSI and SPI _ MISO to be correspondingly connected with the controlled ports CS, CLK, DI and DO of the data temporary storage unit U1444U 14. The temporary storage unit of this embodiment selects W25Q128, and when the analog-to-digital conversion circuit U43 finishes a certain point of conversion in fig. 4, the conversion result can be temporarily stored in the data temporary storage unit U1444.
In fig. 6 and 4, the system clock circuit 6 includes an active crystal oscillator, a shaping chip, a resistor, and a capacitor. The active crystal oscillator enable end EN is connected with a power supply end VCC and then connected with a power supply VDD3.3, the active crystal oscillator ground end DGND is connected with a system ground GND, the C2 is connected between the active crystal oscillator power supply end VCC and the active crystal oscillator ground end DGND, the active crystal oscillator output end OUT is connected with the connection part of the C3 and the R1, and the connection part of the resistor R1 and the resistor R2 is connected with the system ground; the input end A of the shaping chip U3 is connected with the input end B and then connected with the connection position of the capacitor C3, the resistor R2 and the resistor R3, and the output end Y of the shaping chip U3 is connected with the clock port XATL of the microprocessing unit U15. The system clock circuit 6 of the present embodiment generates a27 MHz frequency to provide a sampling clock for the analog-to-digital conversion circuit U43.
In fig. 2 and 5, the receiver RX of the microprocessor unit U15 is connected to the receiver R of the communication circuit U27; a transmitting terminal TX of the micro-processing unit U15 is connected with a transmitting terminal D of the communication circuit U27; the communication circuit U27 data receiving end RE is connected with the communication circuit U27 data transmitting end DE and then connected with the micro-processing unit U15 data direction control end DR; the input ends IO1, IO2 and IO3 of the parameter setting micro-processing unit U15 are correspondingly connected with the 1 st pin, the 2 nd pin and the 3 rd pin of the communication interface 8J1 respectively; the communication circuit U27 data transmission interface A is connected with the 4 th pin of the communication interface 8J 1; the communication circuit U27 data transmission interface B is connected with the 5 th pin of the communication interface 8J 1. In this embodiment, the communication circuit U27 selects the RS485 driver chip MAX485, the baud rate selects 921600bps, the depth measurement start time is 0, the start speed is 0, and when IO1 is equal to 0, IO2 is equal to 0, IO3 is equal to 0, the depth measurement starts.
In FIG. 2, the microprocessing unit U15 includes an FPGA core, a sample timer, and a control port. The FPGA cores IO4, IO5, A _ CYCLK, A _ CYCNT and A _ CYQD are correspondingly connected with CNT4, CNT5, CYCLK, CYCNT and CYQD of the sampling counter CLKCNT respectively. A _ CYCLK in the FPGA core is a sampling timer CLKCNT operation clock port line, A _ CYCNT is a sampling timer starting timing control line, and A _ CYQD informs the FPGA core to start a sampling state line; the FPGA cores IO4, IO5 are used to set the time interval between adjacent sampling points. In this embodiment, the sampling timer CLKCNT always operates with a _ CYCLK being 100MHz, the FPGA cores IO4 and IO5 being set to 0, and the sampling interval being 50 uS. When the communication interface 8J1 detects that IO1 is 0, IO2 is 0, and IO3 is 0, depth measurement starts, a _ CYCNT changes from low level to high level, the sampling counter CLKCNT is started to work, and then every 50uS, the sampling timer CLKCNT output end CYQD sends out a low pulse through the FPGA core input end a _ CYQD, and a point is collected under the control of the microprocessing unit U15.
A mining borehole logging cableless sounding method is realized based on a sounding device, and the method is realized by requiring that the sum of acceleration signal transmission time, analog-to-digital conversion time, data storage time, data processing time and data communication time is less than the time difference between adjacent sampling points. The implementation method comprises the following steps:
And 3, obtaining the displacement S (t) between the adjacent sampling points by utilizing the time difference △ t between the synthesized acceleration a (t) obtained in the step 3 and the set adjacent sampling points through secondary integration, wherein when the device moves forwards, the synthesized acceleration a (t) is a positive value, the calculated displacement S (t) is a positive value, and when the device moves backwards, the synthesized acceleration a (t) is a negative value, and the calculated displacement S (t) is a negative value.
Specifically, with reference to fig. 7, the correlation calculation is performed as follows:
the magnitude of the resultant acceleration a (t) is:
from the above measured acceleration as a (t), the rate of integration of the acceleration once is given by:
the displacement obtained by integrating the velocity signal once is:
the depth-sounding depth h at which n points are thus acquired is calculated as follows:
h＝s1+s2+…+sn
wherein: a (t) is a continuous time domain composite acceleration in m/s2
v (t) is the continuous time domain rate in m/s
s (t) is a continuous displacement in m
h is depth of sounding, unit m
s1，s2，…，snFor displacement between adjacent sampling points, unit m
aiThe resultant acceleration sample value at time i
viRate value at time i
a0＝0，v0＝0
△ t is the time difference between two samples
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the present invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A mining borehole logging cableless depth measurement device comprises a circuit board and an integrated circuit, and is characterized in that the integrated circuit is integrated on the circuit board and comprises an acceleration measurement circuit, an analog-to-digital conversion circuit U4, a data temporary storage unit U14, a micro-processing unit U1, a system clock circuit, a communication circuit U2 and a communication interface;
the signal output end of the acceleration measuring circuit is connected with the signal input end of the analog-to-digital conversion circuit; the digital output end of the analog-to-digital conversion circuit is connected with the numerical input end of the micro-processing unit; the data storage control end of the micro-processing unit is connected with the data control end of the data temporary storage unit; the input clock end of the micro-processing unit is connected with the clock output end of the system clock circuit; the data communication end of the micro-processing unit is connected with the internal communication end of the communication circuit U2; the communication circuit U2 is externally connected with a communication end and is connected with the inner end of the communication interface.
2. The cableless depth measurement device for mining borehole logging according to claim 1, characterized in that: the acceleration measuring circuit comprises a three-axis acceleration sensor U5, a filter U6, an X-axis buffer U7, a Y-axis buffer U8 and a Z-axis buffer U9, the filter U6 comprises three independent X-axis filters U6, Y-axis filters U6 and Z-axis filters U6, and the output end Voutx of the three-axis acceleration sensor U5 is connected with the input end + INA of the X-axis filter U6; the output end Vouty of the three-axis acceleration sensor U5 is connected with the input end + IND of the Y-axis filter U6; the output end Voutz of the three-axis acceleration sensor U5 is connected with the input end + INC of the Z-axis filtering U6; the output end OUA of the X-axis filter U6 is connected with the input end-INA and then is connected with the input end INP of the X-axis buffer U7; the output end OUD of the Y-axis filter U6 is connected with the input end-IND and then is connected with the input end INP of the Y-axis buffer U8; and the output end OUTC of the Z-axis filter U6 is connected with the input end-INC and then is connected with the input end INP of the Z-axis buffer U9.
3. The cableless depth measurement device for mining borehole logging according to claim 1, characterized in that: ports AINP1 and AINN1 of the analog-to-digital conversion circuit U4 are correspondingly connected with output ends + OUT and OUT of an X-axis buffer U7 in the acceleration measuring circuit respectively; the ports AINP2 and AINN2 of the analog-to-digital conversion circuit U4 are correspondingly connected with the output end + OUT and the output end-OUT of a Y-axis buffer U8 in the acceleration measuring circuit respectively; the ports AINP3 and AINN3 of the analog-to-digital conversion circuit U4 are correspondingly connected with output ends + OUT and OUT of a Z-axis buffer U9 in the acceleration measuring circuit respectively.
4. The cableless depth measurement device for mining borehole logging according to claim 1, characterized in that: the ports A _ SYNC, A _ SCLK, A _ DRDY, A _ PWDN1, A _ PWDN2 and A _ PWDN3 of the micro-processing unit U1 are respectively and correspondingly connected with the ports SYNC, SCLK, DRDY, PWDN1, PWDN2 and PWDN3 in the analog-to-digital conversion circuit U4; the data input ends A _ DOUT1, A _ DOUT2 and A _ DOUT3 of the microprocessing unit U1 are respectively and correspondingly connected with the data output ends DOUT1, DOUT2 and DOUT3 of the analog-to-digital conversion circuit U4; the clock CLK of the analog-to-digital conversion circuit U4 is connected with the clock output end Y of the shaping chip U3 in the system clock circuit.
5. The cableless depth measurement device for mining borehole logging according to claim 1, characterized in that: the micro-processing unit U1 controls the ports W25_ CS, SPI _ SCLK, SPI _ MOSI and SPI _ MISO to be correspondingly connected with the controlled ports CS, CLK, DI and DO of the data temporary storage unit U14 respectively.
6. The cableless depth measurement device for mining borehole logging according to claim 1, characterized in that: the system clock circuit comprises an active crystal oscillator CY, a shaping chip U3, a resistor R1, a resistor R2, a resistor R3, a capacitor C2 and a capacitor C3, wherein an enable end EN of the active crystal oscillator CY is connected with a power supply end VCC and then connected with a power supply VDD3.3, a ground end DGND of the active crystal oscillator CY is connected with a system ground GND, the capacitor C2 is connected between the power supply end VCC of the active crystal oscillator CY and the ground end DGND of the active crystal oscillator CY, an output end OUT of the active crystal oscillator CY is connected with both the C3 and the R1, and the resistor R1 and the resistor R2 are connected and the connection part is connected with the system ground; the input end A of the shaping chip U3 is connected with the input end B and then connected with the connection position of the capacitor C3, the resistor R2 and the resistor R3, and the output end Y of the shaping chip U3 is connected with the clock port XATL of the microprocessing unit U1.
7. The cableless depth measurement device for mining borehole logging according to claim 5, characterized in that: the receiving end RX of the micro-processing unit U1 is connected with the receiving end R of the communication circuit U2; a transmitting end TX of the micro-processing unit U1 is connected with a transmitting end D of a communication circuit U2; the communication circuit U2 data receiving end RE is connected with the communication circuit U2 data transmitting end DE and then connected with the micro-processing unit U1 data direction control end DR; the input ends IO1, IO2 and IO3 of the parameter setting micro-processing unit U1 are correspondingly connected with the 1 st pin, the 2 nd pin and the 3 rd pin of the communication interface J1 respectively; the communication circuit U2 data transmission interface A is connected with the 4 th pin of the communication interface J1; the communication circuit U2 data transmission interface B is connected with the 5 th pin of the communication interface J1.
8. The cableless depth measurement device for mining borehole logging according to claim 7, characterized in that: the microprocessing unit U1 comprises an FPGA core IO4, IO5, A _ CYCLK, A _ CYCNT and A _ CYQD, and the FPGA core IO4, IO5, A _ CYCLK, A _ CYCNT and A _ CYQD are respectively and correspondingly connected with CNT4, CNT5, CYCLK, CYCNT and CYQD of the sampling counter CLKCCNT.
9. The cableless depth measurement device for mining borehole logging according to claim 7, characterized in that: the X-axis buffer U7, the Y-axis buffer U8 and the Z-axis buffer U9 are all single-ended to differential buffer amplifiers.
10. A mining borehole logging cableless depth measurement method is characterized in that: the method comprises the following steps:
step 1, the device defaults to an equal time interval continuous sampling mode, before depth measurement starts, a microprocessing unit U1 sets a communication baud rate and a time difference △ t between adjacent sampling points;
step 2, starting sounding, recording the starting time t of sounding by utilizing the microprocessing unit in the device0Simultaneously recording the sampling time t of each sampling point in the depth measurement processi(ii) a The acceleration components of the X axis, the Y axis and the Z axis of the device are respectively a for measuring the ith sampling point in the depth measurement process by utilizing the acceleration measuring circuit in the device1i、a2i、a3iCalculating the resultant acceleration a (t);
step 3, obtaining the displacement S (t) between the adjacent sampling points by utilizing the time difference △ t between the synthesized acceleration a (t) obtained in the step 3 and the set adjacent sampling points through secondary integration, wherein when the device moves forwards, the synthesized acceleration a (t) is a positive value, and the calculated displacement S (t) is a positive value;
step 4, when calculating the displacement between the next adjacent sampling points, calculating the previously calculated displacement S (t-1) and the corresponding sampling time tiStoring the displacement S (t-1) and the corresponding sampling time t in a data temporary storage unitiSending out through a communication interface;
step 5, accumulating the displacement S (t) between the adjacent sampling points obtained in the step 4, and finally obtaining the depth sounding depth h corresponding to each sampling point timeiAnd the depth measurement depth is sent out through a communication interface.
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