CN110622303B - 碳化硅电源模块 - Google Patents

碳化硅电源模块 Download PDF

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Publication number
CN110622303B
CN110622303B CN201880030402.2A CN201880030402A CN110622303B CN 110622303 B CN110622303 B CN 110622303B CN 201880030402 A CN201880030402 A CN 201880030402A CN 110622303 B CN110622303 B CN 110622303B
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terminal
power module
substrate
power
semiconductor die
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CN110622303A (zh
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姆里纳尔·K·达斯
亚当·巴克利
布赖恩·费策尔
乔纳森·扬
范·梅奇科夫斯基
斯科特·艾伦
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Wofu Semiconductor Co ltd
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Wofu Semiconductor Co ltd
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Abstract

电源模块包括第一端子、第二端子和耦合在第一端子和第二端子之间的多个半导体管芯。所述半导体管芯被配置为在前向导通操作模式期间，为从第一端子到第二端子的电流流动提供低电阻路径，并且在前向阻断配置期间，为从第一端子到第二端子的电流流动提供高电阻路径。由于电源模块的改进，电源模块能够在额定电压的80％下通过至少1000小时的温度、湿度和偏置测试。

Description

碳化硅电源模块
技术领域
本公开涉及电源模块，并且具体涉及包括碳化硅开关半导体元件的电源模块，其提高了耐用性和可靠性。
背景技术
电源模块用于选择性地向负载输送功率。电源模块的主要功能由电源模块内的多个开关半导体器件(例如，晶体管和二极管)提供。当设置在具有一个或多个其他电源模块和/或一个或多个其他组件的功率系统中时，电源模块的开关半导体器件可以形成功率转换器(例如，半桥转换器、全桥转换器、降压转换器、升压转换器等)的一部分。电力系统通常处理较高的电压和电流，因此电源模块的开关半导体器件必须同样能够可靠地切换这些高电压和电流。
传统上，电源模块的开关半导体器件是硅器件，这是由于众所周知的用于生产能够可靠地切换高电压和电流的硅开关半导体器件的工艺。然而，近年来，由于碳化硅的使用大大提高了切换速度和效率，用于电源模块的碳化硅半导体开关器件已经普及。虽然具有碳化硅半导体开关器件的电源模块提供了优于其硅对应物的几个性能优势，但是在电源模块中使用碳化硅半导体开关器件在其设计中提出了几个挑战。具体地，碳化硅半导体开关器件中功率密度的增加和电场的集中经常导致包含其的电源模块的长期可靠性问题。
测量电源模块可靠性的一种方法是进行测试，该测试称为温度、湿度和偏差(THB)测试。传统上，通过在具有固定温度(例如，85℃)和相对湿度(例如，85％)的环境中提供被测器件(DUT)，同时在反向偏置(即，阻断)状态下在DUT上提供固定偏置电压(例如，100V)，来进行THB测试。DUT应能够维持器件上的偏置电压数千小时而不击穿(即超过通过器件的漏电流的阈值)，以确保DUT在生产环境中的可靠性。最近，已经出现针对高功率器件的更严格的THB测试，其中，在上述相同条件下，在器件上提供80％的DUT额定电压。在业界被称为“THB80”或“HV-H3TRB”(高压、高温、高反向偏置)测试，这些可靠性测试更准确地反映了正在使用的器件的可靠性，并且是将在室外电力系统等恶劣环境中运行的电源模块的可靠性的关键指标。
值得注意的是，可以在管芯级和模块级进行THB测试。当在管芯级执行THB测试时，半导体管芯经受上述条件，并且评估管芯的可靠性。当在模块级执行THB测试时，包括几个半导体管芯的组装电源模块经受上述条件，并且整体评估模块的可靠性。在模块级执行的THB测试明显更难通过，因为电源模块的复杂性明显大于单个半导体管芯的复杂性，因此与半导体管芯相比，存在更多的故障点。此外，当与从包括在电源模块内的半导体管芯上执行的THB测试推断可靠性相比时，在模块级执行的THB测试更有可能指示电源模块的现实世界可靠性。随着包括碳化硅开关半导体器件的电源模块变得越来越流行，客户对用于恶劣环境的这些电源模块的需求也同样增长。然而，迄今为止，包括碳化硅半导体开关元件的电源模块的可靠性已经证明是在这些空间中采用其的障碍。具体地，迄今为止，包括碳化硅半导体开关元件的电源模块在上述THB80测试中不能获得令人满意的性能。
鉴于上述情况，目前需要提高耐用性和可靠性的包括碳化硅半导体开关元件的电源模块。
发明内容
在一个实施方式中，电源模块包括：第一端子；第二端子；以及多个碳化硅(SiC)半导体管芯，其耦合在第一端子和第二端子之间。所述多个半导体管芯被配置为在前向导通操作模式期间，为从第一端子到第二端子的电流流动提供低电阻路径，使得第一端子和第二端子之间的电阻小于100mΩ。此外，半导体管芯被配置为在前向阻断操作模式期间，为从第一端子到第二端子的电流流动提供高电阻路径，使得当在第一端子和第二端子上提供电源模块的额定电压的至少80％的电压时，第一端子和第二端子之间的泄漏电流小于20mA，其中，所述电源模块的额定电压至少为600V。所述电源模块能够在至少85℃的温度和至少85％的相对湿度下在至少1000小时的周期内在第一端子和第二端子上无故障地保持额定电压的至少80％的电压。
在一个实施方式中，每个半导体管芯包括衬底、衬底上的漂移层和漂移层上的钝化层堆叠。钝化层堆叠包括多个钝化层，使得钝化层的成分在至少第一材料和第二材料之间交替。以这种方式设置钝化层堆叠实质上增加了电源模块的可靠性，因为这防止了分层和腐蚀，这些分层和腐蚀会损坏电源模块的半导体管芯并导致其故障。
在一个实施方式中，每个半导体管芯中漂移层上的钝化层堆叠包括至少四层。此外，钝化层堆叠可以具有至少1.6μm的厚度。提供厚度至少为1.6μm的钝化层堆叠进一步防止分层和腐蚀，这些分层和腐蚀会损坏电源模块的半导体管芯并导致其故障。
在一个实施方式中，每个半导体管芯包括衬底上与漂移层相对的背面金属化层。背面金属化层可以形成金属氧化物半导体场效应晶体管(MOSFET)的漏极触点和/或肖特基二极管的阳极触点，并且基本上不含银。通过使用基本上不含银的背面金属化层，可以防止通常位于背面金属化层中的银的电迁移，从而通过减少经常由此引起的短路来增加电源模块的可靠性。
在一个实施方式中，电源模块还包括功率电子衬底，半导体管芯经由管芯附着材料安装在该功率电子衬底上。功率电子衬底和管芯附着材料都基本上不含银。因此，可以防止通常位于功率电子衬底和管芯附着材料中的银的电迁移，从而通过减少由此引起的短路来增加电源模块的可靠性。
在结合附图阅读优选实施方式的以下详细描述后，本领域技术人员应当理解本公开的范围并实现其额外方面。
附图说明
并入说明书并形成本说明书的一部分的附图说明了本公开的几个方面，并且与说明书一起用于解释本公开的原理。
图1是根据本公开的一个实施方式的电源模块的等轴视图；
图2A和2B是根据本公开的一个实施方式的电源模块的功能示意图；
图3是根据本公开的一个实施方式的电源模块的功能示意图；
图4是根据本公开的一个实施方式的电源模块的一部分的剖视图；
图5是根据本公开的一个实施方式的半导体管芯的剖视图；
图6A和6B是根据本公开的一个实施方式的形成在半导体管芯上的半导体器件的剖视图；
图7是示出根据本公开的一个实施方式的用于制造电源模块的过程的流程图。
具体实施方式
下面阐述的实施方式表示使本领域技术人员能够实践实施方式的必要信息，并示出了实践实施方式的最佳模式。根据附图阅读以下描述后，本领域技术人员应当理解本公开的概念，并且将认识到这些概念在本文没有特别提及的应用。应当理解，这些概念和应用落在本公开和所附权利要求的范围内。
应当理解，尽管术语第一、第二等可以在本文用于描述各种元件，但是这些元件不应该受这些术语的限制。这些术语仅用于区分一种元件和另一种元件。例如，在不脱离本公开的范围的情况下，第一元件可以称为第二元件，并且类似地，第二元件可以称为第一元件。如本文所使用的，术语“和/或”包括一个或多个相关列出项目的任何和所有组合。
应当理解，当诸如层、区域或衬底等元件称为“在另一元件上”或延伸到“另一元件上”时，可以直接在另一元件上或直接延伸到另一元件上，或者也可以存在中间元件。相反，当一个元件称为“直接在另一元件上”或“直接在另一元件上”延伸时，不存在中间元件。同样，应当理解，当诸如层、区域或衬底等元件称为“在另一元件之上”或延伸到“另一元件之上”时，可以直接在另一元件之上或直接延伸到另一元件之上，或者也可以存在中间元件。相反，当一个元件称为“直接在另一元件之上”或“直接在另一元件之上”延伸时，不存在中间元件。还应当理解，当一个元件称为“连接”或“耦合”到另一元件时，可以直接连接或耦合到另一元件，或者可以存在中间元件。相反，当一个元件称为“直接连接”或“直接耦合”到另一元件时，不存在中间元件。
本文可以使用诸如“下方”或“上方”或“上部”或“下部”或“水平”或“垂直”等相对术语来描述一个元件、层或区域与另一元件、层或区域的关系，如图所示。应当理解，这些术语和上面讨论的那些术语旨在包括除了附图中描述的方向之外的器件的不同方向。
本文使用的术语仅用于描述特定实施方式的目的，并不旨在限制本公开。如本文所使用的，单数形式“一”、“一个”和“该”旨在也包括复数形式，除非上下文另有明确指示。还应当理解，术语“包括”、“包含”在本文使用时指定所述特征、整数、步骤、操作、元件和/或组件的存在，但不排除一个或多个其他特征、整数、步骤、操作、元件、组件和/或其组的存在或添加。
除非另有定义，本文使用的所有术语(包括技术和科学术语)具有与本公开所属领域的普通技术人员通常理解的相同含义。还应当理解，本文使用的术语应该被解释为具有与其在本说明书和相关技术的上下文中的含义一致的含义，并且除非本文这样明确定义，否则不会被解释为理想化或过于正式的含义。
图1是根据本公开的一个实施方式的电源模块10的等轴视图。电源模块10包括基板12、基板12上的多个子模块14(单独14A-14D)以及子模块14上的多个半导体管芯16。每个半导体管芯16提供开关半导体器件。例如，半导体管芯16的一半可以提供诸如金属氧化物半导体场效应晶体管(MOSFET)等晶体管，而半导体管芯16的另一半可以提供诸如肖特基二极管等二极管。虽然未示出，以避免混淆附图，但是半导体管芯16通过互连彼此连接，可以提供互连，作为子模块14上的金属迹线和/或器件之间的引线接合。如下所述，多个端子可以提供到半导体管芯的连接点。
虽然电源模块10显示为包括四个子模块14，每个子模块包括六个半导体管芯16，但是本公开不限于此。本领域技术人员应当理解，在不脱离本公开的原理的情况下，可以在衬底上提供任意数量的子模块14，每个子模块包括任意数量的半导体管芯16。
图2A和2B示出了根据本公开的一个实施方式的电源模块10的功能示意图。具体地，图2A示出了电源模块10中子模块14之间的互连，而图2B示出了由电源模块10提供的最终电路。如图2A所示，第一子模块14A和第二子模块14B在第一端子18A和第二端子18B之间彼此并联耦合。第三子模块14C和第四子模块14D在第二端子18B和第三端子18C之间类似地并联连接。第一控制端子20A连接到第一子模块14A和第二子模块14B。第二控制端子20B连接到第三子模块14C和第四子模块14D。
如图2B所示，第一子模块14A和第二子模块14B形成与第一二极管D1反并联耦合的第一MOSFET Q1，而第三子模块14C和第四子模块14D形成与第二二极管D2反并联耦合的第二MOSFET Q2。第一MOSFET Q1和第一二极管D1在第一端子18A和第二端子18B之间耦合。具体地，第一端子18A耦合到第一MOSFET Q1的漏极触点(D)和第一二极管D1的阴极触点(C)，第二端子18B耦合到第一MOSFET Q1的源极触点(S)和第一二极管D1的阳极触点(A)。第一控制端子20A耦合到第一MOSFET Q1的栅极触点(G)。第二MOSFET Q2和第二二极管D2在第二端子18B和第三端子18C之间耦合。具体地，第二端子18B耦合到第二MOSFET Q2的漏极触点(D)和第二二极管D2的阴极触点(C)，第三端子18C耦合到第二MOSFET Q2的源极触点(S)和第二二极管D2的阳极触点(A)。第二控制端子20B耦合到第二MOSFET Q2的栅极触点(G)。
当经由第一控制端子20A在第一MOSFET Q1的栅极触点(G)处提供的电压高于器件的阈值电压并且在漏极触点(D)处提供的电压相对于在其源极触点(S)处提供的电压为正时，第一MOSFET Q1处于前向导通操作模式，并且因此被配置为在第一端子18A和第二端子18B之间提供电流流动的低电阻路径。在这种配置中，第一二极管D1反向偏置，因此电流不会流过第一二极管D1。类似地，当经由第二控制端子20B在第二MOSFET Q2的栅极触点(G)处提供的电压高于器件的阈值电压并且在漏极触点(D)处提供的电压相对于在其源极触点(S)处提供的电压为正时，第二MOSFET Q2处于前向导通操作模式，并且因此被配置为在第二端子18B和第三端子18C之间提供电流流动的低电阻路径。在这种配置中，第二二极管D2反向偏置，因此电流不会流过第二二极管D2。如本文所定义的，低电阻路径是电阻可以忽略的路径，并且等于第一MOSFET Q1或第二MOSFET Q2的导通电阻。第一MOSFET Q1和第二MOSFET Q2的导通电阻可以根据其功率处理能力而变化。然而，通常，低电阻路径可以定义为具有小于100mΩ的电阻。
当经由第一控制端子20A在第一MOSFET Q1的栅极触点(G)处提供的电压低于器件的阈值电压并且在漏极触点(D)处提供的电压相对于在其源极触点(S)处提供的电压为正时，第一MOSFET Q1处于前向阻断配置，并且因此被配置为在第一端子18A和第二端子18B之间提供电流流动的高电阻路径。在这种配置中，第一二极管D1反向偏置，因此电流不会流过第一二极管D1。类似地，当经由第二控制端子20B在第二MOSFET Q2的栅极触点(G)处提供的电压低于器件的阈值电压并且在漏极触点(D)处提供的电压相对于在其源极触点(S)处提供的电压为正时，第二MOSFET Q2处于前向阻断配置，并且因此被配置为在第二端子18B和第三端子18C之间提供电流流动的高电阻路径。在这种配置中，第二二极管D2反向偏置，因此电流不会流过第二二极管D2。如本文所定义的，高电阻路径是具有实际上无限电阻的路径，并且等于第一MOSFET Q1和第二MOSFET Q2的截止状态电阻。第一MOSFET Q1和第二MOSFET Q2的截止状态电阻可以根据其功率处理能力而变化。然而，通常，高电阻路径可以定义为具有比低电阻路径的电阻大得多的电阻，并且大于100kΩ。
当在第一MOSFET Q1的漏极触点(D)处提供的电压相对于在源极触点(S)处提供的电压为负时，第一MOSFET Q1处于反向阻断配置，并且继续为第一端子18A和第二端子18B之间的电流流动提供高电阻路径。在这种配置中，第一二极管D1前向偏置，因此允许电流从第二端子18B流向第一端子18A。类似地，当在第二MOSFET Q2的漏极触点(D)处提供的电压相对于其源极触点(S)为负时，第二MOSFET Q2处于反向阻断配置，并且继续为第二端子18B和第三端子18C之间的电流流动提供高电阻路径。在这种配置中，第二二极管D2前向偏置，因此允许电流从第三端子18C流向第二端子18B。
因此，本领域技术人员应当理解，图2A和2B所示的电源模块10是半桥电源模块。然而，本公开不限于此。本文描述的原理可以应用于任何配置的电源模块，例如，包括以任何数量或配置设置的更多或更少开关元件的电源模块。此外，虽然电源模块10的晶体管器件在上文中被描述为MOSFET，但是在不脱离本文的原理的情况下，任何类型的晶体管器件都可以用于电源模块10中。例如，在一些实施方式中，绝缘栅双极晶体管(IGBT)可以代替第一MOSFET Q1和第二MOSFET Q2。类似地，在不背离本文描述的原理的情况下，第一二极管D1和第二二极管D2可以是任何类型的二极管。例如，第一二极管D1和第二二极管D2可以是肖特基二极管、肖特基势垒二极管(SBD)，或者甚至可以作为上述第一MOSFET Q1和第二MOSFET Q2的内置体二极管而提供，使得第一二极管D1与第一MOSFET Q1集成，第二二极管D2与第二MOSFET Q2集成。即使当第一二极管D1不是由第一MOSFET Q1的内置体二极管形成时，在一些实施方式中，第一二极管D1也可以在同一半导体管芯上与第一MOSFET Q1单片集成。类似地，即使当第二二极管D2不是由第二MOSFET Q2的内置体二极管形成时，在一些实施方式中，第二二极管D2也可以在同一半导体管芯上与第二MOSFET Q2单片集成。
图3是示出每个子模块14的细节的功能示意图。如图3所示，每个子模块14包括：第一晶体管-二极管对22A，包括与第一子模块二极管DS1反并联耦合的第一子模块MOSFETQS1；第二晶体管-二极管对22B，包括与第二子模块二极管DS2反并联耦合的第二子模块MOSFET Q S2；以及第三晶体管-二极管对22C，包括与第三子模块二极管DS3反并联耦合的第三子模块MOSFET Q S3。第一晶体管二极管对22A、第二晶体管二极管对22B和第三晶体管二极管对22C在第一子模块端子24A和第二子模块端子24B之间并联耦合。具体地，第一子模块端子24A耦合到第一子模块MOSFET QS1、第二子模块MOSFET QS2和第三子模块MOSFET QS3中的每一个的漏极触点(D)以及第一子模块二极管DS1、第二子模块二极管DS2和第三子模块二极管DS3中的每一个的阴极触点(C)。第二子模块端子24B耦合到第一子模块MOSFET QS1、第二子模块MOSFET QS2和第三子模块MOSFET QS3中的每一个的源极触点(S)以及第一子模块二极管DS1、第二子模块二极管DS2和第三子模块二极管DS3中的每一个的阳极触点(A)。子模块控制端子26经由单独的栅极电阻器RG耦合到第一子模块MOSFET QS1、第二子模块MOSFETQS2和第三子模块MOSFET QS3中的每一个的栅极触点(G)。
在图3所示的子模块14是第一子模块14A或第二子模块14B的情况下，第一子模块端子24A耦合到第一端子18A(见图2A)，第二子模块端子24B耦合到第二端子18B，并且子模块控制端子26耦合到第一控制端子20A。在图3所示的子模块14是第三子模块14C或第四子模块14D的情况下，第一子模块端子24A耦合到第二端子18B，第二子模块端子24B耦合到第三端子18C，并且子模块控制端子26耦合到第二控制端子20B。
第一子模块MOSFET QS1、第二子模块MOSFET QS2和第三子模块MOSFET QS3有效地在第一子模块端子24A和第二子模块端子24B之间形成单个MOSFET。类似地，第一子模块二极管D S1、第二子模块二极管DS2和第三子模块二极管DS3有效地在第一子模块端子24A和第二子模块端子24B之间形成单个二极管。当第一子模块14A和第二子模块14B在第一端子18A和第二端子18B之间并联耦合时，这些子模块有效地形成第一MOSFET Q1和第一二极管D1(见图2B)。当第三子模块14C和第四子模块14D在第二端子18B和第三端子18C之间并联耦合时，这些子模块有效地形成第二MOSFET Q2和第二二极管D2。
第一子模块MOSFET QS1、第二子模块MOSFET QS2和第三子模块MOSFET QS3的最大漏极-源极电压VDSmax可额定为1.2kV，导通电阻约为25.2mΩ。当如上所述与电源模块10中的另一子模块14的MOSFET并联提供，以提供六个并联MOSFET时，第一MOSFET Q1和第二MOSFET Q2中的每一个的导通电阻因此约为4.2mΩ。电源模块10中使用的MOSFET和二极管可以与北卡罗来纳州达勒姆的Cree公司制造的零件号CAS300M12BM2的相同，其数据表通过引用整体结合于此。因此，电源模块10可以共享与该部分相同的性能，包括阻断电压、导通电阻、泄漏电流等。本领域技术人员应当理解，电源模块10的上述性能特征仅仅是示例性的，并且本公开的原理可以应用于针对任何应用额定的电源模块，因此具有不同的阻塞电压、电流处理能力、导通电阻等。例如，本公开的原理可以应用于额定低至600V和高达15kV的电源模块。在这些实施方式中，可以使用额外的MOSFET和二极管来实现不同的性能特性，并且MOSFET和二极管本身的性能特性可以是不同的(例如，MOSFET和二极管可以针对600V和15kV之间的最大漏极-源极电压单独额定，并且因此提供不同的导通状态电阻)。
如图1所示，第一子模块MOSFET QS1、第二子模块MOSFET QS2、第三子模块MOSFETQS3、第一子模块二极管DS1、第二子模块二极管DS2和第三子模块二极管DS3可以均由分立半导体管芯16提供。然而，如上所述，在某些实施方式中，二极管可以与同一半导体管芯上的MOSFET组合。在一些实施方式中，半导体管芯16可以是碳化硅(SiC)半导体管芯。如上所述，在电源模块中使用SiC半导体管芯可以在性能上提供若干改进，例如，在切换速度和效率上。然而，迄今为止，包括SiC半导体管芯的电源模块的耐用性和可靠性并不令人满意。
因此，为了提高电源模块10的耐用性和可靠性，对电源模块10进行了若干改进，所有这些都在此处介绍并在下面详细讨论。首先，在每个半导体管芯16上提供钝化层堆叠，以减少腐蚀和分层。钝化层堆叠包括几个钝化层，钝化层的成分从一层到另一层交替。在一些实施方式中，钝化层堆叠中包括至少五个交替的钝化层。在某些实施方式中，钝化层堆叠的厚度可以大于1.6μm，并且可以根据等离子体增强化学气相沉积(PECVD)工艺来提供钝化层，以提高层的质量。第二，可以提供每个半导体管芯16的背面金属化层，使得其基本上不含银，以减少银向位于管芯上的一个或多个触点的电迁移。第三，可以提供每个半导体管芯16，使得其切割片基本上不含镍(通常可以提供镍，以形成接地环)，以减少其朝向位于管芯上的一个或多个触点的电迁移。第四，每个半导体管芯16可以使用基本上不含银的管芯附着材料附着到子模块14的功率电子衬底，再次减少银朝向位于管芯上的一个或多个触点的电迁移。类似地，每个子模块14可以使用基本上不含银的衬底附着材料附着到基板12，并且子模块14中的功率电子衬底可以基本上不含银。第五，电源模块10在组装后可以经受严格的清洁过程，以减少位于电源模块10上的污染物，这些污染物可能在电源模块10的操作期间导致腐蚀。最后，可以基于离子色谱测试来选择为电源模块10选择的材料，离子色谱测试需要材料中极低水平的污染物，因为这些污染物会在电源模块10操作期间导致腐蚀。
以这种方式提供电源模块10，可以允许电源模块10通过温度、湿度和偏压(THB)测试，该测试在其额定阻断电压的80％下操作(即THB80测试)超过1000小时、1500小时甚至2000小时。如本文所讨论的，“通过”THB测试需要将至少两个端子之间的漏电流保持在阈值以下，同时保持这些端子上的电压。在一个实施方式中，泄漏电流的阈值低于20mA。值得注意的是，电源模块10整体能够通过该测试，而不仅仅是电源模块10中的半导体管芯16。在各种实施方式中，可以仅在第一MOSFET Q1和第一二极管D1或者第二MOSFET Q2和第二二极管D2中的一个上执行THB测试。在电源模块10是如上所述的1.2kV电源模块的实施方式中，可以在第二端子18B和第三端子18C之间设置1.2kV或960V的80％。在测试期间，第一端子18A可以耦合到第二端子18B，使得第一MOSFET Q1和第一二极管D1短路。此外，第一控制端子20A可以耦合到第二端子18B，第二控制端子20B可以耦合到第三端子18C。结果是第一MOSFETQ1和第一二极管D1短路，而第二MOSFET Q2处于前向阻断配置，第二二极管D2处于反向偏置配置。电源模块10可以设置在温度至少为85℃且相对湿度至少为85％的环境中。由于上述增加电源模块10的耐用性的额外特征，在各种实施方式中，电源模块10能够保持上述状态超过1000小时、超过1500小时、甚至超过2000小时。
图4示出了通过图1中的线A-A’的电源模块10的横截面。如图4所示，电源模块10包括基板12、子模块14中的一个、以及所述子模块14中的一个上的多个半导体管芯16。子模块14包括其上设置有半导体管芯16的功率电子衬底30。该功率电子衬底30又位于基板12上。功率电子衬底30可以包括多层，例如，第一导电层32A、第一导电层32A上的绝缘层32B和绝缘层32B上的第二导电层32C。如上所述，可以选择功率电子衬底30，使得其基本上不含银，以便降低从其向半导体管芯16的一个或多个触点的电迁移的可能性，电迁移可能导致短路，从而导致其灾难性故障。因此，在一些实施方式中，功率电子衬底30可以是直接键合铜(DBC)衬底，其中，第一导电层32A和第二导电层32C是铜，绝缘层32B是陶瓷材料，例如，三氧化二铝(Al2O3)、氧化铝(AlO)、氮化铝(AlN)和氮化硅(SiN)。功率电子衬底30经由衬底附着材料34附着到基板12，如上所述，在各种实施方式中，衬底附着材料34也可以基本上不含银。具体地，衬底附着材料34可以是包含锡和锑的焊料材料。半导体管芯16经由管芯附着材料36附着到功率电子衬底30，如上所述，在各种实施方式中，管芯附着材料36也可以基本上不含银。具体地，管芯附着材料36可以是包含锡和锑的焊料材料。值得注意的是，存在许多基本上不含银的其它焊接材料，例如，包括锡和铅的焊接材料、包括锡、铜和金的焊接材料等，所有这些都在本文中考虑。
如上所述，通过从电源模块10中消除银，消除了否则可能发生的电迁移。因此，类似地消除了与所述电迁移相关联的短路和其他故障，从而如上所述显著增加了电源模块10的耐用性。虽然银和其他金属(例如，镍)的电迁移是封装领域中众所周知的现象，但是发明人在制造电源模块10的过程中发现，可以显著降低包括SiC半导体管芯的电源模块的耐用性。这是由于功率密度以及SiC半导体管芯提供的高电场，这导致电迁移超过了先前认为在电迁移方面相当安全的距离(例如，在μm的尺度上)。换言之，由于由此提供较低的电场，在包括硅(Si)半导体管芯的电源模块中没有观察到这样的问题，因此不需要这样的解决方案。
除了上面讨论的模块级改进之外，在每个半导体管芯16上也进行了改进。因此，图5示出了根据本公开的一个实施方式的一个半导体管芯16的剖视图。半导体管芯16包括衬底40和衬底40上的漂移层42。背面金属化层44位于与漂移层42相对的衬底40上。正面金属化层46位于与衬底40相对的漂移层42上。钝化层堆叠48位于正面金属化层46和漂移层42之上。封装层50位于钝化层堆叠48之上。虽然未示出以避免模糊附图，但是在漂移层42的有源区域56中形成多个器件。这些器件可以包括多个MOSFET单元或多个二极管单元，这将被本领域技术人员所理解并在下面详细讨论。可以在半导体管芯16的边缘区域58中提供多个用于场终止的保护环植入54。切割片60也可以设置在边缘区域58的最外面部分，其中，半导体管芯16与晶片分离。
衬底40和漂移层42可以是SiC层。封装层50可以包括聚酰亚胺或任何其他合适的封装剂。保护环植入54可以通过离子植入工艺设置在漂移层42中，因此可以是漂移层42的相反导电类型。
半导体管芯16的显著改进包括钝化层堆叠48、为背面金属化层44选择的材料以及从半导体管芯16的正面去除镍。钝化层堆叠48包括多个钝化层52，如附图的分解部分所示。值得注意的是，多个钝化层52是交替层。即，钝化层52中的第一个具有第一成分，钝化层52中的第二个具有不同于第一成分的第二成分，并且这些层如图所示交替。在一个实施方式中，钝化层52在氮化硅(SiN)、二氧化硅(SiO2)和氮氧化硅(SiON)之间交替。此外，钝化层52可以以图案而不是交替的方式提供，使得每个第三层、每个第四层等是不同的成分，或者使得材料成分以重复的方式在三种或更多种材料之间变化。以这种方式交替或图案化钝化层52，确保在这些层的沉积中出现的任何缺陷被具有不同成分的后续层中断。因此，针孔和裂纹不能通过整个钝化层堆叠48形成，从而保护半导体管芯16的下面部分免受腐蚀和分层。此外，提供几个钝化层52，增加了钝化层堆叠48的总厚度，这提供了额外的环境保护，并允许多个钝化层52分层或以其他方式受损，而不会导致半导体管芯16的故障。在一个实施方式中，钝化层堆叠48具有至少1.6μm的厚度。在各种实施方式中，钝化层堆叠48的厚度可以在1.6μm和10μm之间。具体地，钝化层堆叠48可以具有至少2.0μm的厚度、至少2.5μm的厚度和至少3.0μm的厚度。此外，钝化层堆叠48可以包括至少五个钝化层52、至少七个钝化层52、至少九个钝化层52、至少十五个钝化层52、至少二十个钝化层52以及多达数百个钝化层52，而不背离本公开的原理。钝化层堆叠48中钝化层52的厚度可以相同，或者可以以任何期望的图案变化。如上所述提供钝化层堆叠48，可以显著增加电源模块10的耐用性。
在制造电源模块10时，发明人发现使用PECVD工艺提供钝化层52可以增加钝化层52的密度和保护质量。然而，在不脱离本公开的原理的情况下，其他制造工艺(例如，溅射)也可以用于钝化层52。
选择背面金属化层44，以便基本上不含银。通常，用于功率器件的半导体管芯中的背面金属化层包括锡、镍和银。然而，如上所述，发明人在制造电源模块10时发现，当使用SiC半导体器件时，银的电迁移带来了很大的风险，即使在较大的距离上，先前认为这种现象是安全的。因此，在一个实施方式中，电源模块10中的半导体管芯16的背面金属化层44被选择为锡、镍和金。如上所述，从背面金属化层44去除银，可以显著增加电源模块10的耐用性。因为正面金属化层46通常首先不包括银，所以与用于电源模块的传统半导体管芯相比，其材料没有改变。然而，应当注意，在器件的正面也应避免使用银。在一个实施方式中，正面金属化层包括铝，并且可以包括钛粘合层。在另一实施方式中，正面金属化层包括具有第一层钛和第二层(包括铝、镍和金)的金属叠层。
为了改善某些情况下的性能，先前已经在切割片60中设置了接地环。在这些情况下，发明人发现，当位于器件的正面时，镍(镍是这种应用中的优选金属)也易于向半导体管芯16的一个或多个触点电迁移。因此，如果在半导体管芯16(未示出)中使用接地环，则接地环应该不含银和镍，以防止其向半导体管芯16的一个或多个触点电迁移，从而防止管芯故障。
图6A示出了根据本公开的一个实施方式的MOSFET单元62的剖视图。如上所述，这种MOSFET单元62可以与一个半导体管芯16中的许多相同单元一起形成。MOSFET单元62包括衬底40、漂移层42、背面金属化层44、正面金属化层46、钝化层堆叠48和封装层50。此外，MOSFET单元62在漂移层42和位于正面金属化层46的一部分和漂移层42之间的氧化物层66中包括多个植入物64。如图所示，背面金属化层44形成MOSFET单元62的漏极触点68，而正面金属化层46形成MOSFET单元62的源极触点70和栅极触点72。
图6B示出了根据本公开的一个实施方式的二极管单元74的剖视图。如上所述，这种二极管单元74可以与一个半导体管芯16中的许多相同单元一起形成。二极管单元74包括衬底40、漂移层42、背面金属化层44、正面金属化层46、钝化层堆叠48和封装层50。此外，二极管单元74包括漂移层42中的多个植入物76。如图所示，背面金属化层44形成二极管单元74的阴极触点78，正面金属化层46形成二极管单元74的阳极触点80。
图7是示出根据本公开的一个实施方式的用于制造电源模块10的方法的流程图。首先，通过提供半导体衬底(步骤100)和在半导体衬底上制造器件(例如，MOSFET和/或二极管)(步骤102)来制造半导体管芯。在半导体衬底上制造器件(例如，MOSFET和二极管)的工艺是众所周知的，因此在本文不再讨论。然而，在其制造过程中提供上述半导体管芯的显著改进(即背面金属化层和接地环的改进)。接下来，在半导体衬底上制造的半导体器件上提供钝化层堆叠(步骤104)。如上所述，钝化层堆叠显著提高了半导体管芯的耐用性，从而提高了所得电源模块的耐用性。半导体衬底然后分割成分立半导体管芯(步骤106)，该管芯可以设置在电源模块中。半导体管芯安装在功率电子衬底上，以形成子模块(步骤108)。如上所述，使用基本上不含银的管芯附着材料，将半导体管芯安装在功率电子衬底上。此外，功率电子衬底本身基本上不含银。
接下来，将子模块安装到基板上(步骤110)。如上所述，使用基本上不含银的衬底附着材料将子模块安装到基板上。然后，清洁制造的电源模块(步骤112)。具体地，电源模块经受严格的清洁，其中，从其所有表面去除诸如氟、乙酸盐、甲酸盐、氯化物、亚硝酸盐、硝酸盐、磷酸盐、硫酸盐、弱有机酸、锂、钠、铵、钾、钙、镁、溴化物等污染物。在一个实施方式中，清洁提供低于0.5μg/in2水平的污染物。在各种实施方式中，清洁足以确保这些污染物中的一种或多种的水平低于0.4μg/in2、低于0.3μg/in2、低于0.2μg/in2、甚至低于0.1μg/in2。在制造电源模块10时，发明人发现这些低污染水平对于避免腐蚀和在上述THB80测试期间导致电源模块10故障的其他问题是必要的。然后，电源模块设置在外壳中，并且在一些实施方式中，外壳填充有灌封材料，例如，硅胶(步骤114)。
在各种实施方式中，基于离子色谱法，选择为电源模块10选择的所有材料，包括基板12、功率电子衬底30、衬底附接材料34、管芯附接材料36以及靠近或接触半导体管芯的任何其他材料(例如，当电源模块10设置在外壳中时，上述围绕电源模块10设置的硅胶)，使得其中的某些污染物显著低于当前业界公认的标准。当使用根据业界标准选择的材料时，发明人发现，甚至这些标准允许的推荐的低水平污染物也足以在上述THB80测试期间引起腐蚀和其他缺陷。因此，发明人发现，与电源模块10中的有源电流路径接触的所有材料应该具有低于0.5μg/in2的污染物水平，例如，氟、乙酸盐、甲酸盐、氯化物、亚硝酸盐、硝酸盐、磷酸盐、硫酸盐、弱有机酸、锂、钠、铵、钾、钙、镁和溴化物。在各种实施方式中，这些污染物中的一种或多种的水平被选择为低于0.4μg/in2、低于0.3μg/in2、低于0.2μg/in2、甚至低于0.1μg/in2。在业界标准允许相同的污染物水平在某些情况下高达6μg/in2的情况下，发明人再次发现这些值太高，不能提供电源模块10的期望耐用性。
本领域技术人员将认识到对本公开的优选实施方式的改进和修改。所有这些改进和修改都被认为在本文公开的概念和随后的权利要求的范围内。

Claims (25)

1.一种电源模块，包括：
第一端子和第二端子；
多个碳化硅(SiC)半导体管芯，耦合在所述第一端子和所述第二端子之间，多个所述半导体管芯被配置为使得所述电源模块：
在前向导通操作模式期间，为从所述第一端子到所述第二端子的电流流动提供低电阻路径，使得所述第一端子和所述第二端子之间的电阻小于100mΩ；并且
在前向阻断操作模式期间，为从所述第一端子到所述第二端子的电流流动提供高电阻路径，使得当在所述第一端子和所述第二端子上提供电源模块的额定电压的至少80％的电压时，所述第一端子和所述第二端子之间的泄漏电流小于20mA，其中，所述电源模块的额定电压至少为600V，并且所述电源模块能够在至少85℃的温度和至少85％的相对湿度下在至少1000小时的周期内在第一端子和第二端子上无故障地保持额定电压的至少80％的电压。
2.根据权利要求1所述的电源模块，其中，多个所述半导体管芯中的每一个包括：
衬底；
所述衬底上的漂移层；以及
所述漂移层上的钝化层堆叠，所述钝化层堆叠包括至少四个钝化层，使得所述至少四个钝化层的成分在至少第一材料和第二材料之间交替。
3.根据权利要求2所述的电源模块，其中，所述第一材料和所述第二材料是氮化硅(SiN)、二氧化硅(SiO2)和氮氧化硅(SiON)中的不同材料。
4.根据权利要求2所述的电源模块，其中，所述钝化层堆叠具有至少1.6μm的厚度。
5.根据权利要求2所述的电源模块，其中，多个所述半导体管芯中的每一个还包括所述衬底上与所述漂移层相对的背面金属化层，使得所述背面金属化层基本上不含银。
6.根据权利要求5所述的电源模块，还包括功率电子衬底，多个所述半导体管芯经由管芯附着材料安装在所述功率电子衬底上，其中，所述功率电子衬底和所述管芯附着材料基本上不含银。
7.根据权利要求2所述的电源模块，还包括功率电子衬底，多个所述半导体管芯经由管芯附着材料安装在所述功率电子衬底上，其中，所述功率电子衬底和所述管芯附着材料基本上不含银。
8.根据权利要求1所述的电源模块，其中，多个所述半导体管芯中的每一个包括：
衬底；
所述衬底上的漂移层；以及
所述衬底上与所述漂移层相对的背面金属化层，其中，所述背面金属化层基本上不含银。
9.根据权利要求8所述的电源模块，其中，
金属氧化物半导体场效应晶体管MOSFET形成在多个半导体管芯中的至少一个的漂移层中；并且
所述背面金属化层提供所述MOSFET的漏极触点。
10.根据权利要求9所述的电源模块，其中，
肖特基二极管形成在多个所述半导体管芯中的至少一个的漂移层中；并且
所述背面金属化层提供肖特基二极管的阳极触点。
11.根据权利要求8所述的电源模块，其中，
肖特基二极管形成在多个所述半导体管芯中的至少一个的漂移层中；并且
所述背面金属化层提供肖特基二极管的阳极触点。
12.根据权利要求8所述的电源模块，其中，所述背面金属化层包括锡、镍和金。
13.根据权利要求8所述的电源模块，其中，多个所述半导体管芯中的每一个还包括与所述衬底相对的漂移层上的正面金属化层，其中，所述正面金属化层包括第一层钛和在所述第一层上包含铝、镍和金的第二层。
14.根据权利要求1所述的电源模块，还包括功率电子衬底，其中，多个所述半导体管芯安装在所述功率电子衬底上。
15.根据权利要求14所述的电源模块，其中，所述功率电子衬底基本上不含银。
16.根据权利要求15所述的电源模块，其中，所述功率电子衬底是直接键合铜(DBC)功率电子衬底。
17.根据权利要求15所述的电源模块，其中，多个所述半导体管芯被使用基本上不含银的管芯附着材料安装在所述功率电子衬底上。
18.根据权利要求17所述的电源模块，其中，所述管芯附着材料包括锡和锑。
19.根据权利要求14所述的电源模块，其中，多个所述半导体管芯被使用基本上不含银的管芯附着材料安装在所述功率电子衬底上。
20.根据权利要求19所述的电源模块，其中，所述管芯附着材料包括锡和锑。
21.根据权利要求19所述的电源模块，还包括基板，所述电源电子衬底安装在所述基板上，其中，所述电源电子衬底被使用基本上不含银的衬底附着材料安装在所述基板上。
22.根据权利要求1所述的电源模块，其中，
在前向导通操作模式期间，所述第一端子和所述第二端子之间的电阻至少为0.1mΩ；并且
在前向阻断操作模式期间，所述第一端子和所述第二端子之间的漏电流大于0.1mA。
23.根据权利要求1所述的电源模块，其中，多个所述半导体管芯中的每一个包括：
衬底；
所述衬底上的漂移层；以及
所述漂移层上的钝化层堆叠，所述钝化层堆叠包括至少四个钝化层。
24.根据权利要求23所述的电源模块，其中，所述钝化层堆叠具有至少1.6μm的厚度。
25.根据权利要求1所述的电源模块，其中，多个所述半导体管芯中的每一个包括：
衬底；
所述衬底上的漂移层；以及
所述漂移层上的钝化层堆叠，所述钝化层堆叠包括氮化硅(SiN)、二氧化硅(SiO2)和氮氧化硅(SiON)的至少四个交替层。
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