CN110531246B - Method for rapidly finding electrostatic weak link through grid method - Google Patents
Method for rapidly finding electrostatic weak link through grid method Download PDFInfo
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- CN110531246B CN110531246B CN201910736475.XA CN201910736475A CN110531246B CN 110531246 B CN110531246 B CN 110531246B CN 201910736475 A CN201910736475 A CN 201910736475A CN 110531246 B CN110531246 B CN 110531246B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
- G01R31/2817—Environmental-, stress-, or burn-in tests
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Abstract
The invention provides a method for quickly finding out an electrostatic weak link by a grid method, which comprises the following steps: s1: dividing the PCB into m areas; s2: removing green oil from each area; s3: testing the highest voltage that each area can pass; s4: determining the lowest voltage value as an electrostatic weak area; s5: dividing the electrostatic weak area into a areas; s6: testing the highest voltage that can be passed by each area on the electrostatically weakened zone; s7: determining the lowest voltage value as the electrostatic sub-weak area; s8: and repeating the steps S5, S6 and S7 until the electrostatic weakest area of the minimum unit is found. The method has the characteristics of simple operation, no need of adding redundant ESD elements, capability of reducing the circuit cost, capability of saving development time, and capability of quickly and accurately finding weak links and quickly finding electrostatic weak links in the system working state.
Description
Technical Field
The invention relates to the field of circuit boards of electronic products, in particular to a method for quickly finding out a weak electrostatic link by a grid method.
Background
In electronic products, such as smart televisions, set-top boxes, smart sound boxes and the like, the problem of Electro-Static discharge (ESD) is a difficult problem in the industry, the smaller the PCB is, the greater the difficulty is, and the difficulty of ESD problems of two layers of PCBs is greater than that of four layers of boards, which is why the industry does not have two layers of small-sized PCBs basically. Therefore, it is the most critical challenge to accurately find the weakest point of the ESD problem at the chip level and the PCB level.
In the prior art, there are two common approaches in the industry: 1. the shielding cover is directly added for solving the problem; 2. weak terminals are found by punching the terminals and then processing by adding devices to the terminals.
However, both of these approaches are cumbersome, require the addition of redundant ESD components, result in increased cost, and fail to quickly find electrostatic weaknesses in system operation.
Disclosure of Invention
In order to solve the problems, the invention provides a method for quickly finding out a weak electrostatic link through a grid method, which has the characteristics of simple operation and capability of reducing the circuit cost and can quickly find out the weak electrostatic link in the working state of a system.
The invention is realized by the following technical scheme:
the invention provides a method for quickly finding out an electrostatic weak link by a grid method, which comprises the following steps:
s1: dividing the PCB into M areas according to a grid pattern mode, wherein M is more than or equal to 2, and marking each divided area as M1, M2, … … Mm;
s2: green oil of each area on the PCB is removed;
s3: respectively contacting and discharging each area on the PCB by using an electrostatic gun, and testing the highest voltage which can pass through each area;
s4: determining the lowest voltage value as an electrostatic weak area by comparing the highest voltage which can pass through each area, and recording the lowest voltage value as Mmin;
s5: dividing the electrostatic weak area Mmin into a areas according to a grid mode, wherein a is more than or equal to 2, and marking each divided area as A1, A2 and … … Aa;
s6: respectively contacting and discharging each area on the electrostatic weak area Mmin by using an electrostatic gun, and testing the highest voltage which can pass through each area;
s7: determining the lowest voltage value as an electrostatic weak area by comparing the highest voltage which can pass through each area, and recording the lowest voltage value as Amin;
s8: and repeating the steps S5, S6 and S7 until the electrostatic weakest area of the minimum unit is found.
Preferably, in the step S1, each of the m regions is equal in size.
Preferably, in the step S5, each of the a regions is equal in size.
The invention has the beneficial effects that:
the method for quickly finding the electrostatic weak link through the grid method has the characteristics of simple operation, no need of adding redundant ESD elements, capability of reducing the circuit cost, capability of saving development time, quick and accurate finding of the weak link and capability of quickly finding the electrostatic weak link in the system working state.
Drawings
FIG. 1 is a schematic diagram of a region division method in the method for rapidly finding electrostatic weak links by a grid method according to the present invention;
fig. 2 is a schematic diagram of a region division method in the method for rapidly finding the electrostatic weak link by the grid method of the present invention.
Detailed Description
In order to more clearly and completely explain the technical scheme of the invention, the invention is further explained with reference to the attached drawings.
Referring to fig. 1-2, the present invention provides a method for quickly finding a weak link of static electricity by a grid method, comprising the following steps:
s1: dividing the PCB into M areas according to a grid pattern mode, wherein M is more than or equal to 2, and marking each divided area as M1, M2, … … Mm;
s2: green oil of each area on the PCB is removed;
s3: respectively contacting and discharging each area on the PCB by using an electrostatic gun, and testing the highest voltage which can pass through each area;
s4: determining the lowest voltage value as an electrostatic weak area by comparing the highest voltage which can pass through each area, and recording the lowest voltage value as Mmin;
s5: dividing the static weak area Mmin into a areas according to a grid mode, wherein a is more than or equal to 2, and marking each divided area as A1, A2 and … … Aa;
s6: respectively contacting and discharging each area on the electrostatic weak area Mmin by using an electrostatic gun, and testing the highest voltage which can pass through each area;
s7: determining the lowest voltage value as a static sub-weak area by comparing the highest voltage which can pass through each area, and recording the lowest voltage value as Amin;
s8: and repeating the steps S5, S6 and S7 until the electrostatic weakest area of the minimum unit is found.
In the present embodiment, the PCB is divided into 4 areas having equal areas in a grid pattern.
In this embodiment, the steps in S3 and S4 are specifically: and respectively contacting and discharging each area on the PCB by using an electrostatic gun, continuously discharging each area for more than 30 times, repeating for 3 times, and assuming that the contact test voltage of 1, 2 and 4 areas can pass through 3KV and the contact test voltage of 3 areas can not pass through 2.5KV, indicating that the weakest area is 3 areas.
In the present embodiment, it is noted that: when there are DDR and FLASH signal lines in the area, the electrostatic gun cannot directly contact the DDR and FLASH signal lines, so that the distance between the electrostatic gun and the DDR and FLASH signal lines is 3mm, and then the discharge voltage measurement is started.
In this embodiment, the weakest area of the minimum unit is an electronic component on the PCB, such as a capacitor or a resistor.
Preferably, in the step S1, each of the m regions is equal in size.
Preferably, in the step S5, each of the a regions is equal in size.
According to the method for quickly finding the electrostatic weak link through the grid method, the method has the characteristics of simplicity in operation, no need of adding redundant ESD elements, capability of reducing the circuit cost, capability of saving development time, quickly and accurately finding the weak link, and capability of quickly finding the electrostatic weak link in the system working state.
Of course, the present invention may have other embodiments, and based on the embodiments, those skilled in the art can obtain other embodiments without any creative effort, and all of them are within the protection scope of the present invention.
Claims (3)
1. A method for rapidly finding an electrostatic weak link by a grid method is characterized by comprising the following steps:
s1: dividing the PCB into M areas according to a grid pattern mode, wherein M is more than or equal to 2, and marking each divided area as M1, M2, … … Mm;
s2: green oil of each area on the PCB is removed;
s3: respectively contacting and discharging each area on the PCB by using an electrostatic gun, and testing the highest voltage which can pass through each area;
s4: determining the lowest voltage value as an electrostatic weak area by comparing the highest voltage which can pass through each area, and recording the lowest voltage value as Mmin;
s5: dividing the electrostatic weak area Mmin into a areas according to a grid mode, wherein a is more than or equal to 2, and marking each divided area as A1, A2 and … … Aa;
s6: respectively contacting and discharging each area on the electrostatic weak area Mmin by using an electrostatic gun, and testing the highest voltage which can pass through each area;
s7: determining the lowest voltage value as an electrostatic weak area by comparing the highest voltage which can pass through each area, and recording the lowest voltage value as Amin;
s8: and repeating the steps S5, S6 and S7 until the electrostatic weakest area of the minimum unit is found.
2. The method for rapidly finding an electrostatic weak link through the palace method according to claim 1, wherein in the step S1, each of the m regions is equal in size.
3. The method for rapidly finding an electrostatic weak link through the palace method as claimed in claim 1, wherein in the step S5, each of the a regions is equal in size.
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| CN201910736475.XA CN110531246B (en) | 2019-08-09 | 2019-08-09 | Method for rapidly finding electrostatic weak link through grid method |
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| CN201910736475.XA CN110531246B (en) | 2019-08-09 | 2019-08-09 | Method for rapidly finding electrostatic weak link through grid method |
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| CN110531246B true CN110531246B (en) | 2022-11-11 |
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| JP2007073838A (en) * | 2005-09-08 | 2007-03-22 | Matsushita Electric Ind Co Ltd | Method of analyzing electrostatic noise tolerance of semiconductor integrated circuit device, and method of optimizing design of the semiconductor integrated circuit device using the same |
| JP2010008149A (en) * | 2008-06-25 | 2010-01-14 | Panasonic Corp | Inspection region setting method |
| CN101398460B (en) * | 2008-10-16 | 2013-05-22 | 北京中星微电子有限公司 | Debugging method for chip electro-static discharge test after failure and device |
| US9222777B2 (en) * | 2012-09-07 | 2015-12-29 | The United States Post Office | Methods and systems for creating and using a location identification grid |
| CN103457279A (en) * | 2013-09-23 | 2013-12-18 | 广东电网公司电力调度控制中心 | Determination method for partition D-STATCOM integrated optimization configuration scheme of large-scale power grid |
| CN104678270B (en) * | 2015-03-19 | 2017-06-16 | 工业和信息化部电子第五研究所 | The method and system of monitoring transmission line pulse electrostatic discharge testing response |
| CN105372506B (en) * | 2015-10-30 | 2018-01-02 | 中国电子科技集团公司第二十九研究所 | A kind of mutative scale gridding method calculated for region electromagnetic environment and system |
| CN107238769A (en) * | 2017-05-31 | 2017-10-10 | 晶晨半导体(上海)股份有限公司 | A kind of method of the Electro-static Driven Comb ability of analysis chip cabling |
| CN108267655A (en) * | 2018-01-15 | 2018-07-10 | 郑州云海信息技术有限公司 | A kind of device and method for assessing electrostatic discharge susceptivity power |
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