CN110429099B - Manufacturing method of high-brightness composite substrate - Google Patents
Manufacturing method of high-brightness composite substrate Download PDFInfo
- Publication number
- CN110429099B CN110429099B CN201910742941.5A CN201910742941A CN110429099B CN 110429099 B CN110429099 B CN 110429099B CN 201910742941 A CN201910742941 A CN 201910742941A CN 110429099 B CN110429099 B CN 110429099B
- Authority
- CN
- China
- Prior art keywords
- coating
- metal
- sapphire
- composite substrate
- sio
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 33
- 239000002131 composite material Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000011248 coating agent Substances 0.000 claims abstract description 64
- 238000000576 coating method Methods 0.000 claims abstract description 64
- 239000002184 metal Substances 0.000 claims abstract description 50
- 229910052751 metal Inorganic materials 0.000 claims abstract description 49
- 229910052594 sapphire Inorganic materials 0.000 claims abstract description 46
- 239000010980 sapphire Substances 0.000 claims abstract description 46
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 39
- 238000005530 etching Methods 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims abstract description 19
- 230000004888 barrier function Effects 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 18
- 229910052681 coesite Inorganic materials 0.000 claims description 13
- 229910052906 cristobalite Inorganic materials 0.000 claims description 13
- 239000000377 silicon dioxide Substances 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052682 stishovite Inorganic materials 0.000 claims description 13
- 229910052905 tridymite Inorganic materials 0.000 claims description 13
- 238000004140 cleaning Methods 0.000 claims description 12
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 6
- 239000008367 deionised water Substances 0.000 claims description 6
- 229910021641 deionized water Inorganic materials 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 6
- 239000001307 helium Substances 0.000 claims description 6
- 229910052734 helium Inorganic materials 0.000 claims description 6
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 6
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 238000001035 drying Methods 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 229910052742 iron Inorganic materials 0.000 claims description 3
- 239000011259 mixed solution Substances 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052763 palladium Inorganic materials 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000011247 coating layer Substances 0.000 claims description 2
- 239000012535 impurity Substances 0.000 claims description 2
- 239000010432 diamond Substances 0.000 claims 1
- 239000004575 stone Substances 0.000 claims 1
- 238000005406 washing Methods 0.000 claims 1
- 229910004298 SiO 2 Inorganic materials 0.000 abstract 3
- 230000000903 blocking effect Effects 0.000 abstract 1
- 239000007769 metal material Substances 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000005381 potential energy Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/85—Packages
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/85—Packages
- H10H20/855—Optical field-shaping means, e.g. lenses
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
- H10H29/10—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00
- H10H29/14—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00 comprising multiple light-emitting semiconductor components
- H10H29/142—Two-dimensional arrangements, e.g. asymmetric LED layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/01—Manufacture or treatment
- H10H20/036—Manufacture or treatment of packages
- H10H20/0363—Manufacture or treatment of packages of optical field-shaping means
Landscapes
- Led Devices (AREA)
Abstract
本发明公开了一种高亮度复合衬底的制作方法，主要包括以下步骤：在蓝宝石平片上沉积一层金属涂层；在金属涂层上涂覆一层正性光刻胶涂层，并曝光、显影选择性的去除不需要的部分在金属涂层上形成一组正性光刻胶柱；以正性光刻胶柱作为阻挡层进行ICP刻蚀，在蓝宝石平片上形成一组相互独立的金属凸台；利用化学气相沉积方法在蓝宝石平片有金属凸台的一面沉积一层SiO2涂层；在SiO2涂层上涂覆一层负性光刻胶涂层，并曝光、显影选择性的去除不需要的部分，从而在SiO2涂层上形成一组负性光刻胶柱；以负性光刻胶柱和SiO2涂层作为阻挡层进行ICP刻蚀，从而得到一种高亮度复合衬底。本发明通过蓝宝石、金属涂层和SiO2形成复合衬底，能够显著提高LED芯片的亮度。
The invention discloses a manufacturing method of a high-brightness composite substrate, which mainly comprises the following steps: depositing a layer of metal coating on a sapphire flat plate; coating a layer of positive photoresist coating on the metal coating, and exposing , The development selectively removes the unwanted parts and forms a group of positive photoresist columns on the metal coating; uses the positive photoresist columns as the blocking layer to carry out ICP etching, and forms a set of mutually independent on the sapphire flat wafer. Metal boss; use chemical vapor deposition method to deposit a layer of SiO 2 coating on the side of the sapphire flat plate with metal boss; apply a layer of negative photoresist coating on the SiO 2 coating, and choose exposure and development The undesired parts are removed effectively, thereby forming a set of negative photoresist pillars on the SiO coating ; ICP etching is performed with the negative photoresist pillars and the SiO coating as barrier layers, resulting in a high Brightness composite substrate. The present invention forms a composite substrate through sapphire, metal coating and SiO 2 , which can significantly improve the brightness of the LED chip.
Description
Technical Field
The invention relates to the field of manufacturing of LED substrates, in particular to a manufacturing method of a high-brightness composite substrate.
Background
As is well known, a PSS (patterned sapphire substrate) is located in an upstream process in the LED display industry, plays a crucial role, and can effectively reduce the dislocation density of a GaN epitaxial material, thereby reducing non-radiative recombination in an active region, reducing reverse leakage current, improving the service life of an LED, and other advantages. At present, micro-nano patterned sapphire substrate technology is generally adopted, conical patterns which are arranged periodically are manufactured on the surface of an epitaxial sapphire substrate, and epitaxial growth parameters are controlled to grow GaN with higher quality by utilizing the characteristic of high potential energy of conical inclined planes on the sapphire patterned substrate. However, with the rapid development of the LED display industry, the consumer market has higher and higher requirements for product quality and brightness, and the brightness of the conventional micro-nano patterned sapphire substrate LED chip is a bottleneck in the prior art, which is a revolutionary breakthrough if the brightness can be improved by more than about 2%.
Along with high requirements of the consumer market, the conventional micro-nano patterned sapphire substrate is difficult to meet the requirements, so that a new sapphire substrate preparation method must be adopted to meet the requirements of people from the aspects of materials and structures.
Disclosure of Invention
The invention aims to provide a manufacturing method of a high-brightness composite substrate, which is used for further improving the brightness of a sapphire substrate.
The technical scheme adopted by the invention for solving the technical problems is as follows: a method for manufacturing a high-brightness composite substrate comprises the following steps:
(1) firstly, selecting a flat sapphire sheet with a smooth surface and two polished surfaces, and cleaning to remove impurities on the surface;
(2) a layer of metal coating is vapor-plated on the sapphire flat sheet;
(3) coating a positive photoresist coating on the metal coating, and selectively removing unnecessary parts by exposure and development to form a group of positive photoresist columns on the metal coating;
(4) carrying out ICP etching by taking the positive photoresist column as a barrier layer, and forming a group of mutually independent metal bosses on the sapphire flat sheet;
(5) depositing a layer of SiO on the surface of the sapphire flat sheet with the metal boss by using a chemical vapor deposition method2Coating;
(6) in SiO2Coating a negative photoresist layer on the coating layer, exposing and developing to selectively remove the undesired portions, thereby forming a SiO layer2Forming a group of negative photoresist columns on the coating;
(7) with negative photoresist posts and SiO2The coating is used as a barrier layer to carry out ICP etching, thereby obtaining the high-brightness composite liningAnd (4) bottom.
In order to ensure clean cleaning, the sapphire plain film in the step (1) is firstly scrubbed by acetone for 5-10 minutes and then subjected to concentrated H at 90 DEG C2SO4And H2O2Cleaning for 10-15 minutes in a mixed solution with a volume ratio of 3:1 or 5:2, cleaning for 8-10 minutes by using 80 ℃ deionized water, finally cleaning for 5-10 minutes by using 25 ℃ deionized water, and then spin-drying for 3-10 minutes at a high speed.
Preferably, the thickness of the metal coating in the step (2) is 5-1000 nm, and the metal is one or a mixture of Au, Ag, Ni, Co, Fe, Cu, Pt, Pd and Al.
Preferably, the film thickness of the positive photoresist coating in the step (3) is 0.5-3.0 μm, and the exposure time is 50-400 ms.
Specifically, in the step (4), ICP etching is to send the developed sapphire flat sheet into an etching machine for plasma dry etching, the power of an upper electrode of the etching machine is set to be 100-2000W, the power of a lower electrode of the etching machine is set to be 100-1500W, and BCL (bulk continuous plasma etching) is set3Flow rate of 50-200 sccm, CHF3The flow is 0-20 sccm, the etching temperature is 10-50 ℃, the helium pressure is 1-10 mTorr, and the time is 100-1000 s.
Preferably, SiO in the step (5)2The thickness is 0.5-2.0 μm, and the temperature of the chemical vapor deposition chamber is 100-500 ℃.
Preferably, in the step (6), the thickness of the negative photoresist coating is 0.5-3.0 μm, the sapphire plain film is exposed from the other surface of the sapphire plain film opposite to the surface with the metal boss, the metal boss replaces a photoetching plate to be used as a shield for exposure, the exposure time is 3-20 s, and the photoresist at the position where the metal boss is not shielded is removed during development.
Specifically, in the step (7), ICP etching is to send the developed sapphire flat sheet into an etching machine for plasma dry etching, the power of an upper electrode of the etching machine is set to be 100-2000W, the power of a lower electrode of the etching machine is set to be 100-1500W, and BCL (bulk continuous plasma etching) is set3Flow rate of 50-200 sccm, CHF3The flow is 0-20 sccm, the etching temperature is 10-50 ℃, the helium pressure is 1-10 mTorr, and the time is 100-3000 s.
The invention has the beneficial effects that: the invention adopts sapphire, metal coating and SiO2The composite substrate is formed, and the brightness of the chip can be remarkably improved. Because the chemical property stability of the metal is relatively poor, a layer of SiO is wrapped on the metal2The coating can effectively avoid the defect that metal is easy to oxidize. The bottom metal coating effectively reduces light refraction and increases light reflection efficiency, and SiO2The refractive index of 1.45 is less than that of 1.76 of sapphire, so that the scattering effect of the substrate on light can be effectively improved, and the luminous efficiency of the LED chip is further improved. Compared with the LED chip using the traditional patterned sapphire substrate, the brightness of the LED chip is improved by more than 5 percent.
The invention will be explained in more detail below with reference to the drawings and examples.
Drawings
FIG. 1 is a process flow diagram of the present invention.
FIG. 2 is a schematic cross-sectional view of a sapphire flat sheet after deposition of a metal coating in accordance with the present invention.
FIG. 3 is a schematic cross-sectional view of a positive photoresist coating applied over a metal coating in accordance with the present invention.
FIG. 4 is a schematic cross-sectional view of a positive photoresist column formed on a metal coating according to the present invention.
FIG. 5 is a schematic cross-sectional view of a metal mesa formed by ICP etching according to the present invention.
FIG. 6 shows the deposition of a layer of SiO on a metal bump according to the present invention2Schematic cross-sectional view of the coating.
FIG. 7 shows the present invention on SiO2A cross-sectional view of a negative photoresist coating applied over the coating.
Figure 8 is a schematic cross-sectional view of the present invention exposing and developing a negative photoresist coating.
FIG. 9 shows the present invention on SiO2A cross-sectional view of a set of negative photoresist pillars formed on the coating.
Fig. 10 is a schematic cross-sectional view of a high-brightness composite substrate of the present invention.
Detailed Description
An embodiment is a manufacturing method of a high-brightness composite substrate, a process flow is shown in fig. 1, and the specific manufacturing method comprises the following steps:
(1) firstly, a flat sapphire sheet 1 with a flat surface is provided, and the back surface of the flat sapphire sheet is light-permeable after double-sided polishing treatment. The sapphire plain film 1 is firstly scrubbed by acetone for 5-10 minutes and then subjected to concentrated H at 90 DEG C2SO4And H2O2Cleaning for 10-15 minutes in a mixed solution with a volume ratio of 3:1 or 5:2, cleaning for 8-10 minutes by using 80 ℃ deionized water, finally cleaning for 5-10 minutes by using 25 ℃ deionized water, and then spin-drying for 3-10 minutes at a high speed.
(2) The cleaned sapphire flat sheet 1 is placed in a cavity of an electron gun evaporation plating machine, a metal material used for film plating is bombarded by accelerated electrons, kinetic energy of the electrons is converted into heat energy to heat the metal material to 2000-6000 ℃ to evaporate the metal material, and then the metal material is plated on the surface of the sapphire flat sheet to prepare a layer of metal coating 2 with the thickness of 5-2000 nm, as shown in figure 2, wherein the metal coating 2 is made of one or a mixture of several metals of Au, Ag, Ni, Co, Fe, Cu, Pt, Pd and Al. The metal coating 2 may be formed by a plating process such as atomic layer deposition or sputtering.
(3) A positive photoresist coating 3 with the film thickness of 0.5-3.0 mu m is coated on the metal coating 2, as shown in figure 3, and then exposure treatment is carried out for 50-400 ms, the part which does not need to be exposed is shielded by a photoetching plate during exposure, and the positive photoresist coating is exposed from the upper part of the positive photoresist coating. The unwanted portions are then selectively removed by a developing process to form a set of positive photoresist pillars 4 on the metal coating, as shown in fig. 4.
(4) Feeding the developed sapphire flat sheet 1 into an etching machine to carry out plasma dry etching by taking the positive photoresist column 4 as a barrier layer, setting the power of an upper electrode of the etching machine to be 100-2000W, the power of a lower electrode of the etching machine to be 100-1500W, and carrying out BCL (bulk continuous plasma etching)3Flow rate of 50-200 sccm, CHF3The flow is 0-20 sccm, the etching temperature is 10-50 ℃, the helium pressure is 1-10 mTorr, the time is 100-1000 s, and the residual product is purged by argon after etching2、Ar、N2、C2H4And the main etching gas is not fixed as the same gas, and the corresponding main etching gas is used according to different metals, so that a group of mutually independent metal bosses 5 are formed on the sapphire flat sheet, as shown in fig. 5.
(5) Depositing a layer of SiO on the surface of the sapphire flat sheet with the metal boss 5 by using a plasma enhanced chemical vapor deposition method2Coating 6, shown in FIG. 6, SiO in the direction of the arrow2The direction of deposition of the coating 6. The temperature of the chamber used for PECVD (plasma enhanced chemical vapor deposition) is 100-500 ℃, and SiO is2The thickness is 0.5-2.0 μm, and the fluidity is changed according to the size of the metal pattern, and the thickness is changed by SiO2The coating can provide a protective film for the oxidation of metal and is also due to SiO2The refractive index of 1.45 is less than that of 1.76 of sapphire, so that the scattering effect of the substrate on light can be effectively improved, and the luminous efficiency of the LED chip is further improved.
(6) In SiO2A coating 7 of negative photoresist is applied over the coating 6 as shown in figure 7. The thickness of the negative photoresist coating is 0.5-3.0 μm, and the sapphire flat sheet is exposed from the other side of the sapphire flat sheet opposite to the side with the metal boss, as shown in fig. 8, and the direction of the arrow is the exposure direction. Exposing by replacing a photoetching plate with a metal boss as a shield for 3-20 s in a short time, taking the metal coating shielding part with gaps as an unexposed part, then developing, removing the unexposed part by reacting with a developing solution during developing according to the characteristics of the negative photoresist, and removing the unexposed part by reacting with the developing solution in SiO2A negative photoresist column 8 is formed on the coating as shown in fig. 9. The method reduces the cost of designing a mask or a photoetching plate with patterns and saves the cost.
(7) Sending the developed sapphire flat sheet into an etching machine to make the sapphire flat sheet have negative photoresist columns 8 and SiO2The coating 6 is used as a barrier layer to carry out plasma dry etching, the power of an upper electrode of an etching machine is set to be 100-2000W, the power of a lower electrode is set to be 100-1500W, and BCL (binary coded decimal) is adopted3Flow rate of 50-200 sccm, CHF3The flow is 0-20 sccm, the etching temperature is 10-50 ℃, the helium pressure is 1-10 mTorr, and the time is 100-3000 s, and the high-brightness patterned composite substrate is obtained after etching. As shown in fig. 10.
The invention is described above with reference to the accompanying drawings. It is to be understood that the specific implementations of the invention are not limited in this respect. Various insubstantial improvements are made by adopting the method conception and the technical scheme of the invention; the present invention is not limited to the above embodiments, and can be modified in various ways.
Claims (8)
1. A method for manufacturing a high-brightness composite substrate comprises the following steps:
(1) firstly, selecting a flat sapphire sheet with a smooth surface and two polished surfaces, and cleaning to remove impurities on the surface;
(2) a layer of metal coating is vapor-plated on the sapphire flat sheet;
(3) coating a positive photoresist coating on the metal coating, and selectively removing unnecessary parts by exposure and development to form a group of positive photoresist columns on the metal coating;
(4) carrying out ICP etching by taking the positive photoresist column as a barrier layer, and forming a group of mutually independent metal bosses on the sapphire flat sheet;
(5) depositing a layer of SiO on the surface of the sapphire flat sheet with the metal boss by using a chemical vapor deposition method2Coating;
(6) in SiO2Coating a negative photoresist layer on the coating layer, exposing and developing to selectively remove the undesired portions, thereby forming a SiO layer2Forming a group of negative photoresist columns on the coating; exposing the sapphire plain film from the other surface of the sapphire plain film with the metal boss, replacing a photoetching plate with the metal boss as a shield for exposure, wherein the exposure time is 3-20 s, and removing photoresist at the position where the metal boss is not shielded during development;
(7) with negative photoresist posts and SiO2And performing ICP etching by using the coating as a barrier layer, thereby obtaining the high-brightness composite substrate.
2. The method for manufacturing a high-luminance composite substrate according to claim 1, wherein: the blue diamond in the step (1)Washing the stone flat sheet with acetone for 5-10 min, and then carrying out concentrated H at 90 DEG C2SO4And H2O2Cleaning for 10-15 minutes in a mixed solution with a volume ratio of 3:1 or 5:2, cleaning for 8-10 minutes by using 80 ℃ deionized water, finally cleaning for 5-10 minutes by using 25 ℃ deionized water, and then spin-drying for 3-10 minutes at a high speed.
3. The method for manufacturing a high-luminance composite substrate according to claim 1, wherein: the thickness of the metal coating in the step (2) is 5-1000 nm, and the metal is one or a mixture of more of Au, Ag, Ni, Co, Fe, Cu, Pt, Pd and Al.
4. The method for manufacturing a high-luminance composite substrate according to claim 1, wherein: the film thickness of the positive photoresist coating in the step (3) is 0.5-3.0 μm, and the exposure time is 50-400 ms.
5. The method for manufacturing a high-luminance composite substrate according to claim 1, wherein: and (4) ICP etching, namely feeding the developed sapphire flat sheet into an etching machine for plasma dry etching, setting the power of an upper electrode of the etching machine to be 100-2000W, the power of a lower electrode of the etching machine to be 100-1500W, and setting BCL3Flow rate of 50-200 sccm, CHF3The flow is 0-20 sccm, the etching temperature is 10-50 ℃, the helium pressure is 1-10 mTorr, and the time is 100-1000 s.
6. The method for manufacturing a high-luminance composite substrate according to claim 1, wherein: SiO in the step (5)2The thickness is 0.5-2.0 μm, and the temperature of the chemical vapor deposition chamber is 100-500 ℃.
7. The method for manufacturing a high-luminance composite substrate according to claim 1, wherein: and (4) in the step (6), the thickness of the negative photoresist coating is 0.5-3.0 μm.
8. Fabrication of the high brightness composite substrate of claim 1The method is characterized in that: and (7) ICP etching, namely feeding the developed sapphire flat sheet into an etching machine for plasma dry etching, setting the power of an upper electrode of the etching machine to be 100-2000W, the power of a lower electrode of the etching machine to be 100-1500W, and setting BCL3Flow rate of 50-200 sccm, CHF3The flow is 0-20 sccm, the etching temperature is 10-50 ℃, the helium pressure is 1-10 mTorr, and the time is 100-3000 s.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910742941.5A CN110429099B (en) | 2019-08-13 | 2019-08-13 | Manufacturing method of high-brightness composite substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910742941.5A CN110429099B (en) | 2019-08-13 | 2019-08-13 | Manufacturing method of high-brightness composite substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110429099A CN110429099A (en) | 2019-11-08 |
| CN110429099B true CN110429099B (en) | 2020-05-05 |
Family
ID=68415811
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910742941.5A Active CN110429099B (en) | 2019-08-13 | 2019-08-13 | Manufacturing method of high-brightness composite substrate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110429099B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112802769B (en) * | 2020-12-31 | 2024-08-16 | 黄山博蓝特半导体科技有限公司 | A method for detecting and repairing a patterned composite substrate |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100831843B1 (en) * | 2006-11-07 | 2008-05-22 | 주식회사 실트론 | Compound semiconductor substrate grown on metal layer, manufacturing method thereof and compound semiconductor device using same |
| FR2960562B1 (en) * | 2010-05-31 | 2012-05-25 | Saint Gobain Cristaux Et Detecteurs | MONOCRYSTAL TEXTURE |
| KR101131485B1 (en) * | 2010-08-02 | 2012-03-30 | 광주과학기술원 | Fabricating method of nano structure for antireflection and fabricating method of photo device integrated with antireflection nano structure |
| JPWO2013146268A1 (en) * | 2012-03-27 | 2015-12-10 | 住友化学株式会社 | Inorganic layer light emitting device |
| CN103035806B (en) * | 2012-12-28 | 2015-12-02 | 湘能华磊光电股份有限公司 | For the preparation of the method for the nano graph substrate of nitride epitaxial growth |
| CN207651512U (en) * | 2017-12-07 | 2018-07-24 | 上海芯元基半导体科技有限公司 | A kind of compound substrate and semiconductor device structure |
-
2019
- 2019-08-13 CN CN201910742941.5A patent/CN110429099B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN110429099A (en) | 2019-11-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101164136B1 (en) | A method for manufacturing sapphire board | |
| TWI450413B (en) | Light-emitting diode and manufacturing method thereof | |
| CN101371338B (en) | Method for manufacturing and separating semiconductor devices | |
| CN110444642B (en) | Preparation method of high-brightness patterned composite substrate | |
| CN110429160B (en) | High-brightness PSS composite substrate and manufacturing method thereof | |
| CN110444641B (en) | A high-brightness patterned composite substrate and method of making the same | |
| CN101027777A (en) | Vertical structure semiconductor devices with improved light output | |
| CN106206896B (en) | The production method of compound pattern Sapphire Substrate and its epitaxial wafer | |
| CN104319333B (en) | A kind of LED chip with high reflection electrode and preparation method thereof | |
| CN111244244A (en) | High-power LED chip and manufacturing method thereof | |
| CN108511573A (en) | A kind of preparation method of GaN base light emitting chip | |
| CN110429099B (en) | Manufacturing method of high-brightness composite substrate | |
| CN102931300B (en) | Method for manufacturing back metallic reflector array in manufacturing process of GaN-based LED | |
| CN101246933A (en) | Bonding pad process for LED epitaxial chip | |
| CN103365091B (en) | Mask liquid for surface roughening of LED (light emitting diode) chip or substrate as well as preparation method and application thereof | |
| CN114823994A (en) | Patterned substrate, preparation method of patterned substrate and LED chip | |
| TWI427822B (en) | Light emitting diode and manufacturing method thereof | |
| CN116387428B (en) | LED chip preparation method | |
| CN214336733U (en) | LED chip structure for ALD deposition of current expansion layer | |
| CN114864774B (en) | Preparation method of patterned substrate and LED epitaxial structure with air gap | |
| CN112951954B (en) | Light-emitting diode chip and manufacturing process thereof | |
| CN105702824B (en) | A method of LED vertical chip is made using wafer scale Si graph substrates | |
| CN114597295A (en) | A chip structure and preparation method of Mini/Micro LED | |
| CN105932133B (en) | A kind of high brightness LED chip and preparation method thereof | |
| CN112750933A (en) | LED chip and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |