CN110176392A - 半导体制造中的间隔物限定的直接图案化方法 - Google Patents
半导体制造中的间隔物限定的直接图案化方法 Download PDFInfo
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- CN110176392A CN110176392A CN201910110274.9A CN201910110274A CN110176392A CN 110176392 A CN110176392 A CN 110176392A CN 201910110274 A CN201910110274 A CN 201910110274A CN 110176392 A CN110176392 A CN 110176392A
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Classifications
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
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- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02219—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and nitrogen
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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Abstract
一种半导体制造中的间隔物限定的直接图案化方法包括:提供具有线的目标宽度的光致抗蚀剂结构;修整所述光致抗蚀剂结构,使得每个修整过的光致抗蚀剂结构的宽度小于所述目标宽度;在模板上沉积氧化物膜,从而用所述氧化物膜完全覆盖所述模板的暴露顶表面和所述修整过的光致抗蚀剂结构;蚀刻所述氧化膜覆盖的模板以去除所述氧化膜的不需要部分而不去除所述修整过的光致抗蚀剂结构,从而形成彼此隔离的竖直间隔物,每个间隔物基本上保持所述目标宽度并由所述修整过的光致抗蚀剂结构和覆盖所述修整过的光致抗蚀剂结构的侧壁的所述氧化膜的竖直部分构成;以及蚀刻形成间隔物的模板,以将由所述间隔物构成的图案转移到所述模板上。
Description
技术领域
本发明一般涉及半导体制造中的图案化方法,特别是半导体制造中的间隔物限定的直接图案化方法,其使用例如用于光刻的EUV(极紫外)。
背景技术
为了对应于半导体装置的小型化,减少用于光刻的光源的波长,例如从ArF(氟化氩激光)变到EUV。迄今为止,由于如下所述的EUV光刻的低生产率,通过使用间隔物限定的双图案化(SDDP)已经实现了半导体装置的小型化。然而,由于曝光精度有限,SDDP的小型化存在限制,并且最近出现了实际使用EUV光刻的前景。因此,预期使用EUV光刻的直接图案化将在未来的半导体制造中投入实际使用。
EUV光刻能够进行图案化,图案尺寸为10至20nm(ArF激光光刻中的最小尺寸约为40nm);然而,作为通过LER(线边缘粗糙度)和LWR(线宽粗糙度)评估的表面粗糙度的图案化精度取决于构成抗蚀剂的聚合物的特征,因此,约5nm的表面粗糙度可能是下限并且尚未改善。因此,在用于微型制造的精细布线中,宽度为5nm的精细布线的起伏或波纹是不可避免的并且导致线间短路。本发明人进行了研究以改善半导体制造中的图案化精度。
对与相关技术有关的问题和解决方案的任何论述都已经仅出于向本发明提供背景的目的而包括于本公开中,并且不应被视为承认所述论述中的任一项或全部在创作本发明时都是已知的。
发明内容
在一些实施例中,通过提供具有通过EUV光刻图案化的抗蚀剂的模板;使用等离子体增强原子层沉积(PEALD)设备进行修整或蚀刻抗蚀剂;并且在包括修整过的抗蚀剂的模板的暴露表面上沉积SiO2膜,其厚度使得预修整过的抗蚀剂的尺寸恢复,以便覆盖具有粗糙表面的修整过的抗蚀剂,同时基本上保持抗蚀剂的原始尺寸,可以减少微型制造的变化。
出于概述本发明的方面和所实现的优于相关技术的优势的目的,本发明的某些目标和优势描述于本公开中。当然,应理解,未必所有此类目标或优势都可以根据本发明的任一特定实施例来实现。因此,举例来说,本领域的技术人员将认识到,本发明可以按实现或优化如本文所传授的一个优势或一组优势的方式实施或进行,而不必实现如本文中可能传授或表明的其它目标或优势。
本发明的其它方面、特征和优势将根据下文的实施方式而变得显而易见。
附图说明
现将参考优选实施例的图来描述本发明的这些和其它特征,所述优选实施例打算说明而非限制本发明。各图出于说明性目的而被大大简化并且未必按比例。
图1A是可用于本发明的一个实施例中的用于沉积电介质膜的PEALD(等离子体增强原子层沉积)设备的示意性图示。
图1B示出了可用于本发明的一个实施例中的使用流通系统(FPS)的前体供应系统的示意图。
图2示出了在未修整的情况下进行EUV光刻后(“光刻后”)、在0.5秒修整后(“0.5s”)、在1.0秒修整后(“1s”)、在1.5秒修整后(“1.5s”)和在2.0秒修整后(“2s”)的图案化表面的STEM照片,其中下面的照片(b)是在比上面的照片(a)高的放大倍率下拍摄的。
图3是示出根据本发明的一个实施例的光致抗蚀剂的CD(“PR CD”)与修整的处理时间(“处理时间”)之间的关系的图。
图4示出了使用间隔物限定的双图案化(SDDP)的图案转移(步骤(a)至(f))的示意图和使用间隔物限定的直接图案化的图案转移(步骤(a')、(b')和(f'))的示意图。
图5示出了根据本发明的一个实施例的使用间隔物限定的直接图案化的图案转移(步骤(a)至(e))的示意图。
图6示出了根据本发明的另一个实施例的使用间隔物限定的直接图案化的图案转移(步骤(a)至(e),另外的步骤(a'))的示意图。
图7示出了根据本发明的一个实施例的通过光刻((a)中的“光刻后”)和在氧化物膜沉积((b)中的“PEALD-SIO2间隔物沉积”)后形成的光致抗蚀剂的图案化线的STEM照片。
图8示出了根据本发明的一个实施例的通过光刻(“光刻后”)、在9秒修整后(“9秒修整后”)和在氧化物膜沉积后(“间隔物沉积后”)形成的光致抗蚀剂的图案化线的STEM照片。图8还示出了其CD、LWR和LER。
图9是示出根据本发明的一个实施例的光致抗蚀剂的LER和LWR(“LER/LWR”)与修整的处理时间(“修整时间”)之间的关系的图。
图10是示出与图9所示的测量点对应的CD的表。
图11示出了根据本发明的一个实施例的通过光刻((a)中的“初始”)和在其上通过ALD沉积SiO层((b)中的“SiO ALD(~2nm)”)之后形成的光致抗蚀剂的图案化线的横截面视图的STEM照片。
图12示出了根据本发明的一个实施例在通过图11的(b)中所示的ALD沉积SiO层((b)中的“SiO ALD(~2nm)”)后、在修整图案化线10秒((c)中的“ALD+修整(10秒)”)后、在修整图案化线15秒((d)中的“ALD+修整(15秒)”)后和在修整图案化线20秒((e)中的“ALD+修整(20秒)”)后图案化线的横截面视图的STEM照片。
图13是示出当根据图12中所示的实施例改变修整时间时图案化线的高度和CD(nm)的变化的图。
图14是示出根据本发明的一个实施例的当修整时间改变时图案化线的高度、宽度(nm)和LWR(nm)的变化的图。
图15示出了在对应于图14中的“初始”的(a)中通过ALD沉积SiO层之前、在对应于图14中的“沉积”的(b)中通过ALD沉积SiO层后、在对应于图14中的“沉积+修整(10秒)”的(c)中修整图案化线10秒后和在对应于图14中的“沉积+修整(15秒)”的(d)中修整图案化线15秒后的图案化线的横截面视图的STEM照片。
具体实施方式
在本公开中,取决于上下文,“气体”可包含汽化固体和/或液体,且可由单一气体或气体混合物构成。同样,取决于上下文,冠词“一”是指一种物种或包含多个物种的属。在本公开中,通过喷头引入反应室中的工艺气体可以包含含硅前体和添加剂气体、主要由其组成或由其组成。添加剂气体可以包括用于氮化和/或碳化前体的反应气体和当向添加剂气体施加RF功率时用于激发前体的惰性气体(例如,稀有气体)。惰性气体可作为运载气体和/或稀释气体馈送到反应室。此外,在一些实施例中,不使用反应气体,且仅使用稀有气体(作为运载气体和/或稀释气体)。前体和添加气体可作为混合气体或单独地引入到反应空间。前体可以与运载气体如稀有气体或氮气一起引入。除工艺气体外的气体,即,在不穿过喷头的情况下引入的气体,可用于例如密封反应空间,这包含稀有气体等密封气体。在一些实施例中,术语“前体”一般是指参与产生另一化合物的化学反应的化合物,并且尤其是指构成膜基质或膜的主要构架的化合物,然而术语“反应物”是指不为前体的活化前体、使前体改性或催化前体反应的化合物,其中当施加RF功率时反应物可以向膜基质提供元素(如N、C)并且变成膜基质的一部分。术语“惰性气体”是指当施加RF功率时激发前体的气体,但不同于反应物,其不变成膜基质的一部分。
在一些实施例中,“膜”是指在垂直于厚度方向的方向上连续延伸的基本上无小孔的覆盖整个目标或相关表面的层,或仅仅是指覆盖目标或相关表面的层。在一些实施例中,“层”是指在表面上形成的具有某一厚度的结构,或膜或非膜结构的同义词。膜或层可以由具有某些特征的离散单个膜或层构成或由多个膜或层构成,并且相邻膜或层之间的边界可以透明或可以不透明,并且可以基于物理、化学和/或任何其它特征、形成工艺或序列和/或相邻膜或层的功能或目的而建立。此外,在本公开中,由于可工作范围可基于常规工作而确定,因此变量的任何两个数字可构成变量的可工作范围,且所指示的任何范围可包含或排除端点。另外,所指示的变量的任何值(不论它们是否用“约”指示)可以指精确值或近似值并且包括等同物,并且在一些实施例中,可以指平均值、中值、代表值、大部分值等。此外,在本公开中,在一些实施例中,术语“由…构成”和“具有”独立地指“典型地或广泛地包括”、“包括”、“基本上由…组成”或“由…组成”。在本公开中,在一些实施例中,任何限定的含义未必排除普通和惯用含义。
在本公开中,在未指定条件和/或结构的情况下,鉴于本公开,本领域的技术人员可以容易地按照常规实验提供此类条件和/或结构。
在所有的公开实施例中,实施例中所用的任何要素可出于既定目的而利用与其同等的任何要素替换,包含本文中明确、必须或本质上公开的那些要素。此外,本发明可以同等地适用于设备和方法。
将参照优选实施例来阐述实施例。然而,本发明不限于所述优选实施例。
在一些实施例中,半导体制造中的间隔物限定的直接图案化方法包含:(i)使用在模板上通过光刻形成的光致抗蚀剂结构在模板中预设待图案化的线的目标宽度;(ii)提供其上具有图案化的光致抗蚀剂结构的模板;(iii)修整光致抗蚀剂结构,使得每个修整过的光致抗蚀剂结构的宽度小于目标宽度;(iv)在模板上沉积氧化物膜,从而用氧化物膜完全覆盖模板的暴露顶表面和修整过的光致抗蚀剂结构;(v)蚀刻氧化物膜覆盖的模板以去除不需要的氧化物膜部分而不去除修整过的光致抗蚀剂结构,从而形成彼此隔离的竖直间隔物,每个间隔物基本上保持目标宽度并由修整过的光致抗蚀剂结构和覆盖修整过的光致抗蚀剂结构的侧壁的氧化膜的竖直部分构成;以及(vi)蚀刻形成间隔物的模板,将由间隔物构成的图案转移到模板上。
在一些实施例中,目标宽度通常为5nm至30nm,优选10nm至20nm。在一些实施例中,在步骤(iii)中,宽度方向上的修整量通常为每侧1nm至5nm(即,在步骤(iii)中光致抗蚀剂结构的宽度减小2nm至10nm)。在一些实施例中,高度方向上的修整量也是1nm至5nm,其基本上等于宽度方向上的修整量,因为修整主要使用自由基进行(然而,当在后面讨论的步骤(iii)之前进行沉积薄氧化物膜的步骤(iia)时,不仅使用自由基而且使用离子轰击进行修整)。在一些实施例中,在步骤(iii)之前,可以在每个光致抗蚀剂结构的顶表面上沉积SiO2预涂层,使得可以主要在宽度方向而不是在高度方向上进行修整。
在一些实施例中,步骤(ii)中的光致抗蚀剂结构具有与目标宽度基本上相同的宽度。在本公开中,“基本上相同”、“基本上均匀”等可以指无关紧要的差异或所属领域的技术人员认可的差异,例如小于30%、小于10%、小于5%或其在一些实施例中取决于主题技术的任何范围的差异(在一些实施例中,即使两者之间的差异高达约50%,这两者也将被认为是基本上相同的)。或者,在一些实施例中,步骤(ii)中的光致抗蚀剂结构的宽度基本上大于目标宽度,因为光致抗蚀剂结构经受下面的修整处理。在本公开中,“基本上更大”、“基本上不同”等可以指实质差异或所属领域的技术人员认可的差异,例如至少1%、5%、10%、20%、30%、40%、50%、60%、70%、80%或其在一些实施例中取决于主题技术的任何范围的差异。
在一些实施例中,在步骤(iv)中沉积的氧化物膜具有这样的厚度,使得每个氧化物膜覆盖的修整过的光致抗蚀剂结构具有与目标宽度基本上相同的宽度,因为预期氧化物膜覆盖的修整过的光致抗蚀剂结构的厚度在步骤(v),即蚀刻步骤期间,基本上保持不变。在一些实施例中,在步骤(iv)中沉积的氧化物膜具有这样的厚度,使得在氧化物膜覆盖的修整过的光致抗蚀剂结构的厚度在步骤(v),即蚀刻步骤期间略微减小的情况下,每个氧化物膜覆盖的修整过的光致抗蚀剂结构的宽度略微大于目标宽度(“略微”可以指小于10%的差异,这取决于实施例)。
在一些实施例中,在步骤(iv)中,氧化物膜是通过等离子体增强原子层沉积(PEALD)沉积的保形膜,因为氧化物膜覆盖的修整过的光致抗蚀剂结构用作竖直间隔物。在一些实施例中,在步骤(iv)中,通过等离子体增强原子层沉积(PEALD)沉积氧化物膜,其中控制压力、温度和/或RF功率,使得沉积在每个修整过的光致抗蚀剂结构的顶表面上的氧化物膜部分的干式蚀刻速率高于(例如,两倍或更多倍)沉积在每个修整过的光致抗蚀剂结构的侧壁上的氧化物膜部分,因此在步骤(v)中,竖直间隔物可以在基本上保持修整过的光致抗蚀剂结构的高度(例如,20nm至150nm,优选30nm至80nm)的同时形成。
在一些实施例中,在步骤(iii)中修整每个光致抗蚀剂结构,以便在光致抗蚀剂结构的每一侧上将其宽度减小1nm至5nm。通过减小光致抗蚀剂结构的宽度,可以改善图案化线的CD、LER和LWR。但是,如果宽度减小超过5nm,则CD、LER和LWR可能不再改善;相反,它们开始退化。
在一些实施例中,在模板的抗反射层上形成光致抗蚀剂结构,并且在步骤(v)中,当去除不需要的氧化物膜部分时,同样去除在不需要的氧化膜部分下面形成的抗反射层部分,使得图案化的抗反射层可以用作掩模以将图案转移到模板。在一些实施例中,不需要的氧化物膜部分包括沉积在光致抗蚀剂结构顶部的氧化物膜部分,以及沉积在抗反射层的暴露表面上的氧化物膜部分,即氧化物膜的水平延伸部分。在上文中,在一些实施例中,沉积在光致抗蚀剂结构顶部上的氧化物膜部分具有耐化学性(例如,低干式蚀刻速率),使得所述部分在沉积于抗反射层的暴露表面上的氧化物膜部分和抗反射层被去除之前未被完全去除,从而防止在步骤(iv)中剥离被氧化膜覆盖的光致抗蚀剂结构。
在一些实施例中,在步骤(i)中,预设目标宽度在10nm至20nm的范围内。在一些实施例中,步骤(ii)包含使用EUV(极紫外)光通过光刻形成光致抗蚀剂结构。由于通过使用EUV光刻或与其等效的其它光刻,预设目标宽度可以小至10nm至20nm,因此可以有效地实现间隔物限定的直接图案化。
在一些实施例中,所述方法进一步包含,在步骤(iii)之前,(iia)通过等离子体增强原子层沉积(PEALD)在模板上沉积具有约2nm或更小厚度的薄氧化物膜,从而用薄氧化膜完全覆盖模板的暴露顶表面和光致抗蚀剂结构。如后所述,通过进行步骤(iia),即使当光致抗蚀剂结构是稀疏排列的光致抗蚀剂结构和密集排列的光致抗蚀剂结构的混合物时,也可以有效地改善“负载效应”,从而改善CD、LER和LWR。
在一些实施例中,当进行步骤(iia)时,步骤(iii)中的修整通过直接等离子体蚀刻进行。由于直接等离子体不仅含有自由基而且含有离子,与远程等离子体不同,可以更有效地改善“负载效应”。
在一些实施例中,步骤(iia)中的薄氧化物膜和步骤(iv)中的氧化物膜由相同的材料构成并且除了沉积过程的持续时间,即膜厚度(通常步骤(iia)中的氧化物膜的厚度为2nm或更小,而步骤(iv)中的氧化物膜的厚度大于2nm)之外,在相同的条件下沉积,从而可以实现有效的操作。在一些实施例中,步骤(iia)中的薄氧化物膜和步骤(iv)中的氧化物膜独立地由SiO2、TiO、HfO或AlO构成,其可以在常规条件下,例如美国专利第8,252,691号和第8,298,951号中所公开的那些条件下沉积,其各自的公开内容通过引用整体并入本文。
在一些实施例中,步骤(ii)中的光致抗蚀剂结构由具有不同线间距的稀疏和密集排列的光致抗蚀剂结构构成。
在一些实施例中,在步骤(iii)之前,光致抗蚀剂结构具有大于5nm的LER(线边缘粗糙度)和大于3.5nm的LWR(线宽粗糙度)。LER和LWR的测量方法是工业上已知的(例如J.S.Villarrubia和B.D.Bunday,“Unbiased Estimation of Linewidth Roughness”,Proc.of SPIE Vol 5752,480(2005),其公开内容通过引用整体并入本文)。
在一些实施例中,在步骤(iv)之前,修整过的光致抗蚀剂结构具有小于5nm的LER和小于3.5nm的LWR。在一些实施例中,在步骤(v)之前,氧化物膜覆盖的修整过的光致抗蚀剂结构具有4nm或更小的LER,以及3nm或更小的LWR。
尽管后面讨论了工艺条件,但是一些实施例的特征在于步骤(iii)中使用的反应气体不包含氧气,步骤(ii)至(v)在150℃或更低的温度下进行,和/或步骤(ii)至(iv)在同一反应室中连续进行。
将结合附图中示出的实施例解释实施例。然而,本发明不限于此。
图4示出了使用间隔物限定的双图案化(SDDP)的图案转移(步骤(a)至(f))的示意图和使用间隔物限定的直接图案化的图案转移(步骤(a')、(b')和(f'))的示意图。
在高级SDDP中,另外进行步骤(b)以降低抗蚀剂图案的CD,因为使用ArF激光光刻难以形成宽度为约20nm或更小的抗蚀剂图案。在步骤(a)中,层状结构由通常通过旋涂或CVD工艺制备作为目标层的非晶碳层(αC)45(例如,其在衬底(未示出)上形成)、沉积在其上用作蚀刻硬掩模的氮化硅层(SiN)44、沉积在其上用作间隔物的非晶硅层(αSi)43、作为用于双图案化的模板的非晶碳层(αC)48、沉积在其上的含硅抗反射涂层(SiARC)42、沉积在其上的底部抗反射涂层(BARC)41(通常由有机材料制成)和通常由ArF激光光刻形成的光致抗蚀剂图案46(由例如东京JSR公司制造的JSR3030、ARX 2014或ARX 1532JE,或与其等效的材料构成)构成。通过ArF激光光刻形成的光致抗蚀剂图案46具有例如45nm的宽度。
在高级SDDP工艺中,进行步骤(b)以通过干式蚀刻(使用例如O2、N2O、CO2、H2或Ar,或者前述任何两种或更多种的混合物作为蚀刻剂气体,根据构成抗蚀剂的材料选择)来修整抗蚀剂46,通过将其宽度从45nm减小到22.5nm来减小抗蚀剂图案的CD,从而形成修整过的抗蚀剂46'。BARC 41也在光致抗蚀剂图案中被修整以在步骤(b)中形成修整过的BARC41',这是将图案转移到用作模板的αC48的步骤。在步骤(c)中,通过使用修整过的抗蚀剂46'和修整过的BARC 41',蚀刻SiARC 42和αC 48(使用例如对于硅:HBr、Cl2、BCl3、Ar、O2、含氟气体(碳氟化合物、SF6、NF3);对于碳:O2、N2O、CO2、H2、Ar、H2、含氟气体(碳氟化合物、SF6、NF3)作为蚀刻剂气体)以将定时抗蚀剂46'的图案转移到SiARC 42和αC48,形成经过蚀刻的SiARC 42'和经过蚀刻的αC 48'。在此实施例中,使用BARC 41、SiARC 42和αC 48;然而,这些层可以共同作为用作模板的抗反射层处理,所述层可以由单层或多层构成。
在步骤(d)中,在相对低的温度下沉积金属氧化物层(LT-SiO2)47(由例如氧化硅构成),然后在步骤(e)中进行蚀刻,所述步骤是间隔物RIE(反应性离子蚀刻)步骤(使用例如HBr、Cl2、BCl3、Ar、O2、含氟气体(碳氟化合物、SF6、NF3)作为蚀刻剂气体)蚀刻金属氧化物层47,形成经过蚀刻的LT-SiO2 47'。通过灰化剥离经过蚀刻的SiARC 42'和经过蚀刻的αC48'的材料,经过蚀刻的LT-SiO2 47'作为竖直间隔物84留在αSi 43上。由于金属氧化物间隔物(47')具有高蚀刻选择性,所以用于在其上形成间隔物的经过蚀刻的SiARC42'和经过蚀刻的αC 48(模板)可以是薄的,并且在蚀刻期间可以维持金属氧化物间隔物(47')。在一些实施例中,抗反射层(由BARC 41、SiARC 42和αC 48共同构成)的厚度为约5至50nm(通常为10至30nm),金属氧化物层(LT-SiO2 47)的厚度为约5至50nm(通常为10至20nm)。在步骤(f)中,通过使用经过蚀刻的LT-SiO2 47',蚀刻αSi 43(使用例如HBr、Cl2、BCl3、Ar、O2、含氟气体(碳氟化合物、SF6、NF3)作为蚀刻剂气体),形成经过蚀刻的αSi 43',其具有例如22.5nm的线宽,其可用作第二模板。因此,根据高级SDDP,即使使用ArF激光光刻,也可以形成具有例如约22.5nm的线宽的模板。
然而,如上面关于图4中的步骤(a)至(f)所讨论的,高级SDDP需要中间模板(例如αC 48)以及涉及额外蚀刻和沉积步骤的相关步骤(c)至(e)。相反,在间隔物限定的直接图案化中,如图4中的步骤(a')、(b')和(f')所示,附加步骤(c)至(e)以及中间模板(例如αC 48)可以完全消除。
在直接图案化中,在步骤(a')中,通过使用EUV光刻,例如在由层55、54、53、52和51构成的层叠结构上形成具有约20nm线宽的抗蚀剂图案56,所述层对应于或等同于非晶碳层(αC)45、氮化硅层(SiN)44、非晶硅层(αSi)43、含硅抗反射涂层(SiARC)42和底部抗反射涂层(BARC)41。在步骤(a')中,修整步骤(a')的抗蚀剂图案中的BARC 51,形成修整过的BARC51',并且通过使用修整过的BARC 51',蚀刻SiARC 52和αSi 53以将步骤(b')中的抗蚀剂图案转移到αSi53,在步骤(f')中形成具有例如20nm线宽的经过蚀刻的αSi 53'。因此,通过使用EUV光刻,可以在不使用中间模板的情况下将线宽为10nm至20nm的抗蚀剂图案直接转移到模板。
然而,如前所述,尽管EUV光刻能够以10至20nm的图案尺寸进行图案化,但是图案化精度,即通过LER(线边缘粗糙度)和LWR(线宽粗糙度)评估的表面粗糙度,取决于构成抗蚀剂的聚合物的特征,因此,约5nm的表面粗糙度可能是下限并且尚未改善。
图5示出了根据本发明的一个实施例的使用间隔物限定的直接图案化的图案转移(步骤(a)至(e))的示意图,其中可以有效地解决上述问题。
在根据此实施例的直接图案化中,在步骤(a)中,通过使用EUV光刻,在由层35、34、33、32和31构成的层叠结构上形成具有例如约20nm(通常10nm至20nm)线宽的抗蚀剂图案36,所述层对应于或等同于图4中的非晶碳层(αC)55、氮化硅层(SiN)54、非晶硅层(αSi)53、含硅抗反射涂层(SiARC)52和底部抗反射涂层(BARC)51。
当使用EUV光刻或其等同物时,抗蚀剂图案的线宽可以小至20nm或更小。然而,抗蚀剂图案的LER(线边缘粗糙度)和LWR(线宽粗糙度)通常分别大于3.5nm和大于5nm,高于用于半导体装置的微型制造所期望的LER和LWR,例如分别为3.5nm或更小(优选3nm或更小)和5nm或更小(优选4nm或更小)。在图5的步骤(a)中,LER和LWR分别是例如3.87nm和5.26nm(参见后面描述的实例)。
根据此实施例,在图5中的步骤(b)中,修整抗蚀剂36,使得抗蚀剂36的宽度从20nm减小到10nm(通常为5nm至10nm),形成修整过的抗蚀剂36'。通过此干式蚀刻工艺,可以显著改善LER和LWR。例如,在步骤(b)中,LER和LWR分别从4.1nm和3.07nm减小到5.26nm和3.87nm。在一些实施例中,修整可以在下表1中所示的条件下进行。
表1(数值是近似值)
一般 | 典型 | |
温度 | 30℃至100℃ | 30℃至50℃ |
压力 | 100Pa至1000Pa | 200Pa至600Pa |
蚀刻剂 | O<sub>2</sub>、N<sub>2</sub>O、CO<sub>2</sub>、H<sub>2</sub>、Ar | 根据抗蚀剂材料选择 |
蚀刻剂流量 | 1至10SLM | 根据抗蚀剂材料选择 |
用于300mm晶片的RF功率 | 10W至500W | 30W至100W |
持续时间 | 1至20秒 | 5至10秒 |
宽度方向的修整速率 | 10nm至100nm/min | 20nm至50nm/min |
高度方向的修整速率 | 10nm至100nm/min | 20nm至50nm/min |
在本公开中,用于300mm晶片的任何指示的RF功率可以被转换为W/cm2(每单位面积晶片的瓦数),其可以应用于具有不同直径(例如200mm或450mm)的晶片。
根据此实施例,在步骤(c)中,通过例如PEALD在相对低的温度下在暴露的表面上沉积保形金属氧化物层(LT-SiO2)37(由例如氧化硅构成)以补偿修整过的抗蚀剂36'的宽度的减小,使得由修整过的抗蚀剂36'构成的线的宽度可以通过沉积的具有5nm(通常2nm至10nm)的厚度的LT-SiO2 37增加到或重建到例如20nm(通常为10nm至25nm,其可以与步骤(a)中的抗蚀剂的宽度基本上相同、更厚或更薄)。由于LT-SiO2 37通过PEALD等沉积并具有高保形性,因此它可以均匀厚度均匀地覆盖修整过的抗蚀剂36',从而可以在不降低其表面粗糙度的情况下增加线的宽度。例如,由氧化物覆盖的修整过的抗蚀剂构成的线的LER和LWR分别为2.63nm和3.64nm。由于在图5的步骤(e)中将线图案转移到模板的同时期望保持LER和LWR,因此模板的线可以具有期望的LER和LWR。
在一些实施例中,步骤(c)中的氧化物膜由SiO2、TiO、HfO或AlO构成,其可以在常规条件下,例如美国专利第8,252,691号和第8,298,951号中公开的那些条件下沉积,其各自的公开内容以引用的方式整体并入本文。在一些实施例中,PEALD的前体是烷氨基硅烷。在一些实施例中,烷氨基硅烷选自由以下组成的群组:双二乙氨基硅烷(BDEAS)、双二甲基氨基硅烷(BDMAS)、己基乙基氨基硅烷(HEAD)、四乙基氨基硅烷(TEAS)、叔丁基氨基硅烷(TBAS)、双叔丁基氨基硅烷(BTBAS)、双二甲基氨基二甲基氨基硅烷(BDMADMS)、七甲基二硅氮烷(HMDS)、三甲基硅烷基二乙胺(TMSDEA)、三甲基硅烷基二甲胺(TMSDMA)、三甲基二苯基环三硅氮烷(TMTVCTS)、三三甲基羟基胺(TTMSHA)、双二甲基氨基甲基硅烷(BDMAMS)和二甲基硅烷基二甲胺(DMSDMA)。前体可以由单一前体或两种或更多种前体的混合物构成。在一些实施例中,氧化物膜具有80%至100%(通常约90%或更高)的保形性,其中“保形性”通过比较在侧壁或凹槽底部上的某些点(通常为中间点)处沉积的膜厚度与沉积在恰好凹槽外的平坦表面上的膜厚度来确定。
在图5的步骤(d)中,修整步骤(c)的抗蚀剂图案中的BARC 31,形成修整过的BARC31',并且通过使用修整过的BARC 31',蚀刻SiARC 32和αSi 33以将步骤(c)中的抗蚀剂图案转移到αSi 33,在步骤(e)中形成具有例如20nm线宽的经过蚀刻的αSi 33'。根据此实施例,通过使用EUV光刻,可以在改善LER和LWR的同时将线宽为10nm至20nm的抗蚀剂图案直接转移到模板。在一些实施例中,在步骤(c)后可以在下表2中所示的条件下进行步骤(d)中的蚀刻。
表2(数值是近似值)
在图5的步骤(c)中,在一些实施例中,可以操纵金属氧化物层37的膜轮廓和膜质量,以便在步骤(d)和(e)中,即当将抗蚀剂图案转移到模板时实现期望的结果。例如,通过以这样的方式沉积金属氧化物膜37,其中沉积在修整过的抗蚀剂36'的顶表面上的膜的厚度选择性地大于沉积在修整过的抗蚀剂36'的侧表面上的膜的厚度和/或耐化学性(以干式蚀刻速率和/或湿式蚀刻速率表示)高于沉积在修整过的抗蚀剂36'的侧表面上的膜的耐化学性,使得氧化物覆盖的修整过的抗蚀剂的高度可以在步骤(d)中进行BARC 31的干式或湿式蚀刻时保持不变。例如,沉积在侧表面上的膜的湿式蚀刻速率是沉积在顶表面上的膜的湿式蚀刻速率的至少两倍(例如2至5倍)。可以根据例如由与本申请中相同的申请人在2016年2月19日提交的美国序列号15/048,422、在2017年5月11日提交的美国序列号15/592,730和2017年7月14日提交的美国序列号15/650,686中公开的技术来实现对膜的厚度和质量的这种选择性调整,其各自的公开内容通过引用整体并入本文。
在图5的步骤(b)中,修整过程可以通过常规方法进行。然而,因为抗蚀剂的修整速度主要由抗蚀剂周围的自由基密度控制,所以修整速度根据抗蚀剂图案的密度而变化,即,图案是稀疏还是密集由例如线之间的距离或间隔来限定。取决于图案密度的修整速度的变化称为“负载效应”。因此,由于负载效应,当抗蚀剂图案由以不同间距或间隔排列的线构成时,密集排列的线的修剪速度低于稀疏排列的线(与进入宽谷(沟槽)相比,较少的自由基进入窄谷(沟槽)),导致线宽或CD的变化。
在本公开中,相邻光致抗蚀剂线、竖直间隔物和任何其它凹槽图案之间的凹槽被称为“线间距”。在一些实施例中,图案由具有从约10nm至约100nm(通常约20nm至约50nm)变化的不同线间距的线构成。在这种情况下,出现“负载效应”,导致线宽变化并降低LER/LWR。
图6示出了根据本发明的另一个实施例的使用间隔物限定的直接图案化的图案转移(步骤(a)至(e)以及附加步骤(a'))的示意图,其中除了步骤(a')之外,步骤(a)至(e)等同于图5中所示的那些。考虑到常规修整方法中的上述问题,在此实施例中,另外进行步骤(a'),其中通过PEALD在相对低的温度下在小厚度(通常0.5nm至5nm,例如2nm或更小,更通常1nm至2nm)处沉积共形薄金属氧化物层(LT-SiO2,由例如氧化硅构成)38。通过沉积接触并覆盖抗蚀剂36的暴露表面的薄氧化物层38,当在步骤(b)中氧化物覆盖的抗蚀剂暴露于氧自由基时,由于薄氧化物层覆盖抗蚀剂表面,抗蚀剂的修整速度不主要或直接受自由基密度控制,而是由氧自由基通过薄氧化物层的扩散速度和/或针对薄氧化物层的离子轰击产生的反应性氧(自由基)的量控制,从而减轻负载效应并改善整个图案中线宽和线间距的均匀性。薄氧化物层的厚度可以根据抗蚀剂和氧化物层之间的相容性或亲和性等来确定;然而,当氧化物层的厚度大于5nm时,自由基不能通过氧化物层到达抗蚀剂表面,因此,不能有效地进行修整。当薄氧化物层暴露于氧自由基时,薄氧化物层充当缓冲层,并且氧自由基通过薄氧化物层再生,修整抗蚀剂,其中当修整进行时,抗蚀剂的宽度逐渐减小而保持薄氧化物层附着在抗蚀剂上,其中薄氧化物层的厚度也逐渐减小。在一些实施例中,在步骤(a')之后可以在下表3中所示的条件下进行步骤(b)中的修整。
表3(数值是近似值)
应当注意,当通过PEALD在抗蚀剂上沉积薄氧化物层时,由于PEALD相比热ALD或自由基ALD(远程等离子体)产生更多的自由基并且产生更多的离子轰击,因此抗蚀剂表面在步骤(a')中在一定程度上被修整,但在图6的步骤(a')中没有示出这种现象(等离子体CVD可能不适合于沉积氧化物层,因为它不适合于沉积保形层)。因此,抗蚀剂的宽度不仅在步骤(b)中减小,而且在步骤(a')中减小。通过观察抗蚀剂横截面的STEM照片或通过测量步骤(a')中线宽度的增加,可以看到或确认上述现象(在沉积时进行修整),其低于除了将该层沉积在化学稳定的非抗蚀剂材料上之外,在相同条件下沉积相同层的情况。当步骤(a')用作上述修整/沉积步骤时,可以使用衬底温度和等离子体功率作为工艺参数来控制抗蚀剂的修整量,其中当衬底温度更高(氧的反应性更高)并且等离子体功率更高(氧的反应性也更高)时修整量变得更高。
在一些实施例中,步骤(a')中沉积的氧化物层与步骤(c)中沉积的氧化物层相同或不同。在一些实施例中,图6中的步骤(a)至(c)在PEALD设备的相同反应室中连续进行,然后在蚀刻设备中连续进行步骤(d)和(e)。在上文中,“连续地”是指在没有实质上不同的介入步骤的情况下,或者在没有实质上不同配方的介入步骤的情况下,不从相同的腔室移动衬底。在一些实施例中,步骤(b)中的修整通常通过使用直接等离子体(原位等离子体蚀刻)进行,或者可以使用远程等离子体等进行,只要抗蚀剂可以直接暴露于等离子体即可。然而,当在图6的步骤(a')之后进行步骤(b)中的修整时,与图5中没有步骤(a')的步骤(b)中的修整相比,直接等离子体是优选的,因为与远程等离子体相比,直接等离子体不仅含有自由基而且还含有大量离子(步骤(a')后面的步骤(b)需要自由基和离子)。在一些实施例中,步骤(b)中的修整使用Ar/N2等离子体而不是O2等离子体来进行,因为Ar/N2等离子体蚀刻涉及缓慢的蚀刻速度,因此,更容易控制或操纵修整的量。另一方面,使用氧等离子体在步骤(a')中(以及在一些实施例中,也在步骤(c)中)沉积氧化物层。
图5中步骤(b)至步骤(d)的处理顺序和图6中步骤(a')至步骤(d)的处理顺序可在同一反应室中连续进行,其中每个步骤由特定配方控制并且可以在不同配方之间进行吹扫/气体稳定步骤,而不从反应室转移衬底或不将衬底暴露于外部空气。例如,可以使用任何合适的设备,包括图1中所示的装置来执行这些处理。图1是可用于本发明一些实施例中的PEALD设备的示意图,所述设备宜与被编程以进行下文所描述的序列的控制装置结合。在这个图中,通过提供一对并联并且在反应室3的内部11(反应区)中彼此面对面的导电平板电极4、2,将HRF功率(13.56MHz或27MHz)25施加到一侧,并且使另一侧12电接地,在电极之间激发等离子体。在下部平台2(下部电极)中提供温度调节器,并且将其上所放置的衬底1的温度保持为在指定温度下恒定。上部电极4也充当喷淋板,根据为每个步骤设定的给定配方,反应气体和/或稀释气体(如果有的话)以及前体气体和蚀刻剂气体通过气体管线21和气体管线22(其它气体管线省略)分别引入反应室3中并通过喷淋板4。另外,在反应室3中,提供具有排气管线7的环形管13,通过所述排气管线排出反应室3的内部11中的气体。另外,安置在反应室3下方的传送室5具备密封气体管线24以将密封气体通过传送室5的内部16(传送区)引入到反应室3的内部11中,其中提供用于分隔反应区和传送区的隔离板14(此图省略闸阀,晶片通过闸阀传入传送室5或从传送室5传出)。传送室还具备排气管线6。
在一些实施例中,步骤(e)(蚀刻步骤)可以在包括传统设备的任何蚀刻设备中进行。根据构成待去除层的材料,即根据其对例如HF、HCl和TMAH湿式蚀刻;例如对BCl3、BCl3/Ar干式蚀刻;或者例如对氧化、交替氧化和HF的湿式蚀刻化学的组合(在半导体处理中常见)或基于氧或CF4的干式蚀刻的抗性或敏感性,例如选择蚀刻条件,并相应地进行蚀刻。
技术人员应了解,所述设备包括一个或多个被编程或以其它方式配置成使得本文其它地方所描述的沉积和反应器清洁工艺能够进行的控制器(未示出)。本领域的技术人员将了解,控制器与各种电源、加热系统、泵、机器人装置和反应器的气体流量控制器或阀连通。
在一些实施方案中,可以使用双室反应器(用于加工彼此靠近设置的晶片的两个部分或隔室),其中反应剂气体和稀有气体可以通过共享管线供应而前体气体通过未共享管线供应。
参考以下工作实例来进一步解释本发明。然而,所述实例并不打算限制本发明。在未指定条件和/或结构的实例中,鉴于本公开,本领域的技术人员可以容易地按照常规实验提供此类条件和/或结构。另外,在一些实施例中,可以将具体实例中应用的数值修改至少±50%的范围,并且所述数值是近似值。
实例
实例1
在下表4中所示的条件下使用图1A所示的PEALD设备对在300mm衬底的SiOC层上形成并具有约35nm的初始CD的光致抗蚀剂图案(由例如设计用于EUV光刻的酚醛树脂构成)进行修整。
表4(数值是近似值)
图3是示出光致抗蚀剂的CD(“PR CD”)与修整的处理时间(“处理时间”)之间的关系的图。确认光致抗蚀剂的CD作为修整的处理时间的函数线性地降低至少达到CD低至约20nm的程度。
实例2
尽管EUV光刻具有比ArF激光更高的曝光精度,但是难以将抗蚀剂图案的CD(临界尺寸)降低到低至12nm或更低的程度。在此实施例中,除了光致抗蚀剂的初始CD为约17.9nm之外,以基本上类似于实例1的方式对光致抗蚀剂进行修整。图2示出了在未修整的情况下进行EUV光刻后(“光刻后”)、在0.5秒修整后(“0.5s”)、在1.0秒修整后(“1s”)、在1.5秒修整后(“1.5s”)和在2.0秒修整后(“2s”)的图案化表面的SEM照片,其中下面的照片(b)是在比上面的照片(a)高的放大倍率下拍摄的。
从图2中可以看出,随着抗蚀剂图案的修整的进行,抗蚀剂图案的CD从约17.9nm(没有修整)降低,约16nm(修整0.5秒)、约15.1nm(修整1秒)、约14.5nm(修整1.5秒)和约12.3nm(修整2秒)。但是,从图2中可以看出,随着修整的进行,线区域和非线区域之间的对比度变低,即开始出现线中断。已经证实,难以将抗蚀剂图案的CD降低至约12nm或更低。
实例3
在此实例中,在下表5中所示的条件下,以与实例1中类似的方式对光致抗蚀剂(具有约7.90nm(平均值)的初始CD的ArF抗蚀剂)进行修整。
表5(数值是近似值)
然后通过PEALD对修整的抗蚀剂图案进行SiO2沉积,其在下表6中所示的条件下进行。
表6(数值是近似值)
图7示出通过光刻((a)中的“光刻后”)和沉积氧化硅膜((b)中的“PEALD-SIO2间隔物沉积”)后形成的光致抗蚀剂的图案化线的STEM照片,其中“3σ”代表平均值的3个标准差)。在此实例中,尽管抗蚀剂图案的初始CD为约38nm(平均值),如图7的(a)中所示,而氧化物覆盖的修整过的抗蚀剂的CD为约29nm(平均值),如图7的(b)中所示,氧化物覆盖的修整过的抗蚀剂图案的宽度被认为与初始抗蚀剂的宽度基本上相同(因为修整过的抗蚀剂图案的宽度为约9nm,而氧化物覆盖的修整过的抗蚀剂图案的宽度为约29nm,这被认为是相对于38nm宽度的实质尺寸恢复)。如图7所示,与初始抗蚀剂图案相比,氧化物覆盖的修整过的抗蚀剂图案显示出对LWR和LER的显著改善。
实例4
在此实例中,除了光致抗蚀剂的初始CD为约44.5nm,修整进行9秒和氧化物覆盖的修整过的抗蚀剂的CD恢复至约62.8nm之外,以基本上类似于实例3的方式对光致抗蚀剂进行修整,然后进行氧化物沉积。虽然抗蚀剂图案的初始CD为约45nm,而氧化物覆盖的修整过的抗蚀剂的CD为约63nm,但氧化物覆盖的修整过的抗蚀剂图案的宽度被认为与初始抗蚀剂的宽度基本上相同(因为修整过的抗蚀剂图案的宽度为约28nm,氧化物覆盖的修整过的抗蚀剂图案的宽度为约63nm,这被认为是相对于约45nm宽度的实质尺寸恢复)。
图8示出了通过光刻(“光刻后”)、在修整9秒后(“9秒修整后”)和在沉积氧化物膜后(“间隔物沉积后”)形成的光致抗蚀剂的图案化线的STEM照片。图8还示出了其CD、LWR和LER。如图8所示,与初始抗蚀剂图案相比,氧化物覆盖的修整过的抗蚀剂图案显示出对LWR和LER的显著改善。
实例5
在此实例中,除了修整时间如图9所示变化之外,以与实例4中基本上类似的方式对光致抗蚀剂进行修整。图9是示出光致抗蚀剂的LER和LWR(“LER/LWR”)和修整的处理时间(“修整时间”)之间的关系的图,其中“POR”指的是“参考点”。如图9所示,当增加修整时间时,修整过的抗蚀剂图案表现出对LWR和LER的显著改善,直到达到平线区。图10是示出与图9所示的测量点对应的CD的表。如图10所示,CD也通过增加修整的处理时间而降低。
实例6
在此实例中,除了膜厚度为约2nm之外,通过PEALD以与实例3中基本上类似的方式对光致抗蚀剂(具有约11nm的初始CD的EUV抗蚀剂)进行SiO沉积,然后除了如图12所示改变修整时间之外,以基本上类似于实例1中的方式修整。图11示出通过光刻((a)中的“初始”)和在其上通过ALD沉积SiO层后((b)中的“SiO ALD(~2nm)”)形成的光致抗蚀剂的图案化线的横截面图的STEM照片。图12示出在通过图11的(b)中所示的ALD沉积SiO层((b)中的“SiOALD(~2nm)”)后、在修整图案化线10秒((c)中的“ALD+修整(10秒)”)后、在修整图案化线15秒((d)中的“ALD+修整(15秒)”)后和在修整图案化线20秒((e)中的“ALD+修整(20秒)”)后图案化线的横截面视图的STEM照片。图13是示出当修剪时间如图12所示改变时图案化线的高度和CD(nm)的变化的图。
如图11所示,在包括侧壁和底部区域的抗蚀剂图案上均匀地沉积保形SiO薄膜(具有约2nm的厚度)。如图12所示,确认可以在基本上不降低间隔物(图案化的抗蚀剂)的高度的情况下进行修整。这似乎是因为SiO薄膜可以充当活性物种的来源,例如产生并提供给抗蚀剂下方表面的氧自由基,用于在暴露于等离子体时进行蚀刻。也就是说,SiO薄膜可以通过减轻由等离子体的离子轰击进行撞击而显著地保护抗蚀剂,从而抑制抗蚀剂顶部和底部区域的主要蚀刻,并且可以相当均匀地将活性物种释放到抗蚀剂表面以进行蚀刻,因此,蚀刻抗蚀剂的侧壁区域比顶部和底部区域更多,因为侧壁区域比顶部和底部区域的耐化学性低得多(例如,侧壁层的致密性较低并且具有比顶部和底部层高两倍或更高的WER,其也可以代表DER)。出于同样的原因,可以改善负载效应(即,无论抗蚀剂图案具有窄间隔还是宽间隔,都可以进行均匀蚀刻),从而降低抗蚀剂图案的CD而不降低图案的高度。然而,如图13所示,当修整时间超过20秒时,图案的高度倾向于开始减小。
实例7
在此实例中,以与实例6中基本上类似的方式通过PEALD对光致抗蚀剂(具有约11nm的初始CD的EUV抗蚀剂)进行SiO沉积,然后进行修整。图14是示出当修整时间改变时图案化线的高度、宽度(nm)和LWR(nm)的变化的图。图15示出了在对应于图14中的“初始”的(a)中通过ALD沉积SiO层之前、在对应于图14中的“沉积”的(b)中通过ALD沉积SiO层后、在对应于图14中的“沉积+修整(10秒)”的(c)中修整图案化线10秒后和在对应于图14中的“沉积+修整(15秒)”的(d)中修整图案化线15秒后的图案化线的横截面视图的STEM照片。如图14所示,结果与实例6中所示的类似。另外,如图14所示,通过沉积SiO薄膜改善了LWR并在修整间隔物(图案化的抗蚀剂)的同时保持改善。
预示性实例1
根据图6所示的顺序,首先,制备具有抗蚀剂图案(EUV抗蚀剂)36的衬底,其具有图6的(a)中所示的层结构。接着,以与实例3中所示基本上类似的方式在低温下对抗蚀剂图案进行SiO薄膜38的沉积(可以调整沉积时间等),如图6的(a')中所示。然后,以与实例1中所示基本上类似的方式对氧化物覆盖的抗蚀剂图案进行修整(可以调整修整时间等),获得具有窄宽度而不降低高度的抗蚀剂图案36',如图6的(b)中所示。其后,以与实例3中所示基本上类似的方式对修整过的抗蚀剂图案进行SiO沉积(可以调整沉积时间等),以便用SiO膜37(称为“间隔物”)覆盖修整过的抗蚀剂,以使得间隔物37的宽度与初始抗蚀剂36的基本上相同,如图6的(c)中所示。接下来,在下表7中所示的条件下,对间隔物36进行模板蚀刻(各向异性蚀刻)以使用间隔物作为蚀刻掩模蚀刻BARC层31,如图6的(d)中所示。接下来,使用由间隔物37'和经过蚀刻的BARC 31'构成的蚀刻掩模,在下表8所示的条件下进一步对模板进行各向异性蚀刻,以便将蚀刻掩模图案转移到αSi层33,从而获得图案化的αSi层33',如图6的(e)中所示。
表7(数值是近似值)
温度 | 60℃ |
压力 | 5Pa |
蚀刻剂 | Ar/O<sub>2</sub>/CF<sub>4</sub> |
蚀刻剂流量 | 200/50/20sccm |
用于300mm晶片的RF功率 | 200W |
持续时间 | 20秒 |
宽度方向的修整速率 | 基本上为零 |
表8(数值是近似值)
温度 | 60℃ |
压力 | 1Pa |
蚀刻剂 | Ar/O<sub>2</sub> |
蚀刻剂流量 | 200/200sccm |
用于300mm晶片的RF功率 | 500W |
持续时间 | 60秒 |
宽度方向的修整速率 | 基本上为零 |
结果,可以获得具有与初始抗蚀剂图案36的CD基本上相同的CD的图案化的αSi33',其具有显著改善的(降低的)LWR和LER,证实成功地进行了如图4的(a')、(b')和(f')所示的直接图案化。
预示性实例2
根据图5所示的顺序,除了预示性实例1的步骤(a')被省略之外,以与预示性实例1中基本上类似的方式将抗蚀剂图案(EUV抗蚀剂)36转移到模板的αSi层33。
结果,可以获得具有与初始抗蚀剂图案36的CD基本上相同的CD的图案化的αSi33',其具有显著改善的(降低的)LWR和LER,证实成功地进行了如图4的(a')、(b')和(f')所示的直接图案化。
本领域的技术人员应理解,可以在不脱离本发明精神的情况下进行大量和各种修改。因此,应清楚地理解,本发明的形式仅是说明性的,并且并不打算限制本发明的范围。
Claims (20)
1.一种半导体制造中的间隔物限定的直接图案化方法,其包含:
(i)使用在模板上通过光刻形成的光致抗蚀剂结构在所述模板中预设待图案化的线的目标宽度;
(ii)提供其上具有图案化的所述光致抗蚀剂结构的所述模板;
(iii)修整所述光致抗蚀剂结构,使得每个修整过的光致抗蚀剂结构的宽度小于所述目标宽度;
(iv)在所述模板上沉积氧化物膜,从而用所述氧化物膜完全覆盖所述模板的暴露顶表面和所述修整过的光致抗蚀剂结构;
(v)蚀刻所述氧化物膜覆盖的模板以去除所述氧化物膜的不需要部分而不去除所述修整过的光致抗蚀剂结构,从而形成彼此隔离的竖直间隔物,每个间隔物基本上保持所述目标宽度并由所述修整过的光致抗蚀剂结构和覆盖所述修整过的光致抗蚀剂结构的侧壁的所述氧化膜的竖直部分构成;以及
(vi)蚀刻形成间隔物的所述模板,将由所述间隔物构成的图案转移到所述模板上。
2.根据权利要求1所述的方法,其中步骤(ii)中的所述光致抗蚀剂结构具有与所述目标宽度基本上相同的宽度。
3.根据权利要求1所述的方法,其中在步骤(iv)中沉积的所述氧化物膜具有的厚度使得每个氧化物膜覆盖的修整过的光致抗蚀剂结构具有与所述目标宽度基本上相同的宽度。
4.根据权利要求1所述的方法,其中在步骤(iv)中,所述氧化物膜是通过等离子体增强原子层沉积(PEALD)沉积的保形膜。
5.根据权利要求1所述的方法,其中在步骤(iv)中,通过等离子体增强原子层沉积(PEALD)沉积所述氧化物膜,其中控制压力、温度和/或RF功率以使得沉积在每个修整过的光致抗蚀剂结构的顶表面上的所述氧化物膜的部分的干式蚀刻速率高于沉积在每个修整过的光致抗蚀剂结构的侧壁上的所述氧化物膜的部分的干式蚀刻速率。
6.根据权利要求1所述的方法,其中在步骤(iii)中修整每个光致抗蚀剂结构,以便在所述光致抗蚀剂结构的每一侧上将其宽度减小1nm至5nm。
7.根据权利要求1所述的方法,其中在所述模板的抗反射层上形成所述光致抗蚀剂结构,并且在步骤(v)中,当去除所述氧化物膜的所述不需要部分时,同样去除在所述氧化物膜的所述不需要部分下面形成的所述抗反射层的部分。
8.根据权利要求1所述的方法,其中在步骤(i)中,所述预设目标宽度在10nm至20nm的范围内。
9.根据权利要求1所述的方法,其中步骤(ii)包含使用EUV(极紫外)光通过光刻形成所述光致抗蚀剂结构。
10.根据权利要求1所述的方法,其进一步包含,在步骤(iii)之前:
(iia)通过等离子体增强原子层沉积(PEALD)在所述模板上沉积具有约2nm或更小厚度的薄氧化物膜,从而用所述薄氧化膜完全覆盖所述模板的暴露顶表面和所述光致抗蚀剂结构。
11.根据权利要求10所述的方法,其中步骤(iii)中的修整是通过直接等离子体蚀刻进行。
12.根据权利要求10所述的方法,其中步骤(iia)中的所述薄氧化膜和步骤(iv)中的所述氧化膜是由相同的材料构成。
13.根据权利要求10所述的方法,其中步骤(ii)中的所述光致抗蚀剂结构是由具有不同线间距的稀疏和密集排列的光致抗蚀剂结构构成。
14.根据权利要求10所述的方法,其中步骤(iia)中的所述薄氧化膜是由SiO2、TiO、HfO或AlO构成。
15.根据权利要求1所述的方法,其中在步骤(iii)之前,所述光致抗蚀剂结构具有大于3.5nm的LER(线边缘粗糙度)和大于5nm的LWR(线宽粗糙度)。
16.根据权利要求15所述的方法,其中在步骤(iv)之前,所述修整过的光致抗蚀剂结构具有小于3.5nm的LER和小于5nm的LWR。
17.根据权利要求16所述的方法,其中在步骤(v)之前,所述氧化物膜覆盖的修整过的光致抗蚀剂结构具有3nm或更小的LER,以及4nm或更小的LWR。
18.根据权利要求1所述的方法,其中步骤(iii)中使用的反应气体不包含氧气。
19.根据权利要求1所述的方法,其中步骤(ii)至(v)是在150℃或更低的温度下进行。
20.根据权利要求1所述的方法,其中步骤(ii)至(iv)是在同一反应室中连续进行。
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CN103843110A (zh) * | 2011-08-26 | 2014-06-04 | 应用材料公司 | 双重图案化蚀刻工艺 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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CN110648905A (zh) * | 2019-09-25 | 2020-01-03 | 上海华虹宏力半导体制造有限公司 | 半导体器件的制备方法 |
CN110902647A (zh) * | 2019-12-05 | 2020-03-24 | 深圳先进技术研究院 | 一种渐变尺寸的纳米通道的制作方法 |
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KR20190100035A (ko) | 2019-08-28 |
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TW201937575A (zh) | 2019-09-16 |
US10658181B2 (en) | 2020-05-19 |
US20190259612A1 (en) | 2019-08-22 |
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