CN110120427A - A kind of thin-film transistor structure - Google Patents
A kind of thin-film transistor structure Download PDFInfo
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- CN110120427A CN110120427A CN201910351411.8A CN201910351411A CN110120427A CN 110120427 A CN110120427 A CN 110120427A CN 201910351411 A CN201910351411 A CN 201910351411A CN 110120427 A CN110120427 A CN 110120427A
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- layer
- film transistor
- tft
- thin film
- metal conducting
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- 239000010409 thin film Substances 0.000 title claims abstract description 47
- 229910052751 metal Inorganic materials 0.000 claims abstract description 59
- 239000002184 metal Substances 0.000 claims abstract description 59
- 239000011521 glass Substances 0.000 claims abstract description 17
- 238000002161 passivation Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 31
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- 239000004411 aluminium Substances 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 229910052750 molybdenum Inorganic materials 0.000 claims description 6
- 239000011733 molybdenum Substances 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 10
- 230000007423 decrease Effects 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 4
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 abstract description 2
- 229910001887 tin oxide Inorganic materials 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 125000001309 chloro group Chemical group Cl* 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Abstract
The present invention provides a kind of thin film transistor (TFT), and the thin film transistor (TFT) includes: glass substrate；First metal conducting layer；Gate insulating layer；A-Si:H layers；n+A-Si:H layers；Second metal conducting layer；Passivation layer；Indium tin oxide layer；Wherein projection of second metal conducting layer on the glass substrate be not be overlapped with projection of first metal conducting layer on the glass substrate, to reduce parasitic capacitance (Cgd), parasitic capacitance decline can improve perforation voltage effects and improve the image quality of panel and promote the display brightness of panel.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of thin film transistor (TFT)s.
Background technique
In technical field of flat panel display, thin film transistor LCD device (Thin Film Transistor
LiquidCrystal Display, abbreviation TFT-LCD) have many advantages, such as that small in size, low in energy consumption, manufacturing cost is relatively low, by
Gradually leading position is occupied in current FPD market.Thin film transistor (TFT) is widely used in various display devices, for example, liquid
Crystal display, organic light emitting diode display etc..
Thin film transistor (TFT) may include gate electrode, source/pole electrode, active layer, gate insulating layer, passivation layer and oxidation
Indium tin layer etc..The structure of thin film transistor (TFT) can be divided into bottom grating structure and top gate structure.Current liquid crystal display is widely used
Be bottom grating structure.According to the difference of manufacture craft, bottom grating structure is generally divided into back channel-etch type structure (Back-channel
Etchant, BCE) and etch stopper stratotype structure (Etched-stopper Layer, ESL).Two kinds of structures are compared, and channel is carried on the back
The processing steps of etching structure are less, i.e., its cost of manufacture is less expensive, currently, panel vendor is all widely used back channel
On the one hand etching type structure is the requirement that its electrology characteristic is able to satisfy display, in addition has benefited from mentioning for design and processes technology
It rises, the processing procedure for carrying on the back channel-etch type structure is simpler.
And current back channel-etch type configuration thin film transistor is due to the projection area coverage of source-drain electrode and gate electrode
It is larger, it is larger so as to cause the parasitic capacitance (Cgd) of thin film transistor (TFT), and perforation voltage is generated, lead to the image quality of display panel
Poor, brightness is lower.Parasitic capacitance (Cgd) decline can improve perforation voltage effects and improve the image quality and panel of panel
Display brightness.
Summary of the invention
The present invention provides a kind of thin film transistor (TFT), can reduce or even eliminate the projection covering surface of source-drain electrode and gate electrode
Product, it is larger to solve the parasitic capacitance (Cgd) of back channel-etch type configuration thin film transistor of the prior art, to generate perforation
Voltage causes the image quality of display panel poor, the lower technical problem of brightness.
To solve the above problems, technical solution provided by the invention is as follows:
The present invention provides a kind of thin film transistor (TFT), and the thin film transistor (TFT) includes:
Glass substrate；
First metal conducting layer is arranged above the glass substrate；
Gate insulating layer is covered on above first metal conducting layer；
A-Si:H layers, setting is square on the gate insulating layer；
n+A-Si:H layers, a-Si:H layers of the top is set；
Second metal conducting layer is arranged in the n+On a-Si:H layer；
Passivation layer is covered on second metal conducting layer and gate insulating layer；And
Indium tin oxide layer is arranged on the passivation layer, and the indium tin oxide layer part covers the passivation layer；
Wherein projection of second metal conducting layer on the glass substrate and first metal conducting layer are in institute
The projection stated on glass substrate is not overlapped.
Thin film transistor (TFT) provided by according to embodiments of the present invention, the part a-Si:H layers of cover the gate insulator
Layer.
Thin film transistor (TFT) provided by according to embodiments of the present invention, the n+A-Si:H layers set only at described a-Si:H layers
Both sides position, and partially cover a-Si:H layers described.
Thin film transistor (TFT) provided by according to embodiments of the present invention, second metal conducting layer are divided into positioned at left side n+a-
Si:H layers top left side second metal conducting layer and be located at right side n+Right side second metal of a-Si:H layers of top
Conductive layer.
Thin film transistor (TFT) provided by according to embodiments of the present invention, the passivation layer is in right side second metal conducting layer
The first opening of top setting.
Thin film transistor (TFT) provided by according to embodiments of the present invention, the indium tin oxide layer are open and position by described first
Second metal conducting layer in right side connects.
According to embodiments of the present invention provided by thin film transistor (TFT), first metal conducting layer be at least molybdenum, aluminium, titanium and
Any metal in copper.
According to embodiments of the present invention provided by thin film transistor (TFT), second metal conducting layer be at least molybdenum, aluminium, titanium and
Any metal in copper.
Thin film transistor (TFT) provided by according to embodiments of the present invention, the gate insulating layer, a-Si:H layers and the institute
State n+A-Si:H layers of three-layer thin-film are to deposit to complete by chemical vapour deposition technique one-time continuous.
The present invention also provides a kind of display device, it includes film described in any of the above embodiments that the display device, which has used,
Transistor.
The invention has the benefit that the projection area coverage of source-drain electrode and gate electrode is reduced or even eliminated, to subtract
Small parasitic capacitance (Cgd), parasitic capacitance (Cgd) decline can improve perforation voltage effects and improve the image quality of panel and mention
Rise the display brightness of panel.
Detailed description of the invention
It, below will be to embodiment or the prior art in order to illustrate more clearly of embodiment or technical solution in the prior art
Attached drawing needed in description is briefly described, it should be apparent that, the accompanying drawings in the following description is only some of invention
Embodiment for those of ordinary skill in the art without creative efforts, can also be attached according to these
Figure obtains other attached drawings.
Fig. 1 is the structural schematic diagram of thin film transistor (TFT) provided in an embodiment of the present invention.
Fig. 2 is the top view of thin-film transistor structure provided in an embodiment of the present invention.
Specific embodiment
The explanation of following embodiment is referred to the additional illustration, the particular implementation that can be used to implement to illustrate the present invention
Example.The direction term that the present invention is previously mentioned, such as [on], [under], [preceding], [rear], [left side], [right side], [interior], [outer], [side]
Deng being only the direction with reference to annexed drawings.Therefore, the direction term used be to illustrate and understand the present invention, rather than to
The limitation present invention.The similar unit of structure is with being given the same reference numerals in the figure.
The present invention is larger for the parasitic capacitance (Cgd) of the back channel-etch type configuration thin film transistor of the prior art, from
And perforation voltage is generated, cause the image quality of display panel poor, the lower technical problem of brightness, the present embodiment is able to solve this and lacks
It falls into.
Further to illustrate technological means and its effect adopted by the present invention, below in conjunction with preferred implementation of the invention
Example and its attached drawing are described in detail.
As shown in Figure 1, the embodiment of the invention provides a kind of thin-film transistor structures.The thin film transistor (TFT) 100 includes:
Glass substrate 101, the glass substrate 101 are placed in the position of the bottom；
The top of the glass substrate 101 is arranged in first metal conducting layer 103；
Gate insulating layer 102 is covered on 103 top of the first metal conducting layer；
A-Si:H layer 104 is arranged above the gate insulating layer 102；
n+The top of the a-Si:H layer 104 is arranged in a-Si:H layer 105；
Second metal conducting layer 106 is arranged in the n+On a-Si:H layer 105；
Passivation layer 107 is covered on second metal conducting layer 106 and gate insulating layer 102；And
Indium tin oxide layer 108 is arranged on the passivation layer 107, and 108 part of indium tin oxide layer covers the passivation
Layer 107；
In the thin film transistor (TFT) 100, second metal conducting layer 106 is projected in first metal conducting layer
The area being not covered on 103.
Specifically, first metal conducting layer 103 is the gate electrode as thin film transistor (TFT) 100, wherein described first
Metal conducting layer 103 is at least any metal or other available metals in molybdenum, aluminium, titanium and copper.
The gate insulating layer 102 is usually g-SiNx, the gate insulating layer 102 is completely covered first metal and leads
Electric layer 103 and the glass substrate 101.Wherein, when making thin film transistor (TFT) 100, chemical vapour deposition technique is generally used
To prepare the gate insulating layer 102.
The a-Si:H layer 104 is used as active layer, and 104 part of a-Si:H layer covers the gate insulating layer 102.Institute
The structure that gate insulating layer 102 forms stairstepping after over etching is stated, wherein a-Si:H layer 104 is then partially covered on institute
State the top of gate insulating layer 102.
The n+A-Si:H layer 105 is as the ohmic contact layer between semiconductor and metal layer, the n+A-Si:H layers
105 are arranged in the both sides position of the a-Si:H layer 104, and part covers the a-Si:H layer 104.
Second metal conducting layer 106 is used as source-drain electrode layer, is arranged in the n+On a-Si:H layer 105, described second
Metal conducting layer 106 divides for positioned at left side n+Left side second metal conducting layer 1061 of the top of a-Si:H layer 1051 and it is located at
Right side n+Right side second metal conducting layer 1062 of 1052 top of a-Si:H layer.Second metal conducting layer, 106 part
Cover the n+A-Si:H layer 105.Second metal conducting layer 106 be at least molybdenum, aluminium, titanium and copper in any metal or other
Metal can be used.
Second metal conducting layer 106, the gate insulating layer 102 and glass is completely covered in the passivation layer 107
Substrate 101.The first opening 109 is arranged in the passivation layer 107 above second metal conducting layer 1062 of right side.Described first
Opening 109 can expose right side second metal conducting layer 1062.
108 part of indium tin oxide layer covers the passivation layer 107, and the indium tin oxide layer 108 passes through described first
Opening 109 is connect with second metal conducting layer 1062 for being located at right side.
Specifically, as shown in Fig. 2, second metal conducting layer 106 is projected on first metal conducting layer 103
Area coverage become smaller or almost without, therefore the parasitic capacitance between grid layer and source-drain electrode layer can decline, thus with this
The relevant perforation voltage of parasitic capacitance also reduced, and improves the image quality of panel and improves the brightness of panel.
Specifically, in the present embodiment, the gate insulating layer 102, a-Si:H layer 104 and the n+a-Si:H
105 three-layer thin-film of layer are to deposit to complete by chemical vapour deposition technique one-time continuous.After the silicon island of thin film transistor (TFT) 100 is formed
Use the ohmic contact layer n of dry or wet etch silicon island channel region+A-Si:H layer 105, therefore inevitably can also etch
Fall certain thickness a-Si:H layer 104, so thicker a-Si:H layer 104 is needed, it could be in etching n+When a-Si:H layer 105
Make to have etched after part a-Si:H layer 104 so that also there are enough thickness.A-Si:H layer 104 and n are etched in the present embodiment+a-
Si:H layer 105 generallys use fluorine-based or chloro plasma etching.
In conclusion although the present invention has been disclosed above in the preferred embodiment, but above preferred embodiment is not to limit
The system present invention, those skilled in the art can make various changes and profit without departing from the spirit and scope of the present invention
Decorations, therefore protection scope of the present invention subjects to the scope of the claims.
Claims (10)
1. a kind of thin film transistor (TFT), which is characterized in that the thin film transistor (TFT) includes:
Glass substrate；
First metal conducting layer is arranged above the glass substrate；
Gate insulating layer is covered on above first metal conducting layer；
A-Si:H layers, setting is square on the gate insulating layer；
n+A-Si:H layers, a-Si:H layers of the top is set；
Second metal conducting layer is arranged in the n+On a-Si:H layer；
Passivation layer is covered on second metal conducting layer and gate insulating layer；And
Indium tin oxide layer is arranged on the passivation layer, and the indium tin oxide layer part covers the passivation layer；
Wherein projection of second metal conducting layer on the glass substrate and first metal conducting layer are in the glass
Projection on glass substrate is not overlapped.
2. thin film transistor (TFT) according to claim 1, which is characterized in that it is exhausted that the part a-Si:H layers of covers the grid
Edge layer.
3. thin film transistor (TFT) according to claim 1, which is characterized in that the n+A-Si:H layers are arranged in the a-Si:H
The both sides position of layer, and partially cover a-Si:H layers described.
4. thin film transistor (TFT) according to claim 1, which is characterized in that second metal conducting layer is divided into positioned at left side
n+A-Si:H layers top left side second metal conducting layer and be located at right side n+Right side second gold medal of a-Si:H layers of top
Belong to conductive layer.
5. thin film transistor (TFT) according to claim 1, which is characterized in that the passivation layer is led in right side second metal
The first opening of setting above electric layer.
6. thin film transistor (TFT) according to claim 5, which is characterized in that the indium tin oxide layer is open by described first
It is connect with right side second metal conducting layer is located at.
7. thin film transistor (TFT) according to claim 1, which is characterized in that first metal conducting layer be at least molybdenum, aluminium,
Any metal in titanium and copper.
8. thin film transistor (TFT) according to claim 1, which is characterized in that second metal conducting layer be at least molybdenum, aluminium,
Any metal in titanium and copper.
9. thin film transistor (TFT) according to claim 1, which is characterized in that the gate insulating layer, it is described a-Si:H layers with
And the n+A-Si:H layers of three-layer thin-film are to deposit to complete by chemical vapour deposition technique one-time continuous.
10. a kind of display device, including such as the described in any item thin film transistor (TFT)s of claim 1-9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910351411.8A CN110120427A (en) | 2019-04-28 | 2019-04-28 | A kind of thin-film transistor structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910351411.8A CN110120427A (en) | 2019-04-28 | 2019-04-28 | A kind of thin-film transistor structure |
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| CN201910351411.8A Pending CN110120427A (en) | 2019-04-28 | 2019-04-28 | A kind of thin-film transistor structure |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010007358A1 (en) * | 1997-10-21 | 2001-07-12 | Kabushiki Kaisha Advanced Display | Liquid crystal display and manufacturing process of thin film transistor used therein |
| US20110122330A1 (en) * | 2009-11-23 | 2011-05-26 | Samsung Mobile Display Co., Ltd. | Liquid crystal display device and method of fabrication for the same |
| CN109378345A (en) * | 2018-10-11 | 2019-02-22 | 深圳市华星光电技术有限公司 | Thin film transistor (TFT) and its manufacturing method |
-
2019
- 2019-04-28 CN CN201910351411.8A patent/CN110120427A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010007358A1 (en) * | 1997-10-21 | 2001-07-12 | Kabushiki Kaisha Advanced Display | Liquid crystal display and manufacturing process of thin film transistor used therein |
| US20110122330A1 (en) * | 2009-11-23 | 2011-05-26 | Samsung Mobile Display Co., Ltd. | Liquid crystal display device and method of fabrication for the same |
| CN109378345A (en) * | 2018-10-11 | 2019-02-22 | 深圳市华星光电技术有限公司 | Thin film transistor (TFT) and its manufacturing method |
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Application publication date: 20190813 |