CN110112204B - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
- Publication number
- CN110112204B CN110112204B CN201910486198.1A CN201910486198A CN110112204B CN 110112204 B CN110112204 B CN 110112204B CN 201910486198 A CN201910486198 A CN 201910486198A CN 110112204 B CN110112204 B CN 110112204B
- Authority
- CN
- China
- Prior art keywords
- interlayer dielectric
- layer
- dielectric layer
- substrate
- groove structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/124—Insulating layers formed between TFT elements and OLED elements
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
The invention discloses an array substrate, a display panel and a display device, which aim to solve the problem that an OLED display panel in the prior art is easy to break an interlayer dielectric layer after being bent for multiple times, so that the OLED display panel is failed. The array substrate comprises a grid electrode, an interlayer dielectric structure and a source drain electrode layer which are sequentially positioned on one surface of a substrate base plate, wherein the interlayer dielectric structure is a laminated structure comprising an organic interlayer dielectric layer and an inorganic interlayer dielectric layer, and the organic interlayer dielectric layer is positioned on one surface, facing the substrate base plate, of the inorganic interlayer dielectric layer.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an array substrate, a display panel and a display device.
Background
Flat Panel Displays (FPDs) have become the mainstream products in the market, and the types of Flat Panel displays are increasing, such as Liquid Crystal Displays (LCDs), Organic Light Emitting Diodes (OLEDs), Plasma Display Panels (PDPs), and Field Emission Displays (FEDs).
The Low Temperature polysilicon technology (LTPS) TFT-LCD has the advantages of high resolution, fast reaction speed, high brightness, high aperture ratio, etc. in addition, the silicon crystal arrangement of the LTPS-TFT LCD is ordered compared with that of a-Si, so that the electron mobility is relatively higher by more than 100 times, a peripheral driving circuit can be simultaneously manufactured on a glass substrate, the goal of system integration is reached, and the space and the cost of driving an IC are saved. Meanwhile, the LTPS-derived AMOLED has the advantages of high image quality, short moving image response time, low power consumption, wide viewing angle, ultra-light weight and the like, and becomes the best choice of future display technologies. Along with the rapid development and popularization of electronic products carrying flexible display, such as smart phones, wearable equipment, vehicle-mounted display, AR/VR (augmented reality/visual reality), the market of medium and small-sized products presents vigorous demand, particularly, the AMOLED technology is taken as a representative high-performance novel display technology, and the advanced high-end smart phone market is accelerated by the unique performance advantages of the display technology in the aspects of display performance, lightness, thinness, flexibility, foldability and the like.
However, after the conventional OLED display panel is bent for many times, the interlayer dielectric layer is easy to break, so that the problem that the OLED display panel fails is caused.
Disclosure of Invention
The invention provides an array substrate, a display panel and a display device, which aim to solve the problem that an OLED display panel in the prior art is easy to break an interlayer dielectric layer after being bent for multiple times, so that the OLED display panel is failed.
The embodiment of the invention provides an array substrate, which comprises a grid, an interlayer dielectric structure and a source drain layer which are sequentially positioned on one surface of a substrate, wherein the interlayer dielectric structure is a laminated structure comprising an organic interlayer dielectric layer and an inorganic interlayer dielectric layer, and the organic interlayer dielectric layer is positioned on one surface of the inorganic interlayer dielectric layer, which faces to the substrate.
In one possible embodiment, the thickness of the organic interlayer dielectric layer is greater than the thickness of the inorganic interlayer dielectric layer.
In one possible implementation, the semiconductor device further comprises a gate insulating layer located between the substrate base plate and the gate, and an active layer located between the substrate base plate and the gate insulating layer;
the gate insulating layer is provided with a first groove structure with an opening facing the interlayer dielectric structure, the organic interlayer dielectric layer fills the first groove structure, and the orthographic projection of the first groove structure on the substrate is not overlapped with the orthographic projection of the active layer and the gate on the substrate.
In one possible embodiment, the first groove structure penetrates through the gate insulating layer.
In one possible embodiment, the organic interlayer dielectric further includes a buffer layer located between the substrate and the active layer, the buffer layer has a second groove structure opened toward the gate insulating layer at a position corresponding to the first groove structure, and the organic interlayer dielectric layer fills the second groove structure.
In one possible embodiment, the second groove structure extends through the buffer layer.
In a possible embodiment, the first groove structures are distributed periodically or the first groove structures are distributed non-periodically.
In one possible embodiment, an orthogonal projection of the first groove structure on the substrate base plate is square, rectangular, or circular.
The embodiment of the invention also provides a display panel, which comprises the array substrate provided by the embodiment of the invention.
The embodiment of the invention also provides a display device which comprises the display panel provided by the embodiment of the invention.
The embodiment of the invention has the following beneficial effects: the array substrate provided by the invention is characterized in that the interlayer dielectric structure is a laminated structure comprising an organic interlayer dielectric layer and an inorganic interlayer dielectric layer, the organic interlayer dielectric layer is positioned on one surface of the inorganic interlayer dielectric layer facing the substrate, namely, the interlayer dielectric structure of the embodiment of the invention is a laminated structure of the organic interlayer dielectric layer and the inorganic interlayer dielectric layer, the organic interlayer dielectric layer has bending resistance, and further, the display panel made of the array substrate can have stronger bending resistance in the bending process, the problem of interlayer dielectric structure fracture is not easy to occur in the multiple bending processes, the inorganic interlayer dielectric layer on the other side of the organic interlayer dielectric layer can play a good insulating role, and further, the interlayer dielectric structure has better insulating role and can improve the problem that the OLED display panel in the prior art is bent for multiple times, the problem that the interlayer dielectric structure is easy to break, so that the OLED display panel is failed can be solved, and the problem that the thicker inorganic interlayer dielectric layer is very easy to break when the interlayer dielectric layer only comprises the thicker inorganic interlayer dielectric layer can be avoided.
Drawings
Fig. 1 is a schematic cross-sectional structural view of an array substrate according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an array substrate having a gate insulating layer with a first groove structure according to an embodiment of the present invention;
fig. 3 is a schematic top view of an array substrate according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an array substrate with a first groove structure penetrating through a gate insulating layer according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of an array substrate with a second groove structure disposed on a buffer layer according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of an array substrate in which a second groove structure penetrates through a buffer layer according to an embodiment of the present invention;
fig. 7 is a schematic view of a manufacturing process of an array substrate according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described below clearly and completely with reference to the accompanying drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
To maintain the following description of the embodiments of the present disclosure clear and concise, a detailed description of known functions and known components have been omitted from the present disclosure.
In the conventional method, the flexible LTPS AMOLED/LCD method mainly uses Poly TFTs and a Polyimide (PI) substrate to achieve temporary local bending, and the bending can be performed only within a certain range. However, the LTPS-AMOLED technology is mostly completed by using an inorganic layer and a metal layer. At the later stage of the conventional LTPS AMOLED flexible display device, the functions of true folding, bending resistance, abrasion resistance and tensile resistance are very difficult to realize. After being bent for many times, the inorganic layer and the metal layer generate stress and generate cracks, so that the problem of failure of the whole display device is easily caused. Especially, the failure rate of a thicker inorganic interlayer Dielectric (ILD) Layer and an LTP-TFT below the ILD Layer is higher, the electrical property of the TFT device after being bent for many times is degraded, and the reliability test cannot be satisfied. Inorganic ILD in a flexible AMOLED product of the common approach: the SiO2/SiNx is larger than 5000A, is the thickest inorganic film layer in the LTPS-TFT, and is easy to cause stress and failure after bending.
Based on this, referring to fig. 1, an embodiment of the present invention provides an array substrate, including a gate 2, an interlayer dielectric structure 4, and a source drain layer 3, which are sequentially located on one side of a substrate 1, where the interlayer dielectric structure 4 is a stacked structure including an organic interlayer dielectric layer 41 and an inorganic interlayer dielectric layer 42, and the organic interlayer dielectric layer 41 is located on one side of the inorganic interlayer dielectric layer 42 facing the substrate 1.
In the array substrate provided by the embodiment of the invention, the interlayer dielectric structure 4 is a laminated structure comprising an organic interlayer dielectric layer 41 and an inorganic interlayer dielectric layer 42, the organic interlayer dielectric layer 41 is positioned on one surface of the inorganic interlayer dielectric layer 42 facing the substrate 1, namely, the interlayer dielectric structure 4 of the embodiment of the invention is the laminated structure of the organic interlayer dielectric layer 41 and the inorganic interlayer dielectric layer 42, wherein the organic interlayer dielectric layer 41 has bending resistance, and further, the display panel made of the array substrate can have stronger bending resistance in the bending process, the problem that the interlayer dielectric structure 4 is broken is difficult to occur in the multiple bending processes, and the inorganic interlayer dielectric layer 42 on the other side of the organic interlayer dielectric layer 41 can play a good insulating role, so that the problem that other display defects are caused when the interlayer dielectric layer 4 only comprises the organic interlayer dielectric layer 41 is avoided, furthermore, the interlayer dielectric structure 4 has a good insulating effect, and meanwhile, the problem that the interlayer dielectric structure 4 is easy to break after the OLED display panel in the prior art is bent for multiple times, so that the OLED display panel is failed can be solved, and the problem that the thicker inorganic interlayer dielectric layer is very easy to break when the interlayer dielectric structure only comprises the thicker inorganic interlayer dielectric layer can be avoided.
In practical implementation, the array substrate in the embodiment of the invention may be an array substrate of an OLED display panel. The substrate 1 may be a flexible substrate, and the material may be a Polyimide (PI) substrate. The gate 2 and the source/drain layer 3 may be film layers of a thin film transistor, and the thin film transistor may further include a gate insulating layer 5 located between the gate 2 and the substrate 1, and an active layer 6 located between the gate insulating layer 5 and the substrate 1. The thin film transistor of the embodiment of the invention can be specifically a top gate type thin film transistor, the source drain layer 3 can specifically comprise a source electrode and a drain electrode, and the source electrode and the drain electrode can be respectively conducted with the active layer 6 through a through hole penetrating through the interlayer dielectric structure 4 and the gate insulation layer 5.
In particular implementation, referring to fig. 1, the thickness of the organic interlayer dielectric layer 41 is greater than the thickness of the inorganic interlayer dielectric layer 42. In the embodiment of the invention, the thickness of the organic interlayer dielectric layer 41 is greater than that of the inorganic interlayer dielectric layer 42, so that the interlayer dielectric structure 4 has stronger bending resistance.
In specific implementation, the array substrate further includes a gate insulating layer 5 located between the substrate 1 and the gate 2, and an active layer 6 located between the substrate 1 and the gate insulating layer 5; referring to fig. 2, the gate insulating layer 5 has a first groove structure 50 with an opening facing the interlayer dielectric structure 4, the organic interlayer dielectric layer 41 fills the first groove structure 50, and an orthographic projection of the first groove structure 50 on the substrate 1 is not overlapped with an orthographic projection of the active layer 6 and the gate 2 on the substrate 1. In the embodiment of the present invention, the gate insulating layer 5 further has the first groove structure 50, that is, the gate insulating layer 5 below the organic interlayer dielectric layer 41 is grooved, and the arrangement of the first groove structure 50 can disperse the stress of the organic interlayer dielectric layer 41 during bending, thereby further enhancing the bending resistance of the organic interlayer dielectric layer 41. In addition, since the gate insulating layer 5 is generally an inorganic layer, the inorganic gate insulating layer 5 is hollowed in a region where the active layer 6 is not present, that is, the entire array substrate has a small region where the inorganic gate insulating layer 5 is present, and the gate insulating layer 5 can have a good bending performance even when bent. In addition, the first groove structure 50 is filled and flat through the organic interlayer dielectric layer 41, so that the surface of the array substrate can be very flat, and the source/drain layer 3 laid subsequently can be prevented from being broken.
It should be noted that the orthographic projection of the first groove structure 50 on the substrate base plate 1 and the orthographic projection of the active layer 6 on the substrate base plate 1 do not overlap with each other, that is, when the gate insulating layer 5 is trenched, it is necessary to avoid digging the active layer 6 below the gate insulating layer 5, specifically, the orthographic projection of the first groove structure 50 on the substrate base plate 1 and the orthographic projection of the gate 2, the source and the drain may not overlap with each other, that is, holes may be dug in other regions of the gate insulating layer 5 except for the region corresponding to the thin film transistor. Specifically, as shown in fig. 3, the first groove structure 50 may be formed mainly in the display area (AA ') and the area where the GOA is located, or the first groove structure may be formed in the peripheral packaging area (the area where the frame sealing glue Seal is located), the bonding area (i.e., the area between the AA' area and the PFC PADs in fig. 3), or the non-bonding area (non-Pad bonding area).
In specific implementation, referring to fig. 4, the first groove structure 50 penetrates through the gate insulating layer 5. In the embodiment of the present invention, the first groove structure 50 penetrates through the gate insulating layer 5, so that the bending resistance of the gate insulating layer 5 can be maximized.
In specific implementation, referring to fig. 5, the array substrate further includes a buffer layer 7 located between the substrate 1 and the active layer 6, the buffer layer 7 has a second groove structure 70 opened toward the gate insulating layer 5 at a position corresponding to the first groove structure 50, and the organic interlayer dielectric layer 41 fills the second groove structure 70. That is, in the embodiment of the present invention, the buffer layer 7 is also grooved and filled with the organic interlayer dielectric layer 41, and the buffer layer 7 may have a better bending resistance. Moreover, the second groove structure 70 is located at a position corresponding to the first groove structure 50, and the second groove structure 70 can be directly formed while the first groove structure 50 is formed, that is, the first groove structure 50 of the gate insulating layer 5 and the second groove structure 70 of the buffer layer 7 can be formed by a single patterning process, so that the manufacturing processes of the first groove structure 50 and the second groove structure 70 can be simplified.
In a specific implementation, referring to fig. 6, the second groove structure 70 penetrates the buffer layer 7. In the embodiment of the present invention, the second groove structure 70 penetrates through the buffer layer 7, so that the bending resistance of the buffer layer 7 can be maximized.
In a specific implementation, the substrate base plate 1 may be grooved at a position corresponding to the first groove structure 50 to form a third groove structure, but the third groove structure is a structure that does not penetrate through the substrate base plate 1. In addition, when other film layers are further provided between the organic interlayer dielectric layer 41 of the array substrate and the substrate 1, the other film layers may also be grooved at positions corresponding to the first groove structures 50.
In a specific implementation, the first groove structures 50 may be periodically distributed. In the embodiment of the present invention, the first groove structures 50 are periodically distributed, so that the bending resistance of each position of the array substrate is substantially consistent. Of course, if it is not considered whether the bending resistance of each position of the array substrate is consistent, the first groove structures 50 may be non-periodically arranged.
In practical implementation, the orthographic projection of the first groove structure 50 on the substrate base plate 1 is square, rectangular or circular. In the embodiment of the present invention, the orthographic projection of the first groove structure 50 on the substrate is square, rectangular, or circular, which is convenient for manufacturing the first groove structure 50. Similarly, the orthographic projection of the second groove structure 70 on the substrate base plate 1 can also be square, rectangular or circular. The orthographic projection of the second groove structure 70 on the substrate base plate 1 and the orthographic projection of the first groove structure 50 on the substrate base plate 1 may be specifically the same. The overall structural shape of the second groove structure 70 is also the same as that of the first groove structure 50 to be completed through a one-time patterning process. Specifically, the size of the first groove structure is 2-10 micrometers. That is, for example, when the orthographic projection of the substrate base plate 1 is a circle, the diameter of the circle is 2 to 10 micrometers.
In specific implementation, the manufacturing process of the array substrate may be as shown in fig. 7, that is, a patterned Active layer (Active) is formed on one side of the substrate through a first mask process; forming a patterned Gate on one surface of the active layer, which is far away from the substrate, by a second mask process (specifically, forming dual-Gate gates 1 and Gate2 by two second mask processes); performing Hole digging (Gate Hole, of course, before the third mask process, a Gate insulating layer may also be formed on the side of the Gate electrode away from the active layer) on the Gate insulating layer by using a third mask process to form a first groove structure; forming via holes exposing the active layer on the interlayer dielectric structure by a fourth mask process so as to conduct the subsequently formed source and drain electrodes with the active layer (of course, before the fourth mask process, the active layer can be doped with Dopant Activation and Hydrogenation process); forming a patterned source drain layer (SD) through a fifth mask process; forming a patterned Planarization Layer (PLN) through a sixth mask process; forming a patterned Anode (Anode) through a seventh mask process; forming a patterned Pixel Defining Layer (PDL) through an eighth mask process; and forming a patterned spacer layer (PS) through a ninth mask process.
Based on the same inventive concept, an embodiment of the present invention further provides a display panel, including the array substrate provided in the embodiment of the present invention.
Based on the same inventive concept, the embodiment of the invention further provides a display device, which comprises the display panel provided by the embodiment of the invention.
The embodiment of the invention has the following beneficial effects: the array substrate provided by the invention is characterized in that the interlayer dielectric structure is a laminated structure comprising an organic interlayer dielectric layer and an inorganic interlayer dielectric layer, the organic interlayer dielectric layer is positioned on one surface of the inorganic interlayer dielectric layer facing the substrate, namely, the interlayer dielectric structure of the embodiment of the invention is a laminated structure of the organic interlayer dielectric layer and the inorganic interlayer dielectric layer, the organic interlayer dielectric layer has bending resistance, and further, a display panel made of the array substrate can have stronger bending resistance in the bending process, the problem of interlayer dielectric structure fracture is not easy to occur in the multiple bending processes, the inorganic interlayer dielectric layer on the other side of the organic interlayer dielectric layer can play a good insulating role, and further, the interlayer dielectric structure has better insulating role and can also improve the problem that the OLED display panel in the prior art is bent for multiple times, the problem that the interlayer dielectric structure is easy to break, so that the OLED display panel is failed can be solved, and the problem that the thicker inorganic interlayer dielectric layer is very easy to break when the interlayer dielectric layer only comprises the thicker inorganic interlayer dielectric layer can be avoided.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (7)
1. An array substrate is characterized by comprising a buffer layer, an active layer, a grid insulation layer, a grid, an interlayer dielectric structure and a source drain layer which are sequentially positioned on one surface of a substrate, wherein the interlayer dielectric structure is a laminated structure comprising an organic interlayer dielectric layer and an inorganic interlayer dielectric layer, the organic interlayer dielectric layer is positioned on one surface of the inorganic interlayer dielectric layer facing the substrate, and the grid insulation layer is provided with a first groove structure with an opening facing the interlayer dielectric structure; the organic interlayer dielectric layer is in direct surface contact with the gate insulating layer in the region outside the first groove structure, and the inorganic interlayer dielectric layer is in direct surface contact with the source drain layer in the region outside the first groove structure;
the thickness of the organic interlayer dielectric layer is greater than that of the inorganic interlayer dielectric layer;
The buffer layer is provided with a second groove structure with an opening facing the grid electrode insulation layer at a position corresponding to the first groove structure, the organic interlayer dielectric layer fills the first groove structure and the second groove structure and is in contact with the substrate base plate, and the substrate base plate is made of polyimide.
2. The array substrate of claim 1, wherein an orthographic projection of the first groove structure on the substrate does not overlap with an orthographic projection of the active layer and the gate electrode on the substrate.
3. The array substrate of claim 2, wherein the first recess structure extends through the gate insulating layer.
4. The array substrate of claim 2, wherein the first groove structures are periodically distributed or the first groove structures are non-periodically distributed.
5. The array substrate of claim 4, wherein the orthographic projection of the first groove structure on the substrate is square, rectangular or circular.
6. A display panel comprising the array substrate according to any one of claims 1 to 5.
7. A display device characterized by comprising the display panel according to claim 6.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910486198.1A CN110112204B (en) | 2019-06-05 | 2019-06-05 | Array substrate, display panel and display device |
| PCT/CN2020/088131 WO2020244350A1 (en) | 2019-06-05 | 2020-04-30 | Array substrate, display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910486198.1A CN110112204B (en) | 2019-06-05 | 2019-06-05 | Array substrate, display panel and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110112204A CN110112204A (en) | 2019-08-09 |
| CN110112204B true CN110112204B (en) | 2022-07-29 |
Family
ID=67493966
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910486198.1A Active CN110112204B (en) | 2019-06-05 | 2019-06-05 | Array substrate, display panel and display device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN110112204B (en) |
| WO (1) | WO2020244350A1 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110112204B (en) * | 2019-06-05 | 2022-07-29 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
| CN111063812A (en) * | 2019-10-22 | 2020-04-24 | 武汉华星光电半导体显示技术有限公司 | Array substrate and display panel |
| CN111463267A (en) * | 2020-04-08 | 2020-07-28 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
| CN114551477A (en) * | 2022-02-09 | 2022-05-27 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
| CN115117093A (en) * | 2022-06-14 | 2022-09-27 | 厦门天马微电子有限公司 | Display panel, manufacturing method thereof and display device |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6336765B2 (en) * | 2014-01-31 | 2018-06-06 | 株式会社ジャパンディスプレイ | Display device |
| KR102280265B1 (en) * | 2014-10-06 | 2021-07-22 | 삼성디스플레이 주식회사 | Thin film transistor array substrate and organic light-emitting display including the same |
| CN106601778B (en) * | 2016-12-29 | 2019-12-24 | 深圳市华星光电技术有限公司 | OLED backboard and manufacturing method thereof |
| CN108336027A (en) * | 2018-01-12 | 2018-07-27 | 武汉华星光电半导体显示技术有限公司 | A kind of array substrate, OLED display panel and OLED display |
| CN109065583B (en) * | 2018-08-06 | 2020-10-16 | 武汉华星光电半导体显示技术有限公司 | Manufacturing method of flexible display panel and flexible display panel |
| CN109300964B (en) * | 2018-10-26 | 2020-10-16 | 武汉华星光电半导体显示技术有限公司 | Flexible OLED panel and manufacturing method thereof |
| CN109671748B (en) * | 2018-12-12 | 2020-06-16 | 武汉华星光电半导体显示技术有限公司 | Display panel and manufacturing method thereof |
| CN109638054B (en) * | 2018-12-18 | 2020-11-24 | 武汉华星光电半导体显示技术有限公司 | Display panel and manufacturing method |
| CN110112204B (en) * | 2019-06-05 | 2022-07-29 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
-
2019
- 2019-06-05 CN CN201910486198.1A patent/CN110112204B/en active Active
-
2020
- 2020-04-30 WO PCT/CN2020/088131 patent/WO2020244350A1/en active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| CN110112204A (en) | 2019-08-09 |
| WO2020244350A1 (en) | 2020-12-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110112204B (en) | Array substrate, display panel and display device | |
| US11800783B2 (en) | Array substrate, stretchable display device, and method for manufacturing array substrate | |
| US10714707B2 (en) | Organic light-emitting display apparatus and fabrication method thereof | |
| US10741789B2 (en) | Flexible display device | |
| US10014491B2 (en) | Organic light-emitting diode display and manufacturing method thereof | |
| KR102654925B1 (en) | Display apparatus and manufacturing method of the same | |
| US10748853B2 (en) | Flexible display device | |
| US10249652B2 (en) | Manufacturing method of flexible TFT substrate | |
| KR101416718B1 (en) | Organic Light Emitting diode Display device | |
| US10170728B2 (en) | Display device | |
| CN104637983A (en) | Organic light emitting diode display device and method of fabricating the same | |
| KR20140080238A (en) | Method for fabricaing flexible display module | |
| KR20150101002A (en) | Display device | |
| US11342397B2 (en) | Array substrate and manufacturing method thereof | |
| US11329194B2 (en) | Display panel and display device | |
| CN109638021B (en) | Manufacturing method of flexible TFT substrate and manufacturing method of flexible OLED panel | |
| US10685989B2 (en) | Method for manufacturing display panel, display panel, and display device | |
| CN111554721A (en) | Display substrate, manufacturing method and display device | |
| CN111223886A (en) | Display screen and electronic equipment | |
| US20210134897A1 (en) | Display device | |
| CN108121104A (en) | Polarizer, its manufacturing method and with its display device | |
| US20150129842A1 (en) | Method For Manufacturing Organic Electroluminescence Device And Organic Electroluminescence Device Manufactured With Same | |
| CN117038675A (en) | Array substrate, display panel, display device and manufacturing method of array substrate | |
| GB2534691A (en) | Method of manufacturing organic electroluminescence device, and manufactured organic electroluminescence device | |
| CN114335023A (en) | Display panel, preparation method thereof and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |