CN110049263A - A kind of high-speed, high precision phase-locked loop circuit for super large face array CMOS image sensor - Google Patents

A kind of high-speed, high precision phase-locked loop circuit for super large face array CMOS image sensor Download PDF

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CN110049263A
CN110049263A CN201910469549.8A CN201910469549A CN110049263A CN 110049263 A CN110049263 A CN 110049263A CN 201910469549 A CN201910469549 A CN 201910469549A CN 110049263 A CN110049263 A CN 110049263A
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transistor
switch
source
grid
drain terminal
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CN110049263B (en
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曹天骄
刘晓轩
袁昕
李婷
李海松
吴龙胜
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Xian Microelectronics Technology Institute
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Xian Microelectronics Technology Institute
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/30Transforming light or analogous information into electric information
    • H04N5/335Transforming light or analogous information into electric information using solid-state image sensors [SSIS]
    • H04N5/357Noise processing, e.g. detecting, correcting, reducing or removing noise
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/30Transforming light or analogous information into electric information
    • H04N5/335Transforming light or analogous information into electric information using solid-state image sensors [SSIS]
    • H04N5/369SSIS architecture; Circuitry associated therewith
    • H04N5/374Addressed sensors, e.g. MOS or CMOS sensors

Abstract

The invention discloses a kind of high-speed, high precision phase-locked loop circuits for super large face array CMOS image sensor, belong to image sensor technologies field.The phase-locked loop circuit, three-level cross-coupling complementation oscillating unit successively reversely cascade;The grid end of NM5 connects PD signal, and the drain terminal of NM5, the grid end of NM2, the grid end of NM3, the grid end of NM4 are connected with Input voltage terminal, the source of NM2, the source of NM3, the source of NM4 with NM5 source be connected, the drain terminal of NM2 exports Ictrl1, Ictrl1Electric current, which is adjusted, as frequency inputs the first order;The drain terminal of NM3 exports Ictrl2, Ictrl2Electric current, which is adjusted, as frequency inputs the second level;The drain terminal of NM4 exports Ictrl3, Ictrl3Electric current, which is adjusted, as frequency inputs the third level.The phase-locked loop circuit, improves the frequency-tuning range of voltage controlled oscillator in phaselocked loop, and is adjustable the oscillator center frequency of phaselocked loop.

Description

A kind of high-speed, high precision phase-locked loop circuit for super large face array CMOS image sensor
Technical field
The invention belongs to cmos image sensor technical fields, and in particular to one kind is sensed for super large face array CMOS image The high-speed, high precision phase-locked loop circuit of device.
Background technique
In extensive cmos image sensor, high speed readout circuit is mainly under the guidance of timing control, opposite battle array The weak electric signal of output carries out amplification, noise reduction and driving functionally and handles, while realizing the black-level correction in performance and column The high quality output of picture signal is realized in the processing such as FPN correction.
Phase-locked loop circuit is exactly to mention as a high-frequency clock generator, main function in cmos image sensors For meeting the clock of each module work requirements.It is each in reading circuit with the raising of cmos image sensor pixel and frame frequency Module also has the clock demand of higher frequency, this just needs phaselocked loop to have higher frequency, bigger lock-in range and higher Stability.Voltage controlled oscillator as a part most important in phase-locked loop circuit, adjust in real time by the generation and frequency for being responsible for clock Section plays a decisive role to the lock-in range of phaselocked loop, output clock quality and reliability.
The output noise overwhelming majority of clock generator circuit from the noise of voltage controlled oscillator, make an uproar by voltage controlled oscillator Sound main source has noise caused by thermal noise and power supply and ground, and the latter is the main source of voltage controlled oscillator noise.So pressure Control oscillator is also a part critically important in design to the rejection ability of power supply Earth noise.
Summary of the invention
It is an object of the invention to overcome the above-mentioned prior art, provide a kind of for super large face array CMOS image biography The high-speed, high precision phase-locked loop circuit of sensor.
In order to achieve the above objectives, the present invention is achieved by the following scheme:
A kind of high-speed, high precision phase-locked loop circuit for super large face array CMOS image sensor, including reset transistor NM5, crystalline substance Body pipe NM2, transistor NM3, transistor NM4, first order cross-coupling complementation oscillating unit, second level cross-coupling complementation oscillation Unit and third level cross-coupling complementation oscillating unit;
First order cross-coupling complementation oscillating unit, second level cross-coupling complementation oscillating unit and third level cross-coupling Complementary oscillating unit successively reversely cascades;
The grid end of reset transistor NM5 connects PowerDown signal, the drain terminal of reset transistor NM5, the grid end of transistor NM2, transistor The grid end of NM3, the grid end of transistor NM4 are connected with Input voltage terminal, the source of the source of transistor NM2, transistor NM3 End, the source of transistor NM4, the source of reset transistor NM5 are grounded, and the drain terminal of transistor NM2 exports Ictrl1, Ictrl1As Frequency adjusts electric current and inputs first order cross-coupling complementation oscillating unit;
The drain terminal of transistor NM3 exports Ictrl2, Ictrl2It is complementary that electric current input second level cross-coupling is adjusted as frequency Oscillating unit;
The drain terminal of transistor NM4 exports Ictrl3, Ictrl3It is complementary that electric current input third level cross-coupling is adjusted as frequency Oscillating unit.
Further, first order cross-coupling complementation oscillating unit include transistor PM0, transistor PM2, transistor PM3, Transistor PM4, transistor PM5, transistor NM0 and transistor NM1;
The drain terminal of transistor PM0 is mutually shorted with grid end, both inputs Ictrl1, the grid end of transistor PM0 also with crystal Grid end, the transistor PM3 grid end of pipe PM2 is connected, the source of transistor PM0, the source of transistor PM2, transistor PM3 source End, the source of transistor PM4, the source of transistor PM5 connect feeder ear, the drain terminal of transistor PM3 and the drain terminal of transistor PM5 It is connected and is followed by output end, the grid end of transistor PM4 is connected with the drain terminal of transistor NM1 is followed by output end, and output end is for exporting Output signal VOUT1+;
The drain terminal of transistor PM2 is connected with the drain terminal of transistor PM4 is followed by output end, the grid end and crystal of transistor PM5 The drain terminal of pipe NM0, which is connected, is followed by output end, and output end is used for output signal output VOUT1-;
The source of transistor NM0 and the source of transistor NM1 are grounded.
Further, the circuit of second level cross-coupling complementation oscillating unit, third level cross-coupling complementation oscillating unit Structure is identical as the circuit structure of first order cross-coupling complementation oscillating unit;
Wherein, output signal VOUT1-, VOUT1+ of first order cross-coupling complementation oscillating unit is respectively as the second level Input signal VIN2+, VIN2- of cross-coupling complementation oscillating unit;
Output signal VOUT2-, VOUT2+ of second level cross-coupling complementation oscillating unit intersects coupling respectively as the third level Close input signal VIN3+, VIN3- of complementary oscillating unit.
Further, first order cross-coupling complementation oscillating unit, second level cross-coupling complementation oscillating unit and third The output end of grade cross-coupling complementation oscillating unit is equipped with the configurable centre frequency for adjusting oscillating unit load capacitance Adjustment module.
Further, the configurable centre frequency adjustment module include switch M0, switch M1, switch M2, switch M3, PMOS capacitor M4, PMOS capacitor M5, NMOS capacitor M6 and NMOS capacitor M7, switch M0 and switch M3 are NMOS, switch M1 and Switch M2 is PMOS;
The output end of the source of switch M0 and the source of switch M1 oscillating unit complementary with cross-coupling is connected, switch M0 Grid end and the grid end of switch M1 be connected to configuration signal, the drain terminal of switch M0 and the drain terminal of switch M1 it is connected after respectively with PMOS The grid end of capacitor M4, the grid end of NMOS capacitor M6, the source of the source of switch M2 and switch M3 are connected, and the grid end of switch M2 is opened The grid end for closing M3 is connected to configuration signal, grid with PMOS capacitor M5 respectively after the drain terminal of switch M2 is connect with the drain terminal of switch M3 End, NMOS capacitor M7 grid end be connected, the source and drain terminal of PMOS capacitor M4 connects feeder ear, the source and leakage of PMOS capacitor M5 Terminate feeder ear, source and the drain terminal ground connection of NMOS capacitor M6, source and the drain terminal ground connection of NMOS capacitor M7;
When configuring signal TR<1:0>is 00 or 10, switch M0, M1, M2, M3 are in off state;
When configuring signal TR<1:0>is 01, switch M0, M1 are in the open state, and switch M2, M3 are in close state;
When configuring signal TR<1:0>is 11, switch M0, M1, M2, M3 are in open state.
Compared with prior art, the invention has the following advantages:
A kind of high-speed, high precision phase-locked loop circuit for super large face array CMOS image sensor is passed meeting cmos image On the basis of sensor frame frequency and timing requirements, the real-time adjusting of output clock oscillation centre frequency is realized by can configure signal, Improve the frequency-tuning range of voltage controlled oscillator in phaselocked loop;Otherwise for the different input clocks frequency of cmos image sensor Rate, by can configure the bandwidth of Signal Regulation phaselocked loop to meet the stability requirement of clock generator under the conditions of different operating; The phaselocked loop have many advantages, such as high frequency output, flexibly it is adjustable, lock-in range is big and low noise is highly reliable, it is low to can be widely used for high speed Noise reading circuit meets a variety of on piece clock generator demands.
Detailed description of the invention
Fig. 1 is first kind voltage controlled oscillator unit structure chart;
Fig. 2 is the second class voltage controlled oscillator unit structure chart;
Fig. 3 is the high-speed, high precision phase-locked loop circuit structure chart for super large face array CMOS image sensor of the invention;
Fig. 4 is the circuit structure diagram of the difference cross-coupling complementation oscillating unit in the present invention;
Fig. 5 is the circuit structure diagram of the configurable centre frequency adjustment module in the present invention.
Wherein, PMx indicates xth PMOS transistor;
NMx indicates xth NMOS transistor.
Specific embodiment
In order to enable those skilled in the art to better understand the solution of the present invention, below in conjunction in the embodiment of the present invention Attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is only The embodiment of a part of the invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill people The model that the present invention protects all should belong in member's every other embodiment obtained without making creative work It encloses.
It should be noted that description and claims of this specification and term " first " in above-mentioned attached drawing, " Two " etc. be to be used to distinguish similar objects, without being used to describe a particular order or precedence order.It should be understood that using in this way Data be interchangeable under appropriate circumstances, so as to the embodiment of the present invention described herein can in addition to illustrating herein or Sequence other than those of description is implemented.In addition, term " includes " and " having " and their any deformation, it is intended that cover Cover it is non-exclusive include, for example, the process, method, system, product or equipment for containing a series of steps or units are not necessarily limited to Step or unit those of is clearly listed, but may include be not clearly listed or for these process, methods, product Or other step or units that equipment is intrinsic.
The invention will be described in further detail with reference to the accompanying drawing:
It is first kind voltage controlled oscillator unit structure chart referring to Fig. 1, Fig. 1;Fig. 1 is traditional voltage controlled oscillator level-one cross-coupling Complementary oscillating unit structure chart is worked by keyholed back plate M3, M4 in deep linear zone, and the output voltage swing of circuit is in entire frequency-tuning range The amplitude of oscillation changes very greatly in the process.When circuit switches completely, every grade of the differential output amplitude of oscillation reaches 2IssRon3, and 4, output frequency Range is smaller, is unsatisfactory for the performance requirement in cmos image sensor to phaselocked loop.
Referring to fig. 2, Fig. 2 is the second class voltage controlled oscillator unit structure chart;Fig. 2 is that another voltage controlled oscillator level-one intersects coupling Complementary oscillating unit structure chart is closed, compared with conventional surge cellular construction figure, circuit shown in Fig. 2 changes tail electricity by control voltage The size of Iss, the conducting resistance of the conducting resistance tracking M5 of control M3 and M4 are flowed, and passes through while adjusting I1 and Iss and change vibration Swing frequency.If M3, M4, M5 size are identical, I1 and Iss are equidimension current mirror, when M1 and M2 controls tail current from one While Vo+ and Vo- just change from VDD to VDD-Vref when being switched to another side, make to export amplitude variations reduction.But amplifier in Fig. 2 The bandwidth of A1 will affect the stability of this type phaselocked loop, and the type phaselocked loop is weaker to Power supply rejection ability.
It is the high-speed, high precision phase-locked loop circuit for super large face array CMOS image sensor of the invention referring to Fig. 3, Fig. 3 Structure chart;Input voltage Vctrl is being added in transistor NM2, transistor NM3, the grid end generation three of transistor NM4 and Vctrl just Relevant image current Ictrl1,2,3, i.e., the frequency adjusting electric current of every grade cross-coupling complementation oscillating unit, process are as follows: adjust vibration Cell signal reversal rate is swung, achievees the purpose that adjust output frequency.
Referring to fig. 4, Fig. 4 is the circuit structure diagram of the difference cross-coupling complementation oscillating unit in the present invention;The first order is handed over It pitches in coupling and complementing oscillating unit, when VIN1+ changes from low to high, VIN1- changes from high to low, VOUT1+ is by Gao Bianwei Low, VOUT1- becomes high from low;When VIN1+ changes from low to high, VIN1- changes from high to low, VOUT1+ becomes low from height, VOUT1- becomes high from low;If Ictrl1 increases, Ictll1 by transistor PM0 mirror image to transistor PM2 and transistor PM3, The leakage current for flowing through transistor PM2 and transistor PM3 is caused to increase, so that VOUT1+ or VOUT1- is by the low pull-up current got higher Increase, reversal rate is faster;If Ictrl1Reduce, Ictl1By transistor PM0 mirror image to transistor PM2 and transistor PM3, lead The leakage current for flowing through transistor PM2 and transistor PM3 is caused to reduce, so that VOUT1+ or VOUT1- is subtracted by the low pull-up current got higher Small, reversal rate is slower.When the speed of oscillating unit signal overturning just determines the output of clock generation module-voltage controlled oscillator Clock frequency.
The circuit structure of three cross-coupling complementation oscillating units is identical, and is in reversed cascade connection, and second level oscillation is single In member, input terminal VIN2+, VIN2- are respectively VOUT1-, VOUT1+ of first order oscillating unit;When VIN2+ becomes from low to high When change, VIN2- change from high to low, VOUT2+ becomes low from height, and VOUT2- becomes high from low;When VIN2+ changes from low to high, When VIN2- changes from high to low, VOUT2+ becomes low from height, and VOUT2- becomes high from low;If Ictrl2Increase, Ictl2Pass through crystalline substance Body pipe PM0 mirror image causes the leakage current for flowing through transistor PM2 and transistor PM3 to increase, makes to transistor PM2 and transistor PM3 It obtains VOUT2+ or VOUT2- to be increased by the low pull-up current got higher, reversal rate is faster;If Ictrl2Reduce, Ictl2Pass through crystal Pipe PM0 mirror image causes the leakage current for flowing through transistor PM2 and transistor PM3 to reduce to transistor PM2 and transistor PM3, so that VOUT2+ or VOUT2- is reduced by the low pull-up current got higher, and reversal rate is slower.
In third level oscillating unit, input terminal VIN3+, VIN3- are respectively VOUT2-, VOUT2 of second level oscillating unit +;If Ictrl3Increase, Ictl3By transistor PM0 mirror image to transistor PM2 and transistor PM3, cause to flow through transistor PM2 Increase with the leakage current of transistor PM3, so that VOUT3+ or VOUT3- is increased by the low pull-up current got higher, reversal rate is more Fastly;If Ictrl3Reduce, Ictl3By transistor PM0 mirror image to transistor PM2 and transistor PM3, cause to flow through transistor PM2 Reduce with the leakage current of transistor PM3, so that VOUT3+ or VOUT3- is reduced by the low pull-up current got higher, reversal rate is more Slowly.VOUT3+, VOUT3- are connected to VIN1-, VIN1+ again, continue through loop control reversal rate.Pass through three-level oscillating unit side To cascade structure, accurate control of the control electric current Ictrl to output clock frequency may be implemented, i.e., when control voltage is with output The positive correlation of clock frequency.
It is the circuit structure diagram of the configurable centre frequency adjustment module in the present invention referring to Fig. 5, Fig. 5;Every level-one is above-mentioned Cross-coupling oscillating unit output end all one, band configurable centre frequency adjustment modules;When configuration signal TR<1:0>is When 00 or 10, all switching tube M0, M1, M2, M3 are turned off in circuit, and centre frequency adjustment module does not work;When configuration signal When TR<1:0>is 01, switching tube M0, M1 are opened, and M2, M3 are closed, and mos capacitance M4 starts to act on M6, increase every grade of oscillation The load capacitance of unit, that is, increase time constant, reduces the centre frequency of PLL;When configuring signal TR<1:0>is 11, Switching tube M0, M1, M2, M3 are switched on, and mos capacitance M4, M5, M6, M7 start to act on, and increase the load electricity of every grade of oscillating unit Hold, further decreases the centre frequency of PLL.
High-speed, high precision phase-locked loop circuit for super large face array CMOS image sensor of the invention, including three-level are intersected The input voltage Vcrtl of voltage controlled oscillator made of coupled oscillator is unit cascaded, voltage controlled oscillator can be converted into Ictrl, Ictrl adjusts oscillating unit signal reversal rate by mirror current source, achievees the purpose that adjust output frequency;Control voltage After being converted into additional reverse current, oscillator operating frequency adjustable extent is substantially increased;Secondly controlled current source can have Effect inhibits the influence of power supply Earth noise to pass through appropriate adjustment NMOS differential pair and PMOS using three-level cross-coupling complementary structure Differential pair size is consistent oscillator signal rising edge with failing edge, to reduce influence of the output waveform to phase noise. In addition output voltage swing can also reduce phase noise close to supply voltage.
Further, it can configure centre frequency and adjust circuit, the clock generator for cmos image sensor needs Itself output clock frequency is adjusted according to the change of frame frequency, shaken so configurable center is added in phase-locked loop clock generation module It is necessary for swinging frequency adjustment circuit;Specific implementation is to every level-one cross coupled oscillator unit difference output end In addition the capacitor of adjustable size reaches to adjust the tipping load of every level-one oscillating unit and adjusts output clock frequency Purpose.
Phase-locked loop circuit in the present invention, low-pass filter use the capacitor and resistance of a configurable adjusting size, Purpose is according to different input clock and frequency dividing ratio, the i.e. different working frequency of voltage controlled oscillator, dynamic regulation phaselocked loop The bandwidth of circuit substantially increases the Stability and dependability of clock generator.
The above content is merely illustrative of the invention's technical idea, and this does not limit the scope of protection of the present invention, all to press According to technical idea proposed by the present invention, any changes made on the basis of the technical scheme each falls within claims of the present invention Protection scope within.

Claims (5)

1. a kind of high-speed, high precision phase-locked loop circuit for super large face array CMOS image sensor, which is characterized in that including multiple Position pipe NM5, transistor NM2, transistor NM3, transistor NM4, first order cross-coupling complementation oscillating unit, the second level intersect coupling Close complementary oscillating unit and third level cross-coupling complementation oscillating unit;
First order cross-coupling complementation oscillating unit, second level cross-coupling complementation oscillating unit and third level cross-coupling are complementary Oscillating unit successively reversely cascades;
The grid end of reset transistor NM5 meets PowerDown signal, the drain terminal of reset transistor NM5, the grid end of transistor NM2, transistor NM3 Grid end, the grid end of transistor NM4 be connected with Input voltage terminal, the source of transistor NM2, the source of transistor NM3, crystalline substance The source of body pipe NM4, the source of reset transistor NM5 are grounded, and the drain terminal of transistor NM2 exports Ictrl1, Ictrl1As frequency tune Current inputs first order cross-coupling complementation oscillating unit;
The drain terminal of transistor NM3 exports Ictrl2, Ictrl2Electric current input second level cross-coupling complementation oscillation is adjusted as frequency Unit;
The drain terminal of transistor NM4 exports Ictrl3, Ictrl3Electric current input third level cross-coupling complementation oscillation is adjusted as frequency Unit.
2. the high-speed, high precision phase-locked loop circuit according to claim 1 for super large face array CMOS image sensor, It is characterized in that, first order cross-coupling complementation oscillating unit includes transistor PM0, transistor PM2, transistor PM3, transistor PM4, transistor PM5, transistor NM0 and transistor NM1;
The drain terminal of transistor PM0 is mutually shorted with grid end, both inputs Ictrl1, the grid end of transistor PM0 also with transistor PM2 Grid end, transistor PM3 grid end be connected, the source of transistor PM0, the source of transistor PM2, the source of transistor PM3, crystalline substance The source of body pipe PM4, the source of transistor PM5 connect feeder ear, and the drain terminal of transistor PM3 is connected with the drain terminal of transistor PM5 It is followed by output end, the grid end of transistor PM4 is connected with the drain terminal of transistor NM1 is followed by output end, and output end is for exporting output Signal VOUT1+;
The drain terminal of transistor PM2 is connected with the drain terminal of transistor PM4 is followed by output end, the grid end and transistor NM0 of transistor PM5 Drain terminal be connected and be followed by output end, output end is used for output signal output VOUT1-;
The source of transistor NM0 and the source of transistor NM1 are grounded.
3. the high-speed, high precision phase-locked loop circuit according to claim 2 for super large face array CMOS image sensor, Be characterized in that, second level cross-coupling complementation oscillating unit, third level cross-coupling complementation oscillating unit circuit structure with The circuit structure of first order cross-coupling complementation oscillating unit is identical;
Wherein, output signal VOUT1-, VOUT1+ of first order cross-coupling complementation oscillating unit is intersected respectively as the second level Input signal VIN2+, VIN2- of coupling and complementing oscillating unit;
Output signal VOUT2-, VOUT2+ of second level cross-coupling complementation oscillating unit is mutual respectively as third level cross-coupling Mend input signal VIN3+, VIN3- of oscillating unit.
4. the high-speed, high precision phase-locked loop circuit according to claim 1 for super large face array CMOS image sensor, It is characterized in that, first order cross-coupling complementation oscillating unit, second level cross-coupling complementation oscillating unit and the third level intersect coupling The output end for closing complementary oscillating unit is equipped with the configurable centre frequency adjustment module for adjusting oscillating unit load capacitance.
5. the high-speed, high precision phase-locked loop circuit according to claim 4 for super large face array CMOS image sensor, It is characterized in that, the configurable centre frequency adjustment module includes switch M0, switch M1, switch M2, switch M3, PMOS capacitor M4, PMOS capacitor M5, NMOS capacitor M6 and NMOS capacitor M7, switch M0 and switch M3 are NMOS, switch M1 and switch M2 equal For PMOS;
The output end of the source of switch M0 and the source of switch M1 oscillating unit complementary with cross-coupling is connected, the grid of switch M0 The grid end of end and switch M1 are connected to configuration signal, the drain terminal of switch M0 and the drain terminal of switch M1 it is connected after respectively with PMOS capacitor The grid end of M4, the grid end of NMOS capacitor M6, the source of the source of switch M2 and switch M3 are connected, the grid end of switch M2, switch M3 Grid end be connected to configuration signal, the drain terminal of switch M2 connect with the drain terminal of switch M3 after respectively with the grid end of PMOS capacitor M5, The grid end of NMOS capacitor M7 is connected, and the source and drain terminal of PMOS capacitor M4 connects feeder ear, the source and drain terminal of PMOS capacitor M5 Connect feeder ear, source and the drain terminal ground connection of NMOS capacitor M6, source and the drain terminal ground connection of NMOS capacitor M7;
When configuring signal TR<1:0>is 00 or 10, switch M0, M1, M2, M3 are in off state;
When configuring signal TR<1:0>is 01, switch M0, M1 are in the open state, and switch M2, M3 are in close state;
When configuring signal TR<1:0>is 11, switch M0, M1, M2, M3 are in open state.
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US20170019021A1 (en) * 2015-07-17 2017-01-19 Analog Devices, Inc. Charge pump circuit with enhanced output impedance

Patent Citations (5)

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Publication number Priority date Publication date Assignee Title
CN101521498A (en) * 2008-02-29 2009-09-02 北京芯慧同用微电子技术有限责任公司 Voltage controlled oscillator
CN202617065U (en) * 2012-02-28 2012-12-19 无锡芯骋微电子有限公司 Low voltage voltage-controlled oscillator capable of restraining power supply noise
CN102843132A (en) * 2012-02-28 2012-12-26 无锡芯骋微电子有限公司 Low-voltage voltage-controlled oscillator capable of inhibiting power noise
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