CN109995681A - A kind of single-chip realizes the device and method of dual master control active-standby switch - Google Patents
A kind of single-chip realizes the device and method of dual master control active-standby switch Download PDFInfo
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- CN109995681A CN109995681A CN201910171099.4A CN201910171099A CN109995681A CN 109995681 A CN109995681 A CN 109995681A CN 201910171099 A CN201910171099 A CN 201910171099A CN 109995681 A CN109995681 A CN 109995681A
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- master control
- control board
- chip
- control borad
- cpu
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/06—Management of faults, events, alarms or notifications
- H04L41/0654—Management of faults, events, alarms or notifications using network fault recovery
- H04L41/0663—Performing the actions predefined by failover planning, e.g. switching to standby network elements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/55—Prevention, detection or correction of errors
- H04L49/552—Prevention, detection or correction of errors by ensuring the integrity of packets received through redundant connections
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Computer Security & Cryptography (AREA)
- Hardware Redundancy (AREA)
Abstract
Present invention discloses the device and methods that a kind of single-chip realizes dual master control active-standby switch, device includes: master control borad, slave control board, pcie interchanger and exchange chip, pcie interchanger is connected with master control borad or slave control board, pcie interchanger is connected with exchange chip, exchange chip is connected by the switching of pcie interchanger with master control borad or slave control board, and after switching on slave control board the state of CPU and CPU on the preceding master control borad of switching state consistency.The present invention can effectively reduce cost, while efficiently realize active-standby switch.
Description
Technical field
The present invention relates to a kind of dual master control implementations, realize dual master control active-standby switch more particularly, to a kind of single-chip
Device and method.
Background technique
Dual master control is a kind of universal redundancy backup mechanism for improving system stability and using, and is made extensively at present
With.In switch system, dual master control is divided to active and standby master control two kinds of roles, and master control and standby master control independently work, wherein main
Master control is responsible for being communicated (such as including the various list items in lower section, transmitting-receiving message and the various events of response) with total interface plate, with
And the operation of whole dual master control equipment of control.There was only master control work under normal circumstances, by the agreement on upper layer complete it is active and standby it
Between synchronization.When master control operates normally, standby master control will not intervene the fortune of whole dual master control equipment not with interface board communications
Row only receives master control and backs up the Backup Data to come.When main equipment breaks down, it can be switched to standby equipment at once, by
The Backup Data of master control is had received in standby master control, so all working of the former master control of energy seamless pipe, completes active-standby switch.
But the prior art when realizing dual master control needs that independent CPU and exchange are respectively configured in active and standby equipment
Chip at least needs 2 CPU and 2 exchange chips, and in the network switching equipment, exchange chip is core component, cost
It is higher, so needing to be reduced as far as production cost on the basis of realizing dual master control.
Summary of the invention
It is an object of the invention to overcome the deficiencies of existing technologies, a kind of single-chip is provided and realizes dual master control active-standby switch
Device and method.
To achieve the above object, the following technical solutions are proposed by the present invention: a kind of single-chip realizes dual master control active-standby switch
Device, comprising: master control borad, slave control board, pcie interchanger and exchange chip, the pcie interchanger and master control borad or spare
Master control borad is connected, and the pcie interchanger is connected with exchange chip, and the exchange chip is switched by pcie interchanger and master control
Plate or slave control board are connected.
Preferably, the master control borad and slave control board include a CPU, CPU on the slave control board after switching
State and the state consistency for switching CPU on preceding master control borad.
Preferably, the pcie interchanger is connected between master control borad or slave control board by pcie link.
Preferably, the CPU of the slave control board is connected by socket interface with the receiving end of master control borad, is read and main
Control the configuration on the connected exchange chip of plate.
Present invention further teaches another technical solutions: a kind of method that single-chip realizes dual master control active-standby switch, packet
It includes:
S1 realizes the state consistency of the state of CPU and CPU on master control borad before switching on slave control board after switching；
S2, after master control borad goes wrong, exchange chip is connected by the switching of pcie interchanger with slave control board, is completed
Active-standby switch.
Preferably, the S1 includes:
S11, master control borad, which issues, to be configured in exchange chip, and configuration is synchronized to slave control board；
S12, the slave control board receives configuration, by the configuration distributing；
S13, the slave control board send access instruction to master control borad, it is desirable that read the chip value of exchange chip；
S14, the master control borad receive the access instruction, and the chip value reading of exchange chip is returned to spare master control
Plate realizes the state consistency of the state of CPU and CPU on master control borad before switching on slave control board after switching.
Preferably, the master control borad and slave control board issue configuration and pass sequentially through protocol layer, adaptation layer, SDK software
To Shim layers of IO, and the master control borad eventually by pcie link by configuration distributing into exchange chip.
Preferably, in S13, access instruction is passed to master control borad by socket by the slave control board.
Preferably, in S14, after the master control borad receives access instruction, by pcie link by chip value from exchange chip
Middle reading.
Preferably, in S2, after master control borad goes wrong, pcie interchanger is by pcie link switching and slave control board phase
Even.
The beneficial effects of the present invention are:
1, the present invention controls the connectivity of master control borad and slave control board by pcie interchanger, realizes and only needs one
The masterslave switchover of dual master control can be realized in exchange chip, i.e., two CPU share a chips to realize in dual master control plate, passes through
Pcie link carries out the switching between active and standby, can effectively reduce cost, while efficiently realizing active-standby switch.
2, in software realization, before master control borad failure, slave control board transmits the visit of read operation by socket
Ask that instruction to master control borad, reads the data of exchange chip by master control borad and returns to slave control board, ensure that spare after switching
The state of CPU and the state consistency for switching CPU on preceding master control borad on master control borad, that is, realize that the configuration of active and standby control plate is fully synchronized.
Detailed description of the invention
Fig. 1 is the schematic illustration of apparatus of the present invention；
Fig. 2 is the schematic illustration of the active and standby synchronization of the present invention；
Fig. 3, Fig. 4 are the flow diagrams of the active and standby synchronization of the embodiment of the present invention.
Specific embodiment
Below in conjunction with attached drawing of the invention, clear, complete description is carried out to the technical solution of the embodiment of the present invention.
A kind of disclosed single-chip realizes the device and method of dual master control active-standby switch, utilizes an exchange core
Piece realizes the active-standby switch of dual master control, reduces the cost of dual master control realization.
As shown in Figure 1, a kind of revealed device of single-chip realization dual master control active-standby switch of the embodiment of the present invention, including
Master control borad, slave control board, pcie (high speed serialization computer expansion bus standard) interchanger and exchange chip, exchange chip are logical
The switching of pcie interchanger is crossed to be connected with master control borad or slave control board.
Specifically, master control borad and slave control board pass through pcie link (lane) and are connected with pcie interchanger.In master control
When plate works normally, the pcie link between master control borad and pcie interchanger is connected to, and slave control board is exchanged with pcie
Pcie link between machine is to disconnect, i.e., it is connection that synchronization, which only has a pcie link,.Pcie interchanger with exchange
Chip is connected, that is to say, that the present invention is connected by the switching of pcie interchanger with master control borad or slave control board, i.e., is handed over pcie
It changes planes to control the connectivity of pcie lane.Pcie link when master control borad work, between slave control board and exchange chip
It is to disconnect.When master control borad goes wrong, the pcie link of slave control board all the way is switched to by pcie interchanger.
Any variation does not occur for exchange chip itself in handoff procedure, therefore can guarantee in handoff procedure and be not in
Message loss of forwarded packets, it is only necessary to guarantee that the state of CPU and CPU state on master control borad before switching are consistent just on switching standby master control borad
It can be with.
It is consistent with CPU state on preceding master control borad is switched how to guarantee to switch the state of CPU on standby master control borad, in conjunction with Fig. 2
Shown in~Fig. 4.The configuration that the CPU of all master control borads is issued, all needs to be synchronized to the CPU of standby control plate, the CPU of standby control plate also under
The same configuration of hair.The difference is that the configuration that the CPU of master control borad is issued can be issued in exchange chip all the way, and standby control plate
CPU can not normally access the resource of exchange chip, just need at this time since the pcie link between exchange chip is to disconnect
It is realized by IO Shim (input and output bed course) layer, the CPU of standby control plate passes through socket to the read operation of exchange chip at this time
(socket) passes to the receiving end on master control borad, completes the read access to chip by master control borad and result is returned to standby master control
Plate, and the write operation of standby master control does not need to handle, and returns successfully.Detailed process is as shown in Figure 2 to 4:
A1, master control borad, which issues, to be configured in exchange chip.
Specifically, in the present embodiment, the CPU of master control borad issues configuration A, normally issues, passes sequentially through protocol layer, is adapted to
Layer, SDK (Software Development Kit, Software Development Kit) software are issued to Shim layers of IO, Shim layers of IO
By pcie link connection between exchange chip, when master control borad works normally, this between master control borad and exchange chip
Pcie link is connection (active), so the CPU of master control borad is successfully configured to exchange for A is configured eventually by pcie link
In chip.
Configuration is simultaneously synchronized to slave control board by A2, master control borad.
Specifically how configuration is synchronized to the slave control board present invention not repeating them here, can refer to the existing master for realizing dual master control
Synchronous principle is configured between standby control plate to realize.
A3, slave control board receives configuration, by configuration distributing.
With master control borad issue configuration principle it is similar, the configuration A received is passed sequentially through protocol layer by slave control board, adaptation
Layer, SDK software is issued to Shim layers of IO, although Shim layers of IO are connected between exchange chip and through pcie link,
But when master control borad works normally, the pcie link between slave control board and exchange chip is to disconnect (being inactive)
, so the configuration A on slave control board can not continue to issue after being issued to Shim layers of IO, need to carry out read operation to obtain
Chip value on exchange chip is specifically shown in below step A4.
A4, slave control board send access instruction to master control borad, it is desirable that read the chip value of exchange chip.
Specifically, slave control board needs to read the chip value on exchange chip, is realized by socket, slave control board
Shim layers of IO and Shim layers of IO of master control borad between pass through socket connection.Slave control board passes through access instruction first
Socket first passes to Shim layers of IO of master control borad, then passes sequentially through SDK software, and adaptation layer, protocol layer passes to the CPU of master control borad.
Here access instruction is the request instruction for reading the chip value of exchange chip.
A5, master control borad receive access instruction, and the chip value reading of exchange chip is returned to slave control board.
Specifically, after the CPU of master control borad receives access instruction, the pcie link that is worked between exchange chip by it
Chip value on exchange chip is read, and returns to the CPU of slave control board.It is spare after the CPU for returning to slave control board
The CPU of master control borad originally need to will configuration write-in, but completed since correct chip value at this time is handled on master control borad,
So slave control board does not need to write, the chip value of reading is directly directly returned to slave control board by master control borad can.
To realize the state consistency of the state of CPU and CPU on master control borad before switching on slave control board after switching
A6, after master control borad goes wrong, exchange chip is connected by the switching of pcie interchanger with slave control board, is completed
Active-standby switch.
How to switch, i.e., above-mentioned introduced, pcie link switching to slave control board is made spare master by pcie interchanger
Control plate between pcie interchanger and exchange chip by being connected.
In the network switching equipment, exchange chip is core component, higher cost.Two on dual master control card of the invention
CPU shares an exchange chip to realize, carries out the switching between active and standby by pcie link, i.e., only needs an exchange chip
The masterslave switchover for achieving that dual master control, can effectively reduce cost.
In addition, the exchange chip in the present invention is not limited to ASIC (Application Specific Integrated
Circuit, specific integrated circuit) chip further includes FPGA (Field-Programmable Gate Array, field-programmable
Gate array) or NP (network processing unit) etc..
Technology contents and technical characteristic of the invention have revealed that as above, however those skilled in the art still may base
Make various replacements and modification without departing substantially from spirit of that invention, therefore, the scope of the present invention in teachings of the present invention and announcement
It should be not limited to the revealed content of embodiment, and should include various without departing substantially from replacement and modification of the invention, and be this patent Shen
Please claim covered.
Claims (10)
1. the device that a kind of single-chip realizes dual master control active-standby switch characterized by comprising master control borad, slave control board,
Pcie interchanger and exchange chip, the pcie interchanger are connected with master control borad or slave control board, the pcie interchanger with
Exchange chip is connected, and the exchange chip is connected by the switching of pcie interchanger with master control borad or slave control board.
2. the device that a kind of single-chip according to claim 1 realizes dual master control active-standby switch, which is characterized in that the master
It controls plate and slave control board includes a CPU, after switching on the slave control board in the state of CPU and the preceding master control borad of switching
The state consistency of CPU.
3. the device that a kind of single-chip according to claim 1 realizes dual master control active-standby switch, which is characterized in that described
Pcie interchanger is connected between master control borad or slave control board by pcie link.
4. the device that a kind of single-chip according to claim 2 realizes dual master control active-standby switch, which is characterized in that described standby
It is connected by socket interface with the receiving end of master control borad with the CPU of master control borad, is read on the exchange chip being connected with master control borad
Configuration.
5. the side that a kind of single-chip based on 2~4 any one described device of the claims realizes dual master control active-standby switch
Method characterized by comprising
S1 realizes the state consistency of the state of CPU and CPU on master control borad before switching on slave control board after switching；
S2, after master control borad goes wrong, exchange chip is connected by the switching of pcie interchanger with slave control board, is completed active and standby
Switching.
6. the method that a kind of single-chip according to claim 5 realizes dual master control active-standby switch, which is characterized in that the S1
Include:
S11, master control borad, which issues, to be configured in exchange chip, and configuration is synchronized to slave control board；
S12, the slave control board receives configuration, by the configuration distributing；
S13, the slave control board send access instruction to master control borad, it is desirable that read the chip value of exchange chip；
S14, the master control borad receive the access instruction, and the chip value reading of exchange chip is returned to slave control board, real
After now switching on slave control board the state of CPU and before switching on master control borad CPU state consistency.
7. the method that a kind of single-chip according to claim 6 realizes dual master control active-standby switch, which is characterized in that the master
Control plate and slave control board issue configuration and pass sequentially through protocol layer, adaptation layer, SDK software to Shim layers of IO, and the master control
Plate eventually by pcie link by configuration distributing into exchange chip.
8. the method that a kind of single-chip according to claim 6 realizes dual master control active-standby switch, which is characterized in that in S13,
Access instruction is passed to master control borad by socket by the slave control board.
9. the method that a kind of single-chip according to claim 6 realizes dual master control active-standby switch, which is characterized in that in S14,
After the master control borad receives access instruction, chip value is read from exchange chip by pcie link.
10. the method that a kind of single-chip according to claim 5 realizes dual master control active-standby switch, which is characterized in that in S2,
After master control borad goes wrong, pcie link switching is connected by pcie interchanger with slave control board.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910171099.4A CN109995681B (en) | 2019-03-07 | 2019-03-07 | Device and method for realizing double-master-control main-standby switching by single chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910171099.4A CN109995681B (en) | 2019-03-07 | 2019-03-07 | Device and method for realizing double-master-control main-standby switching by single chip |
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Cited By (4)
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| CN110543390A (en) * | 2019-09-19 | 2019-12-06 | 深圳市友华通信技术有限公司 | Method and device for quickly responding to interrupt reconnection and communication equipment |
| CN112235192A (en) * | 2020-10-10 | 2021-01-15 | 盛科网络（苏州）有限公司 | Linkagg port switching method for stacking equipment and Linkagg-based stacking equipment |
| CN113407480A (en) * | 2021-06-25 | 2021-09-17 | 新华三信息安全技术有限公司 | Centralized management's frame switch |
| CN116582471A (en) * | 2023-07-14 | 2023-08-11 | 珠海星云智联科技有限公司 | PCIE equipment, PCIE data capturing system and server |
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| CN109995681B (en) | 2021-03-23 |
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