CN109981062A - With asymmetric enlarged structure and linear power amplification device - Google Patents
With asymmetric enlarged structure and linear power amplification device Download PDFInfo
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- CN109981062A CN109981062A CN201811523617.6A CN201811523617A CN109981062A CN 109981062 A CN109981062 A CN 109981062A CN 201811523617 A CN201811523617 A CN 201811523617A CN 109981062 A CN109981062 A CN 109981062A
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- 238000004519 manufacturing process Methods 0.000 description 4
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0261—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the polarisation voltage or current, e.g. gliding Class A
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3211—Modifications of amplifiers to reduce non-linear distortion in differential amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3223—Modifications of amplifiers to reduce non-linear distortion using feed-forward
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
- H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3036—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers
- H03G3/3042—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers in modulators, frequency-changers, transmitters or power amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Amplifiers (AREA)
Abstract
The disclosure provides a kind of with asymmetric enlarged structure and linear power amplification device.The power amplification device includes: the first biasing circuit, generates first bias current with first amplitude；First amplifying circuit, is connected between first node and second node, and receives first bias current, amplifies the signal inputted by the first node, and the first amplified signal is output to the second node；Second biasing circuit, generates second bias current with the second amplitude, and second amplitude is different from the first amplitude of first bias current；And second amplifying circuit, it is connected in parallel between the first node and the second node with first amplifying circuit, and receive second bias current, amplify the signal inputted by the first node, and the second amplified signal is output to the second node, wherein, second amplifying circuit can have the size different from the size of first amplifying circuit.
Description
This application claims be submitted to Korea Spro 10-2017-0181053 of Korean Intellectual Property Office on December 27th, 2017
The equity of the priority of state's patent application, the complete disclosure of the South Korea patent application pass through reference quilt for all purposes
It is incorporated herein.
Technical field
Linear power amplification device is kept using asymmetric enlarged structure this application involves a kind of.
Background technique
As the demand to broadband, multimedia and intelligentized ability in wireless communication system gradually increases, to application
The demand of broadband ability, linear improvement in radio frequency (RF) power amplifier of wireless communication system and intelligent ability
Increase.
It is beneficial due to operating RF power amplifier in higher-wattage region middle line, it is ensured that for packet
Include the linear and undistorted of the broadband signal of multiple frequency bands.
However, in typical RF power amplifier, when the interval between the fundamental frequency signal of two or more different bands is narrow
When, since fundamental frequency signal is adjacent with third order intermodulation distortion (hereinafter referred to as IM3) component, so between IM3 component and fundamental frequency signal
Difference (hereinafter referred to as IMD3) and linearly may reduce.
Summary of the invention
There is provided the content of present invention is to introduce will further retouch in the following detailed description in simplified form
The selected design stated.The content of present invention is not intended to determine the key features or essential features of theme claimed,
It is not intended to be used as the range for assisting in theme claimed.
In a general aspect, a kind of power amplification device includes: the first biasing circuit, and being configured as generating has first
First bias current of amplitude；First amplifying circuit, is connected between first node and second node, and is configured as: connecing
First bias current is received, amplifies the signal inputted by the first node, and the first amplified signal is output to institute
State second node；Second biasing circuit, be configured as generate have the second amplitude the second bias current, second amplitude with
The first amplitude of first bias current is different；And second amplifying circuit, it is in parallel with first amplifying circuit to connect
It connects between the first node and the second node, and is configured as: receiving second bias current, amplification passes through
The signal of the first node input, and the second amplified signal is output to the second node, wherein described second
Amplifying circuit can have the current gain different from the current gain of first amplifying circuit.
Second amplified signal can have third-harmonic component, and there is the third-harmonic component counteracting described first to put
The phase of third order intermodulation distortion (IM3) component in big signal.
Second amplitude of second bias current is smaller than the first amplitude of first bias current.
The quantity of transistor in second amplifying circuit can be greater than the number of the transistor in first amplifying circuit
Amount.
The current gain of second amplifying circuit can be greater than the current gain of first amplifying circuit.
Second amplitude of second bias current can be greater than the first amplitude of first bias current.
The quantity of transistor in second amplifying circuit is smaller than the number of the transistor in first amplifying circuit
Amount.
The current gain of second amplifying circuit is smaller than the current gain of first amplifying circuit.
First bias current can be the bias current of AB class, and second bias current can be AB class and
The bias current of deep AB class between B class.
Second biasing circuit can be configured to for second bias current to be produced as to have and include in input
The corresponding amplitude of the amplitude of fundamental frequency in the signal.
In a general aspect, a kind of power amplification device includes: driving biasing circuit, is configurable to generate driving biasing
Electric current；Drive amplification circuit, is connected between input terminal and first node, and is configured as: receiving the driving biasing
Electric current amplifies the input signal with first frequency component and second frequency component, and the first amplified signal is output to institute
State first node；First biasing circuit is configured as generating first bias current with first amplitude；First amplifying circuit,
It is connected between the first node and second node, and is configured as: receiving first bias current, amplification passes through institute
First amplified signal of first node input is stated, and the second amplified signal is output to the second node；Second partially
Circuits are configured as: generating second bias current with the second amplitude, second amplitude and first bias current
The first amplitude it is different；And second amplifying circuit, the first node is connected in parallel with first amplifying circuit
It between the second node, and is configured as: receiving second bias current, amplification is inputted by the first node
First amplified signal, and third amplified signal is output to the second node, wherein second amplifying circuit
It is configured with the current gain different from the current gain of first amplifying circuit.
The third amplified signal can have third-harmonic component, and there is the third-harmonic component counteracting described second to put
The phase of third order intermodulation distortion (IM3) component in big signal.
Second amplitude of second bias current is smaller than the first amplitude of first bias current.
The current gain of second amplifying circuit can be greater than the current gain of first amplifying circuit.
Second amplitude of second bias current can be greater than the first amplitude of first bias current.
The current gain of second amplifying circuit is smaller than the current gain of first amplifying circuit.
First bias current can be the bias current of AB class, and second bias current can be AB class and
The bias current of deep AB class between B class.
Second biasing circuit can be configured to for second bias current to be produced as to have and include described defeated
Enter the corresponding amplitude of amplitude of the fundamental frequency in signal.
In a general aspect, a kind of power amplification device includes: the first amplifier with the first current gain, and
It is configured as the input signal based on the first bias current received and including one or more frequency components and generates
First amplified signal；And the second amplifier with second current gain bigger than first current gain, with described the
The connection of one amplifier in parallel, and be configured as generating second based on the input signal and the second bias current received
Amplified signal, wherein second amplified signal can have third-harmonic component, and the third-harmonic component has described in counteracting
The phase of third order intermodulation distortion (IM3) component in the first amplified signal.
The quantity of the transistor of second amplifier can be greater than the quantity of the transistor of first amplifier.
By following specific embodiment, drawings and claims, other feature and aspect be will be apparent.
Detailed description of the invention
Fig. 1 is the exemplary diagram for showing the configuration of power amplification device；
Fig. 2 is the exemplary diagram for showing the configuration of power amplification device；
Fig. 3 is the exemplary diagram for showing the implementation of power amplification circuit；
Fig. 4 is the exemplary diagram for showing the implementation of biasing circuit；
Fig. 5 A and Fig. 5 B are the exemplary diagrams for describing the input capacitance generated due to the mirror capacity effect of amplifying circuit；
And
Fig. 6 shows the example according to whether the performance diagram using the IMD3-Pout of variable bias.
Throughout the drawings and the detailed description, identical appended drawing reference indicates identical element.Attached drawing can not be according to
Ratio is drawn, and for the sake of clear, explanation and convenience, can exaggerate the relative size, ratio and description of the element in attached drawing.Attached
In figure, such as due to manufacturing technology and/or tolerance, the change of shown shape can be estimated.Therefore, example described herein is not
It should be construed as limited to the specific shape in the region being shown here, for example, example described herein includes as caused by manufacture
The change of shape.
Specific embodiment
Following specific embodiment is provided to help reader to obtain to method described herein, equipment and/or system
Comprehensive understanding.However, after understanding disclosure of this application, method described herein, the various of equipment and/or system change
Become, modification and equivalent will be apparent.For example, the sequence of operation described herein is only example, and it is not limited to
Here the sequence illustrated, but other than the operation in addition to that must occur in a specific order, it can be to the sequence of operation described herein
Making will be apparent upon changing understanding disclosure of this application.In addition, can be saved in order to more clear and succinct
The description of feature slightly known in the art.
Feature described herein can be implemented in different forms, and will not be construed as limited to described herein show
Example.More precisely, example described herein is provided, it will after understanding disclosure of this application just to show
It is some feasible patterns in many feasible patterns for obviously realize method described herein, equipment and/or system.
Throughout the specification, when such as element of layer, region or substrate is described as " " another element "upper", " company
It is connected to " another element or when " being integrated to " another element, which can directly " " described another element "upper", directly " connection
To " another element or direct " being integrated to " described another element, or between them one or more may be present
A other elements.In contrast, when element be described as " directly existing " another element "upper", " being directly connected to " another element or
When " being bonded directly to " another element, other elements between them may not be present.
As used herein, term "and/or" include in related institute's list any one and any two or more
Any combination.
Although herein can be used such as " first ", " second ", " third " term come describe various components, component, region,
Layer or part, but these components, component, region, layer or part will should not be limited by these terms.More precisely, these
Term is only used to distinguish a component, component, region, layer or part and another component, component, region, layer or part.Cause
This, is in the case where not departing from exemplary introduction, the first component, the first assembly, the firstth area that are referred in example described herein
Domain, first layer or first part are also referred to as second component, the second component, second area, the second layer or second part.
For ease of description, herein can be used such as " ... on ", " above ", " ... under ", " below "
Spatially relative term describes the relationship of an element and another element as shown in figures.Such spatially relative term meaning
It also include the different direction of device in use or operation other than the orientation in addition to describing in comprising attached drawing.For example, if attached
Device in figure is reversed, then is described as then being positioned in the element of another element " on " or " above " described another
One element " under " or " following ".Therefore, term " ... on " according to the dimensional orientation of device include " ... on "
" ... under " two kinds of orientation.Device can also be positioned in other ways (for example, being rotated by 90 ° or in other sides
Position), and spatially relative term used herein will be interpreted accordingly.
Term as used herein is merely to describe various examples, and will be not used in the limitation disclosure.Unless context
In addition it is expressly noted that, otherwise singular is also intended to include plural form.Term "comprising", " comprising " and " having " enumerate presence
Feature, quantity, operation, component, element and/or the their combination stated, but do not preclude the presence or addition of one or more
A other feature, quantity, operation, component, element and/or their combination.
Due to manufacturing technology and/or tolerance, it may occur however that the variation of shape shown in the drawings.Therefore, described herein
Example is not limited to concrete shape shown in the accompanying drawings, but the change of the shape including occurring during manufacture.
Fig. 1 is the exemplary diagram for showing the configuration of power amplification device.
It referring to Fig.1, may include that the first biasing circuit 210, the first amplifying circuit (or are put according to exemplary power amplification device
Big device) the 110, second biasing circuit 220 and the second amplifying circuit (or amplifier) 120.
Fig. 2 is another exemplary diagram for showing the configuration of power amplification device.Referring to Fig. 2, power amplification device can be wrapped
Include driving biasing circuit 205, drive amplification circuit 105, the first biasing circuit 210, the first amplifying circuit 110, the second biased electrical
Road 220 and the second amplifying circuit 120.
Referring to Fig. 2, driving biasing circuit 205 can produce driving bias current Ibias.
Drive amplification circuit 105, which can be supplied driving bias current Ibias and amplify, has first frequency component f1 and the
The input signal Si n of the twotone of two frequency component f2, and export amplified signal S105.As an example, in addition to the of amplification
Other than the one frequency component f1 and second frequency component f2 of amplification, amplified signal S105 may also include IM3 component (2f1-f2,
2f2-f1)。
As an example, first frequency component f1 and second frequency component f2 can be long term evolution (LTE) B1 high channel
(fc:1979.5MHz) dual tone signal, and in this case, pitch interval can be 1MHz.
Referring to Figures 1 and 2, the first biasing circuit 210 can produce the first bias current Ibias1.
First amplifying circuit 110 can be supplied the first bias current Ibias1 and amplify by first node N1 (or input
Terminal IN, Fig. 1) input signal, and the first amplified signal S110 is output to second node N2, wherein first node N1
It is the output node of drive amplification circuit 105.As an example, the first amplified signal S110 may include the first frequency component of amplification
F1, amplification second frequency component f2 and IM3 component (2f1-f2,2f2-f1).
Second biasing circuit 220 can produce the second bias current Ibias2, and the second bias current Ibias2 has and first
The different amplitude of the amplitude of bias current Ibias1.As an example, the second bias current Ibias2 can have than the first biased electrical
Flow the small amplitude of the amplitude of Ibias1.As another example, the second bias current Ibias2 can have than the first bias current
The big amplitude of the amplitude of Ibias1.
For example, the first bias current Ibias1 can be the bias current of AB class, and the second bias current Ibias2 can
To be the bias current of deep AB class between AB class and B class.
Second amplifying circuit 120 can be connected in parallel with the first amplifying circuit 110, and the second bias current can be supplied
Ibias2.Second amplifying circuit 120 can amplify the signal inputted by first node N1 (or input terminal IN, Fig. 1), and will
Second amplified signal S120 is output to second node N2.As an example, in order to accurately eliminate IM3 component, the second amplifying circuit
120 can have the size different from the size of the first amplifying circuit 110.In this example, size can be 110 He of amplifying circuit
120 physical size.As another example, the second amplifying circuit 120 can have with the current gain of the first amplifying circuit 110 not
Same current gain.For example, the amplitude of the bias current of the second amplifying circuit 120 can be greater than the inclined of the first amplifying circuit 110
The amplitude of electric current is set, and the gain (for example, current gain) of the second amplifying circuit 120 can be less than the first amplifying circuit 110
Gain (for example, current gain).Furthermore the amplitude of the bias current of the second amplifying circuit 120 can be less than the first amplification electricity
The amplitude of the bias current on road 110, the gain (for example, current gain) of the second amplifying circuit 120 can be greater than the first amplification electricity
The gain (for example, current gain) on road 110.
As an example, the second amplified signal S120 may include the first frequency component f1 of amplification and the second frequency point of amplification
F2 is measured, and may also include the IM3 component (2f1-f2,2f2-f1) of phase offset.
In addition, the second amplifying circuit 120 can be exported based on the second bias current Ibias2 has the of third-harmonic component
Two amplified signal S120, the third-harmonic component have can offset or eliminate including the IM3 in the first amplified signal S110
The phase of component.As an example, can offset or eliminate the offset phase of IM3 component or phase can be between 150 ° and 180 °
Phase, and can be substantially 180 ° of eradicating efficacies to increase IM3 component.
In addition, the second amplifying circuit 120 can be realized with the size different from the size of the first amplifying circuit 110, and
Exportable second amplified signal S120, the second amplified signal S120 have and include IM3 in the first amplified signal S110 points
The third-harmonic component of the identical amplitude of the amplitude of amount.
Correspondingly, at second node N2, due to the frequency of first frequency component f1 and second from the first amplifying circuit 110
Rate component f2 has identical with the phase of first frequency component f1 and second frequency component f2 from the second amplifying circuit 120
Phase, thus the first frequency component f1 from the first amplifying circuit 110 and second frequency component f2 and from second amplification
The first frequency component f1 of circuit 120 is added each other with second frequency component f2, so that the amplitude of first frequency component f1 and
The amplitude of two frequency component f2 can further increase.For example, in fig. 1 and 2, the defeated of increase can be exported in output terminal OUT
Signal Sout out.
On the other hand, at second node N2, IM3 component (2f1-f2,2f2-f1) phase from the first amplifying circuit 110
There is about 180 ° of offset phase for the IM3 component (2f1-f2,2f2-f1) from the second amplifying circuit 120, and come
Amplitude from the IM3 component (2f1-f2,2f2-f1) of the first amplifying circuit 110 and the IM3 component from the second amplifying circuit 120
The amplitude of (2f1-f2,2f2-f1) is substantially identical to each other so that from the first amplifying circuit 110 IM3 component (2f1-f2,
2f2-f1) cancel each other out with the IM3 component (2f1-f2,2f2-f1) from the second amplifying circuit 120.As a result, in second node
At N2, the amplitude of IM3 component (2f1-f2,2f2-f1) is significantly reduced or IM3 component can almost be eliminated.
As described above, when the first amplifying circuit 110 and the second amplifying circuit 120 that are driven with different bias levels have spy
When biasing difference in magnitude surely, the IM3 component generated at corresponding output can have 180 ° of phase difference, and due to the first amplification electricity
Road 110 and the second amplifying circuit 120 can be realized in different sizes, and the amplitude for exporting IM3 component can be mutually the same, because
This IM3 component can almost be eliminated.
According to example, when the respective IM3 component generated from the first amplifying circuit 110 and the second amplifying circuit 120 substantially
, it can be achieved that maximum eradicating efficacy when with mutually the same amplitude and with 180 ° of phase difference.
In this example, by the such design of description: in each self-bias of the first amplifying circuit 110 and the second amplifying circuit 120
In the case that the amplitude set is different from each other, from the first amplifying circuit 110 export IM3 component and from the second amplifying circuit 120 it is defeated
The phase of IM3 component out shifts.The reason is that: in each amplifying circuit, three ranks of transistor associated with IM3 across
Negative value or positive value can be had according to bias level by leading gm ".For example, three rank mutual conductances can when the transistor biasing of amplifying circuit
There is positive value+gm in the case where transistor is in weak inversion regime domain ", and three rank mutual conductances can be in strong inversion in transistor
There is negative value-gm " in the case where in region.On the other hand, regardless of displacement zone, single order associated with fundamental frequency signal across
Positive value can always be had by leading.
As described above, the first amplification electricity by biasing to make 180 ° of phase difference of IM3 component with different amplitudes
Road 110 and the second amplifying circuit 120 can have as described above based on the first amplifying circuit 110 and the second amplifying circuit 120
The current amplitude for the IM3 component that relative size determines.The relative size of first amplifying circuit 110 and the second amplifying circuit 120 can
It can be important for obtaining more effective IM3 eradicating efficacy.
In each example, the first amplifying circuit 110 and the second amplifying circuit 120 can be asymmetricly connected in parallel each other,
And it may be biased to varying level, to can get most effective IM3 eradicating efficacy.In addition, the second amplifying circuit 120 can have
The size different from the size of the first amplifying circuit 110.As an example, the size of the first amplifying circuit 110 or the second amplification electricity
The size on road 120 can be corresponding with the quantity for the transistor being connected in parallel with each other, but not limited to this.For example, the second amplifying circuit
The quantity of 120 transistors for including can be greater than the quantity for the transistor that the first amplifying circuit 110 includes, the second amplifying circuit
120 size can be greater than the size of the first amplifying circuit 110.As another example, the second amplifying circuit 120 can have and the
The different current gain of the current gain of one amplifying circuit 110.As an example, the gain of the first amplifying circuit 110 or second putting
The gain of big circuit 120 can be determined by the quantity for the transistor being connected in parallel with each other, but not limited to this.
In each attached drawing of the disclosure, it is convenient to omit not for the component with same reference numerals and identical function
Necessary repeated description, and the difference in each attached drawing will be described.
Fig. 3 is the exemplary diagram for showing the implementation of power amplification device.
Referring to Fig. 3, drive amplification circuit 105 may include with the multiple of the base stage that driving bias current Ibias is supplied
Drive transistor QD.First amplifying circuit 110 may include multiple the with the base stage that the first bias current Ibias1 is supplied
One amplifying transistor Q1.Second amplifying circuit 120 may include with the multiple of the base stage that the second bias current Ibias2 is supplied
Second amplifying transistor Q2.
In addition, power amplification circuit may include input matching circuit (IMC) 115, intervalve matching circuit (MMC) 125 and defeated
Match circuit (OMC) 135 out.
Input matching circuit IMC 115 may include inductor and capacitor.
Intervalve matching circuit MMC 125 may include wire type inductor.
Output matching circuit OMC 135 may include the two of inductor, capacitor and the Opposite direction connection for discharge prevention
Pole pipe circuit.
As an example, block capacitor is attached between foregoing circuit.
As an example, each of driving transistor QD, the first amplifying transistor Q1 and second amplifying transistor Q2 can be with
It is heterojunction bipolar transistor (HBT), but not limited to this.
Fig. 4 is the exemplary diagram for showing biasing circuit.
Referring to Fig. 4, as an example, driving biasing circuit 205 may include between driving reference current Iref terminal and ground
The transistor Q11 and Q12 and resistor R12 of the resistor R11, the diode connection being connected to each other that are serially connected.It drives
Dynamic biasing circuit 205 may include output transistor Q13, and output transistor Q13 has the collection for being connected to cell voltage Vbat terminal
Electrode, be connected to resistor R11 and diode connection transistor Q11 connecting node base stage and by resistor R13
It is connected to the output the emitter of son.Driving biasing circuit 205 may also include the capacitor for being connected to the base stage of output transistor Q13
Device C11.Driving biasing circuit 205 shown in Fig. 4 is only shown as example, and without being limited thereto.
As an example, the first biasing circuit 210 may include being one another in series between the first reference current Iref1 terminal and ground
The transistor Q21 and Q22 and resistor R22 of the resistor R21 of connection, the diode connection being connected to each other.First biased electrical
Road 210 may include output transistor Q23, and output transistor Q23 has the collector for being connected to cell voltage Vbat terminal, connection
Output is connected to the base stage of the connecting node of resistor R21 and the transistor Q21 of diode connection and by resistor R23
The emitter of terminal.First biasing circuit 210 may also include the capacitor C21 for the base stage for being connected to output transistor Q23.Fig. 4
Shown in the first biasing circuit 210 be only shown as example, and it is without being limited thereto.
As an example, the second biasing circuit 220 may include being one another in series between the second reference current Iref2 terminal and ground
The transistor Q31 and Q32 and resistor R32 of the resistor R31 of connection, the diode connection being connected to each other.Second biased electrical
Road 220 may include output transistor Q33, and output transistor Q33 has the collector for being connected to cell voltage Vbat terminal, connection
Output is connected to the base stage of the connecting node of resistor R31 and the transistor Q31 of diode connection and by resistor R33
The emitter of terminal.Second biasing circuit 220 may also include the capacitor C31 for the base stage for being connected to output transistor Q33.Fig. 4
Shown in the second biasing circuit 220 be only shown as example, and it is without being limited thereto.
As an example, in the value of the resistor R23 of the first biasing circuit 210 and the resistor R33 of the second biasing circuit 220
Value be set to it is different from each other in the case where, the width of the amplitude of the first bias current Ibias1 and the second bias current Ibias2
Value can be set.It is that mode different from each other is not limited to above-mentioned example by the first bias current and the second bias current sets.
Fig. 5 A and Fig. 5 B are the exemplary diagrams for describing the input capacitance generated due to the mirror capacity effect of amplifying circuit.
Referring to Fig. 5 A, amplifying circuit may include base stage-collection between input terminal (base stage) and output terminal (collector)
Electrode capacitance Cbc.
It can pass through referring to Fig. 5 B, the input capacitance Cin due to Miller capacitance effect present in the base stage of input node
It is indicated underneath with the formula 1 of base-collector capacitance Cbc.
Formula 1
Cin=Cbe+ (1- (- Av)) * Cbc
Formula 1 indicates that the input capacitance of amplifying circuit can be promoted by voltage gain (- Av).In addition, the width of input capacitance
Value can the voltage gain (- Av) based on see-saw circuit and change.Correspondingly, in the first amplification with mutually the same size
Circuit 110 and the second amplifying circuit 120 are biased in the example of varying level, since the biasing of relatively small amplitude is supplied
Second amplifying circuit 120 of electric current can have the mutual conductance gm smaller than the mutual conductance gm of the first amplifying circuit 110 and therefore have small
Voltage gain, therefore even if the first amplifying circuit 110 and the second amplifying circuit 120 have mutually the same size, the second amplification
Circuit can also have low input capacitance.
In terms of impedance, if being divided into the first amplifying circuit 110 and with mutually the same size in amplifying circuit
In the state of two amplifying circuits 120, the second amplifying circuit 120 is biased to the bias current of low amplitude value, then the second amplifying circuit
120 can have the input impedance bigger than the input impedance of the first amplifying circuit 110.
In this example, the electric current of signal can concentrate on the first amplifying circuit 110 as the path with low input impedance
On, and the amplitude of fundamental frequency signal and the amplitude of IM3 component that export from the second amplifying circuit 120 are smaller than the first amplifying circuit
The amplitude of 110 fundamental frequency signal and the amplitude of IM3 component.
As a result, even if the IM3 component of the first amplifying circuit and the second amplifying circuit with mutually the same size has essence
180 ° true of phase difference, also due to may be difficult to achieve maximum IM3 there are the difference of the amplitude of IM3 component eliminates effect
Fruit.
In order to compensate for above-mentioned phenomenon, if the size phase of the second amplifying circuit 120 of the biasing with small magnitude is supplied
To the size for being greater than the first amplifying circuit 110, then the base-collector junction junction capacity of the second amplifying circuit 120 can further increase.
Correspondingly, input impedance can reduce and amplifying circuit can be driven with high current, to can realize that more effective IM3 disappears
It removes.
In addition, in the transistor with low bias level, voltage gain (Av) can be it is small, but if transistor
Size increase, then parasitic capacitance Cbe and Cbc can increase and input capacitance Cin can increase so that input impedance can reduce and
The electric current of input signal can increase.Input current increase example in, IM3 electric current can according to non-linear formula and and input current
The cube of amplitude proportionally increase.As a result, if using asymmetric enlarged structure, from two 110 Hes of amplifying circuit
120 output IM3 amplitude can be compensated for as it is generally mutually the same, so as to improve the eradicating efficacy of IM3 and can improve
Linearly.
Fig. 6 is the performance diagram according to whether the IMD3-Pout using variable bias.
P1 and P2 be LTE B3 frequency band (@1710MHz into 1785MHz) IMD3 emulation result curve figure, wherein
P1 is for using (210:1500 μm of first amplifying circuit with mutually the same size2) and the second amplifying circuit (220:
1500μm2) exemplary IMD3-Pout performance diagram, and P2 be for using have asymmetric size first amplification
(210:1500 μm of circuit2) and (220:2100 μm of the second amplifying circuit2) the case where IMD3-Pout performance diagram.
Referring to the P1 and P2 of Fig. 6, under the target power (Pout) of 25dBm, P1 is -32dBc, and in this example, P2
It is -34dBc, thus in the presence of the substantially improvement of 2dB.
As explained above, according to example, in the device using the dual tone signal for including two different frequency components
Amplifying circuit in parallel in, can by realize include the amplifying circuit in parallel of asymmetric enlarged structure structure, while making to bias
The amplitude of electric current is different from each other, further to improve IMD3 and linear.
That is, the amplitude of each Self-bias Current of amplifying circuit in parallel can be implemented as different from each other, and in parallel
The respective size of amplifying circuit can be implemented as different from each other, and the IM3 electric current exported from amplifying circuit in parallel can have 180 °
Phase difference and there can be mutually the same amplitude, to more effectively realize IM3 eradicating efficacy.
Although the present disclosure includes specific examples, be evident that after understanding disclosure of this application,
In the case where not departing from claim and its spirit and scope of equivalent, it can make in these examples in form and in details
Various changes.Example described herein is considered merely as descriptive meaning, rather than for purposes of limitation.Each show
The description of features or aspect in example will be considered as the similar features or aspects being applicable in other examples.If with difference
Sequence execute the technology of description, and/or if combined in the system of description, framework, device or circuit in different ways
Component and/or with the group in other components or the system of their equivalent replace or supplement description, framework, device or circuit
Part can then obtain suitable result.Therefore, the scope of the present disclosure is not limited by specific embodiment, but by claim
And its equivalent limits, and all changes in the range of claim and its equivalent are to be interpreted as being included in this
In open.
Claims (20)
1. a kind of power amplification device, comprising:
First biasing circuit is configured as generating first bias current with first amplitude；
First amplifying circuit, is connected between first node and second node, and is configured as: receiving first biased electrical
Stream amplifies the signal inputted by the first node, and the first amplified signal is output to the second node；
Second biasing circuit is configured as generating second bias current with the second amplitude, second amplitude and described the
The first amplitude of one bias current is different；And
Second amplifying circuit is connected in parallel between the first node and the second node with first amplifying circuit,
And it is configured as: receives second bias current, amplify the signal inputted by the first node, and by the
Two amplified signals are output to the second node,
Wherein, second amplifying circuit is configured with the electric current different from the current gain of first amplifying circuit and increases
Benefit.
2. power amplification device according to claim 1, wherein second amplified signal has third-harmonic component,
The third-harmonic component has the phase for offsetting the third order intermodulation distortion component in first amplified signal.
3. power amplification device according to claim 1, wherein second amplitude of second bias current is less than
The first amplitude of first bias current.
4. power amplification device according to claim 3, wherein the quantity of the transistor in second amplifying circuit is big
The quantity of transistor in first amplifying circuit.
5. power amplification device according to claim 4, wherein the current gain of second amplifying circuit is greater than
The current gain of first amplifying circuit.
6. power amplification device according to claim 1, wherein second amplitude of second bias current is greater than
The first amplitude of first bias current.
7. power amplification device according to claim 6, wherein the quantity of the transistor in second amplifying circuit is small
The quantity of transistor in first amplifying circuit.
8. power amplification device according to claim 7, wherein the current gain of second amplifying circuit is less than
The current gain of first amplifying circuit.
9. power amplification device according to claim 1, wherein first bias current is the bias current of AB class,
And
Second bias current is the bias current of the deep AB class between AB class and B class.
10. power amplification device according to claim 1, wherein second biasing circuit is configured as described
Two bias currents be produced as with include the corresponding amplitude of the amplitude of fundamental frequency in the signal of input.
11. a kind of power amplification device, comprising:
Driving biasing circuit is configurable to generate driving bias current；
Drive amplification circuit, is connected between input terminal and first node, and is configured as: receiving the driving biased electrical
Stream amplifies the input signal with first frequency component and second frequency component, and the first amplified signal is output to described
First node；
First biasing circuit is configured as generating first bias current with first amplitude；
First amplifying circuit is connected between the first node and second node, and is configured as: receiving described first partially
Electric current is set, amplifies first amplified signal inputted by the first node, and the second amplified signal is output to institute
State second node；
Second biasing circuit, is configured as: generating second bias current with the second amplitude, second amplitude and described the
The first amplitude of one bias current is different；And
Second amplifying circuit is connected in parallel between the first node and the second node with first amplifying circuit,
And it is configured as: receives second bias current, amplifies first amplified signal inputted by the first node,
And third amplified signal is output to the second node,
Wherein, second amplifying circuit is configured with the electric current different from the current gain of first amplifying circuit and increases
Benefit.
12. power amplification device according to claim 11, wherein the third amplified signal is with triple-frequency harmonics point
Amount, the third-harmonic component have the phase for offsetting the third order intermodulation distortion component in second amplified signal.
13. power amplification device according to claim 11, wherein second amplitude of second bias current is small
In the first amplitude of first bias current.
14. power amplification device according to claim 13, wherein the current gain of second amplifying circuit is big
In the current gain of first amplifying circuit.
15. power amplification device according to claim 11, wherein second amplitude of second bias current is big
In the first amplitude of first bias current.
16. power amplification device according to claim 15, wherein the current gain of second amplifying circuit is small
In the current gain of first amplifying circuit.
17. power amplification device according to claim 11, wherein first bias current is the biased electrical of AB class
Stream, and
Second bias current is the bias current of the deep AB class between AB class and B class.
18. power amplification device according to claim 11, wherein second biasing circuit is configured as described
Two bias currents be produced as with include the corresponding amplitude of the amplitude of fundamental frequency in the input signal.
19. a kind of power amplification device, comprising:
First amplifier is configured with the first current gain, and is configured as: having first amplitude based on what is received
The first bias current and input signal including one or more frequency components, generate the first amplified signal；And
Second amplifier is configured with second current gain bigger than first current gain, with first amplification
Device is connected in parallel, and is configured as: based on the input signal and receive have it is different from the first amplitude
Second bias current of the second amplitude generates the second amplified signal,
Wherein, second amplified signal has third-harmonic component, and there is the third-harmonic component counteracting described first to put
The phase of third order intermodulation distortion component in big signal.
20. power amplification device according to claim 19, wherein by the number for the transistor that second amplifier is implemented
Amount is greater than the quantity for the transistor implemented by first amplifier.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020170181053A KR102491944B1 (en) | 2017-12-27 | 2017-12-27 | Power amplifier with asymmetric amplification structure for improving linearity |
| KR10-2017-0181053 | 2017-12-27 |
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| Publication Number | Publication Date |
|---|---|
| CN109981062A true CN109981062A (en) | 2019-07-05 |
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| CN201811523617.6A Active CN109981062B (en) | 2017-12-27 | 2018-12-13 | Power amplifying device with asymmetric amplifying structure and linearity |
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|---|---|
| US (1) | US10707820B2 (en) |
| KR (1) | KR102491944B1 (en) |
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| KR20220072030A (en) | 2020-11-23 | 2022-06-02 | 삼성전자주식회사 | Amplifier |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6791418B2 (en) * | 2002-10-02 | 2004-09-14 | Koninklijke Philips Electronics N.V. | Capacitor coupled dynamic bias boosting circuit for a power amplifier |
| US6937094B2 (en) * | 2002-11-22 | 2005-08-30 | Powerwave Technologies, Inc. | Systems and methods of dynamic bias switching for radio frequency power amplifiers |
| CN1993883A (en) * | 2004-05-18 | 2007-07-04 | 皇家飞利浦电子股份有限公司 | Amplifier circuit with automatic gain correction |
| KR101002893B1 (en) * | 2005-08-06 | 2010-12-21 | 삼성전자주식회사 | Apparatus and method for amplifying multi mode power using predistorter |
| US7936213B2 (en) * | 2008-08-28 | 2011-05-03 | Xronet Corporation | Doherty amplifier and signal amplification system having the same, method for amplifying signal |
| CN107294498A (en) * | 2016-03-30 | 2017-10-24 | 中国科学院苏州纳米技术与纳米仿生研究所 | A kind of asymmetric Doherty amplifiers |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7471154B2 (en) * | 2006-08-08 | 2008-12-30 | Skyworks Solutions, Inc. | Bias circuit for maintaining high linearity at cutback power conditions |
| WO2008043098A2 (en) * | 2006-10-06 | 2008-04-10 | Vikram Bidare Krishnamurthy | System and method for on-chip im3 reduction over a broad range of operating powers |
| US9379673B2 (en) * | 2014-05-30 | 2016-06-28 | Qualcomm Incorporated | Distortion cancellation for dual stage carrier-aggregation (CA) low noise amplifier (LNA) non-linear second order products |
-
2017
- 2017-12-27 KR KR1020170181053A patent/KR102491944B1/en active IP Right Grant
-
2018
- 2018-10-16 US US16/161,236 patent/US10707820B2/en active Active
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6791418B2 (en) * | 2002-10-02 | 2004-09-14 | Koninklijke Philips Electronics N.V. | Capacitor coupled dynamic bias boosting circuit for a power amplifier |
| US6937094B2 (en) * | 2002-11-22 | 2005-08-30 | Powerwave Technologies, Inc. | Systems and methods of dynamic bias switching for radio frequency power amplifiers |
| CN1993883A (en) * | 2004-05-18 | 2007-07-04 | 皇家飞利浦电子股份有限公司 | Amplifier circuit with automatic gain correction |
| KR101002893B1 (en) * | 2005-08-06 | 2010-12-21 | 삼성전자주식회사 | Apparatus and method for amplifying multi mode power using predistorter |
| US7936213B2 (en) * | 2008-08-28 | 2011-05-03 | Xronet Corporation | Doherty amplifier and signal amplification system having the same, method for amplifying signal |
| CN107294498A (en) * | 2016-03-30 | 2017-10-24 | 中国科学院苏州纳米技术与纳米仿生研究所 | A kind of asymmetric Doherty amplifiers |
Also Published As
| Publication number | Publication date |
|---|---|
| KR102491944B1 (en) | 2023-01-25 |
| CN109981062B (en) | 2023-07-04 |
| KR20190079096A (en) | 2019-07-05 |
| US20190199301A1 (en) | 2019-06-27 |
| US10707820B2 (en) | 2020-07-07 |
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