CN109768051B - TFT-driven addressable cold cathode flat X-ray source device and preparation method thereof - Google Patents
TFT-driven addressable cold cathode flat X-ray source device and preparation method thereof Download PDFInfo
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Abstract
The invention discloses an addressable cold cathode flat plate X-ray source device driven by a TFT (thin film transistor), which comprises an active driving device; adopting a high-voltage insulating separator to parallelly and oppositely form an anode substrate and a cathode substrate; the active driving device is a high-voltage TFT; the anode substrate is provided with a metal thin film target layer; the cathode substrate comprises an addressable array of cold cathode electron sources; the high-voltage TFT and the cold cathode electron source array are arranged on the same substrate, and the preparation method of the addressable cold cathode flat-plate X-ray source device driven by the TFT integrates the TFT and the cold cathode on the same substrate; the high-voltage TFT adopts a circular ring structure, and the offset drain structure is adopted to realize the normal operation of the TFT under high source-drain voltage, so that a large-area driven high-resolution low-voltage addressable flat X-ray source can be realized.
Description
Technical Field
The invention belongs to the technical field of vacuum micro-nano electronics, and particularly relates to a TFT-driven addressable cold cathode flat X-ray source device, and a preparation method of the TFT-driven addressable cold cathode flat X-ray source device.
Background
With the addressable flat panel X-ray source, a new generation of low dose imaging methods can be developed. The addressable flat X-ray source emits electrons by adopting a field emission cold cathode microarray to bombard a metal target to generate X-rays. The device has the capability of transmitting point by point in a partitioning manner, has the advantages of low power consumption, short imaging working distance, high response speed and the like, does not need to be provided with a heavy heating power supply and cooling equipment, and is more flexible and convenient to use and convenient to carry. The addressable flat-panel X-ray source consists of an array of cold cathode electron sources which can be addressed in columns and an anode. The addressing driving mode of the cold cathode electron source array can be divided into a passive driving mode and an active driving mode. In both Active control of the emission current of field emission devices and a monolithic field emission device with a JFET, researchers use Active devices such as a field effect transistor (MOSFET) and a Junction Field Effect Transistor (JFET) to control the emission current of the cold cathode, so as to improve the uniformity of the emission current and the stability of the current of each pixel of the cold cathode. The MOSFET, the JFET and the cold cathode field emission array can be integrated together only through a silicon wafer, the maximum size of the current single wafer of the silicon wafer is 12 inches, and the large-area active drive addressable electron source array cannot be realized due to the limitation of a silicon substrate.
Disclosure of Invention
The invention provides an addressable cold cathode flat-plate X-ray source device driven by a TFT (thin film transistor) and a preparation method thereof, aiming at overcoming at least one defect in the prior art.
In order to solve the technical problems, the invention adopts the technical scheme that: the addressable cold cathode flat X-ray source device driven by the TFT comprises an active driving device, an anode substrate and a cathode substrate, wherein the anode substrate and the cathode substrate are parallelly opposite by adopting a high-voltage insulating spacer, the anode substrate is provided with a metal thin film target layer, the cathode substrate comprises a nano cold cathode array and a high-voltage TFT, the high-voltage TFT is an active driving device, and the high-voltage TFT comprises a grid electrode, a source electrode and a drain electrode; the high-voltage TFT and the nanometer cold cathode array are arranged on the same substrate. And low-voltage addressing is realized by using high-voltage TFT drive. High voltage TFTs are used in voltage environments up to 1000V or more. The cold cathode electron source array consists of cold cathode electrodes driven by high-voltage TFTs.
Preferably, the flat panel X-ray source device is operated in vacuum packaging or dynamic vacuum. The dynamic vacuum is not packaged, operates in a vacuum cavity and needs a vacuum pump to maintain the vacuum of an operating environment; the vacuum packaging is to package the device by adopting a vacuum sealing-off technology to form a portable device without a vacuum pump to maintain vacuum.
Preferably, each cell of the cold cathode electron source array is individually driven by the high voltage TFT. The addressable cold cathode field emission can be realized by adopting high-voltage TFT active control. When positive voltage is applied to the grid electrode of the high-voltage TFT, the corresponding cold cathode starts field emission; a negative voltage is applied to the gate electrode of the high voltage TFT and the corresponding cold cathode turns off the field emission. In the whole addressable cold cathode flat-plate X-ray source device, each unit is controlled by a separate high-voltage TFT, so that each unit can be controlled independently to realize the addressable function. Meanwhile, the efficiency is higher and more stable in the driving process.
The invention also provides a preparation method of the TFT-driven addressable cold cathode flat-plate X-ray source device, which comprises the following steps:
1) manufacturing a cathode substrate:
a) the substrate is cleaned and the substrate is cleaned,
b) a grid electrode is manufactured on a substrate, and the grid electrode can be made of metal materials such as Mo, Cr, Al, Ti, Cu and the like, metal oxide materials such as ITO, IZO, AZO and the like, and other materials with excellent conductive performance.
c) The gate electrode is covered with a gate insulating layer, which is composed of one or more layers of insulating films made of silicon oxide, silicon nitride, aluminum oxide or other materials with high resistance and their mixtures, and the insulating films can be prepared by common film preparation methods, such as electron beam evaporation, sputtering, and chemical vapor deposition.
d) And manufacturing an active layer on the gate insulating layer, wherein the active layer comprises a semiconductor material such as a-IGZO, a-IZTO, a-Si or p-Si. The active layer film can be prepared by a general film preparation method, such as sputtering, chemical vapor deposition and the like. And obtaining the patterned active layer by adopting a localized etching method, wherein the method for etching the active layer can be a general film etching method such as wet etching, reactive ion etching and the like.
e) And a source electrode and a drain electrode are manufactured above the active layer, an offset drain structure is arranged between the gate electrode and the drain electrode, and the source electrode and the drain electrode can be made of metal materials such as Mo, Cr, Al, Ti, Cu and the like, metal oxide materials such as ITO, IZO, AZO and the like, and other materials with excellent conductivity. The source electrode and the drain electrode film can be prepared by adopting electron beam evaporation, sputtering, chemical vapor deposition and other common film preparation methods.
f) And covering a passivation layer above the source electrode and the drain electrode, wherein the passivation layer is etched to form an etching through hole to expose the drain electrode, the passivation layer is composed of one or more layers of insulating films made of silicon oxide, silicon nitride, aluminum oxide or other materials with high resistance and mixed materials thereof, and the insulating films can be prepared by adopting a universal film preparation method, such as electron beam evaporation, sputtering, chemical vapor deposition and the like. The method for etching the insulating layer can be a general film etching method such as wet etching, reactive ion etching and the like.
g) And manufacturing a cold cathode electrode above the passivation layer, and connecting the cold cathode electrode with the drain electrode through an etching through hole, wherein the cold cathode electrode is made of one of materials with good high-temperature oxidation resistance, good conductivity such as ITO (indium tin oxide), IZO (indium zinc oxide), AZO (AZO) and the like.
h) And (2) locally manufacturing a cold cathode pre-growth film on the top of the cold cathode electrode, wherein the cold cathode pre-growth source film can be manufactured by using electron beam evaporation, sputtering, chemical vapor deposition and other general film preparation methods, and then obtaining a growth source film array for the growth of the cold cathode electron source array by adopting a stripping technology. The material of the cold cathode pre-grown film can be one or more of tungsten, zinc, copper, iron, molybdenum, chromium or oxidizable metal materials, and the one-dimensional metal oxide cold cathode electron source array is obtained by means of thermal oxidation.
i) Heating the cold cathode pre-grown film to 200-650 ℃ in an oxygen-containing atmosphere, preserving the heat for 30 minutes-12 hours, and finally naturally cooling to obtain a nano cold cathode array; the high-voltage TFT and the nanometer cold cathode array are both prepared on the cathode substrate.
2) Manufacturing an anode substrate:
a) an anode metal film target layer is manufactured on a substrate,
b) an anode protective layer is manufactured on the anode metal film target layer,
3) the anode substrate and the cathode substrate are parallel and opposite by adopting a high-voltage insulating separator.
An offset drain electrode structure is designed between the grid electrode and the drain electrode, an active layer of the offset drain electrode structure area is not regulated and controlled by a grid electric field, and meanwhile, the offset drain electrode structure can bear the higher anode voltage of the nanometer cold cathode array.
The offset drain structure enables the TFT to normally operate under high source leakage voltage, and an active layer of an offset drain region is not regulated by a grid electric field, namely a resistor is connected in series in a channel, so that the TFT can bear high source leakage voltage; preparing a passivation layer for protecting a channel of the TFT; etching an opening on the passivation layer to expose the drain electrode so as to integrate the cold cathode on the drain electrode subsequently; the nanometer cold cathode array is integrated right above the high-voltage TFT by adopting a vertical integration method, so that a high-resolution addressable cold cathode electron source array can be realized; the annealing process is completed for the high-voltage TFT while the metal oxide nanometer cold cathode array is obtained by using a thermal oxidation method.
Preferably, the high-voltage insulating spacer is one of glass, quartz, ceramic or insulating plastic, and the thickness of the high-voltage insulating spacer is 0.1 mm-500 mm.
Preferably, the anode substrate comprises a metal film target layer and an anode protection layer, the metal film target layer is a metal film formed by one or any combination of tungsten, molybdenum, rhodium, silver, copper, gold, chromium, aluminum, niobium, tantalum and rhenium, the thickness of the metal film target layer is 0.1-1500 mu m, and the anode protection layer is an alloy film resistant to high-temperature oxidation and has a thickness of 20-200 nm. The anode protective layer is used for protecting the anode metal layer from being oxidized in the high-temperature packaging process. If the device is to be vacuum packaged and the process temperature is above 400 ℃, the anode metal will be oxidized if there is no anode protection layer.
Preferably, the high-voltage TFT adopts a concentric circle structure, the gate electrode, the source electrode and the drain electrode are in a circular or circular shape, the centers of the circles of the gate electrode, the source electrode and the drain electrode are overlapped, and the length range of the offset drain electrode structure is 1-50% of the length of a channel. The inner radius range of the circular ring-shaped grid electrode of the high-voltage TFT is 0-500 mu m, the difference value between the inner radius and the outer radius is 5-500 mu m, the outer radius range of the circular ring-shaped source electrode is 0-500 mu m, the difference value between the inner radius and the outer radius is 5-500 mu m, the radius range of the circular drain electrode is 0-500 mu m, and the length range of the offset drain electrode structure is 0-500 mu m. The grid electrode, the source electrode and the drain electrode are made of materials which have conductive performance and are compatible with micro-processing technology, and the materials comprise Mo, Cr, ITO, Al, Cu, Ti, IZO or AZO.
Preferably, the active layer includes at least one of a-IGZO, a-IZTO, a-Si, or p-Si. The grid electrode, the source electrode and the drain electrode are made of materials which have conductive performance and are compatible with a micro-processing technology, and the materials comprise Mo, Cr, ITO, Al, Cu, Ti, IZO or AZO;
preferably, the gate insulating layer and the passivation layer are made of a material with a high resistance characteristic or a mixture thereof, the material includes silicon oxide, silicon nitride, aluminum oxide, or the like, the thickness of the gate insulating layer is 100nm to 500nm, and the thickness of the passivation layer is 0.1 μm to 1 μm.
Preferably, the material of the cold cathode pre-grown film can be one or more of tungsten, zinc, copper, iron, molybdenum, chromium or oxidizable metal materials, and a one-dimensional metal oxide cold cathode electrode is obtained by means of thermal oxidation. The cold cathode electrode comprises one of a one-dimensional nano material or a two-dimensional nano cold cathode film material. The one-dimensional linear nano material is ZnO or WOxAnd the CNTs and the two-dimensional nano cold cathode film material are graphene and diamond films.
Compared with the prior art, the invention has the beneficial effects that:
1) by utilizing the device characteristics of the high-voltage TFT, the stability of the cold cathode field emission current can be effectively improved, and the switching of the cold cathode field emission and the accurate control of the current are realized; the high-voltage TFT is used as active drive to drive the nano cold cathode array, so that the drive voltage can be reduced, and the cost of a drive circuit of the large-area cold cathode electron source is reduced; the integration of the high-voltage TFT and the nanometer cold cathode array is an effective way for realizing a large-area active driving and low-voltage addressable electron source array.
2) When the cold cathode electron source array works, high-voltage direct current or pulse voltage is applied to the anode, low-voltage direct current or pulse voltage is applied to the corresponding gate electrode of the high-voltage TFT, and the corresponding nano cold cathode electrode can realize the emission and regulation of electrons under the driving action of the high-voltage TFT. By selectively applying a voltage to the gate electrode of the high voltage TFT, low voltage driven addressable electron emission can be achieved.
3) The cold cathode electron source array is vertically integrated right above the high-voltage TFT, and the high-resolution addressable electron emission capability is achieved. And the annealing of the high-voltage TFT can be completed while the growth process of the nano cold cathode array is completed, and the two can be integrated on the glass substrate through the compatible preparation process. Therefore, the preparation of large-size electron source array devices can be realized, and the cold cathode electron source array can be applied to a flat-panel X-ray source to realize an addressable flat-panel X-ray source.
Drawings
FIG. 1 is a schematic structural diagram of a TFT-driven addressable cold cathode flat panel X-ray source device according to the present invention;
FIG. 2 is a cross-sectional view of the cold cathode electron source array of FIG. 1;
FIG. 3 is a schematic top view of the cold cathode electron source array of FIG. 1;
FIG. 4 is a schematic top view of a portion of the cold cathode electron source array of FIG. 3;
FIG. 5 is a flow chart of the fabrication of the cold cathode electron source array of FIG. 1;
description of the reference numerals
A substrate 1; a gate electrode 2; a gate insulating layer 3; an active layer 4; a drain electrode 5; an offset drain structure 6; a source electrode 7; a passivation layer 8; etching the through hole 9; a cold cathode electrode 10; a growth source film 11; a nano cold cathode array 12; a gate electrode bar 13; source electrode stripes 14; a separator 15; an anode metal thin film target layer 16; and an anode protective layer 17.
Detailed Description
The present invention will be further described with reference to the following embodiments.
The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar components; in the description of the present invention, it is to be understood that the terms "upper", "lower", "left", "right", "top", "bottom", "inner", "outer", and the like, if any, are used in the orientations and positional relationships indicated in the drawings only for the convenience of describing the present invention and simplifying the description, but not for indicating or implying that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and therefore the terms describing the positional relationships in the drawings are used for illustrative purposes only and are not to be construed as limiting the present patent.
Furthermore, if the terms "first," "second," and the like are used for descriptive purposes only, they are used for mainly distinguishing different devices, elements or components (the specific types and configurations may be the same or different), and they are not used for indicating or implying relative importance or quantity among the devices, elements or components, but are not to be construed as indicating or implying relative importance.
Example 1
As shown in fig. 1, which is a schematic structural diagram of a TFT-driven addressable cold cathode flat panel X-ray source device according to the present invention, the flat panel X-ray source is composed of a cold cathode electron array and an anode, which are addressable by using a high voltage TFT. An isolator 15 is adopted between the anode and the cold cathode electron source array to keep a certain distance between the anode and the cathode. The nano cold cathode array 12 emits electrons under the combined action of the anode high voltage and the pulse grid voltage to bombard the anode metal film target layer 16, so as to generate addressable X rays.
Example 2
As shown in fig. 2, a structural section view of the cold cathode electron source array in fig. 1 is shown. As shown in fig. 2, the basic structure of the electron source array includes a substrate 1, a circular ring-shaped gate electrode 2, a gate insulating layer 3, an active layer 4, a circular drain electrode 5, an offset drain structure 6, a circular ring-shaped source electrode 7, a passivation layer 8, a cold cathode electrode 10, and a nano cold cathode array 12. The nano cold cathode array 12 is vertically integrated right above the high-voltage TFT, and the cold cathode electrode 10 connects the nano cold cathode array 12 with the drain electrode 5 of the high-voltage TFT by etching the through hole 9, as shown in fig. 2 and 3. Because the nanometer cold cathode array 12 is driven by the high-voltage TFT, the addressable regulation of the cold cathode electron source array can be realized by regulating and controlling the grid voltage of the high-voltage TFT under the constant anode voltage.
As shown in fig. 3, a schematic diagram of a top view structure of the cold cathode electron source array in fig. 3; the source electrode bars 14 connect the source electrodes 7 of all the high-voltage TFTs in the same column, and the gate electrode bars 13 connect the gate electrodes 2 of all the high-voltage TFTs in the same row. Thereby, the addressing of the nanometer cold cathode array can be realized by applying pulse voltage to the grid electrode strip 13.
As shown in fig. 4, it is a schematic diagram of a partial top view of the cold cathode electron source array in fig. 3; the high-voltage TFT adopts a concentric circle structure, a grid electrode 2 and a source electrode 7 are circular rings, and a drain electrode 5 is circular. And there is an offset drain structure 6 between the gate electrode 2 and the drain electrode 5. The active layer 4 in the region of the offset drain structure 6 is not controlled by the electric field generated by the gate electrode 2, and can bear the higher anode voltage of the nano cold cathode array 12. The offset drain structure 6 allows the TFT to operate normally at high source drain voltages.
Example 3
Fig. 5 is a flow chart showing the manufacturing process of the cold cathode electron source array in fig. 1.
This example shows the fabrication process of a cold cathode electron source array using zinc oxide nanowires as cold cathode material and addressable with high voltage TFT drive.
Firstly, ultrasonically cleaning a glass substrate with acetone, ethanol and deionized water for 20 minutes respectively, and drying with nitrogen. And preparing a circular ring-shaped gate electrode 2 on the glass substrate by adopting a direct-current magnetron sputtering vacuum coating technology, photoetching and wet etching. The electrode material was molybdenum, which was about 200nm thick. As shown in fig. 5 (a).
And depositing a gate insulating layer 3 film above the gate electrode 2 by plasma enhanced chemical vapor deposition, wherein the insulating layer film is a silicon dioxide film and has a thickness of about 300 nm. And preparing the active layer 4 above the gate insulating layer 3 by adopting a radio frequency magnetron sputtering vacuum coating technology, photoetching and wet etching, wherein the active layer 4 is made of a-IGZO and has the thickness of about 50 nm. As shown in fig. 5 (b).
And preparing a circular source electrode 7 and a circular drain electrode 5 above the active layer 4 by adopting a direct-current magnetron sputtering vacuum coating technology, photoetching and wet etching. The electrode material was molybdenum, which was about 200nm thick. As shown in fig. 5 (c).
And depositing a passivation layer 8 film on the structure by adopting a plasma enhanced chemical vapor deposition method, wherein the passivation layer 8 film is a silicon dioxide film and the thickness of the silicon dioxide film is about 300 nm. As shown in fig. 5 (d).
And then etching silicon dioxide by adopting a reactive ion etching technology to obtain an etched through hole 9 for connecting the cold cathode electrode 10 and the drain electrode 5 of the high-voltage TFT. As shown in fig. 5 (e).
And then, preparing a cold cathode electrode 10 above the passivation layer 8 by adopting photoetching, direct-current magnetron sputtering vacuum coating technology and a stripping process. In the process of preparing and depositing the cold cathode electrode 10 film, the top electrode film is also deposited on the passivation layer 8 to etch the opening edge and the inner wall of the through hole 9 and the local high-voltage TFT drain electrode 5 exposed at the bottom of the etched through hole 9, so that the cold cathode electrode 10 can be well connected with the high-voltage TFT drain electrode 5. The top electrode material was ITO and was approximately 200nm thick. As shown in fig. 5 (f).
And photoetching and positioning a cold cathode electron source array growth area on the top of the cold cathode electrode 10, plating a growth source film 11 by adopting an electron beam evaporation vacuum coating technology, wherein the growth source film 11 is a zinc film, and obtaining a growth source zinc film array by adopting a stripping method. As in fig. 5 (g).
And finally, putting the glass substrate with the film structure into a tubular furnace for oxidation to obtain the zinc oxide cold cathode electron source array. The thermal oxidation process is firstly increased from room temperature to 470 ℃, then the temperature is kept at 470 ℃ for 2 hours, and finally the thermal oxidation process is naturally cooled, wherein the whole oxidation process is carried out under the air. As shown in fig. 5 (h).
The preparation method of the anode comprises the following steps: the glass substrate was ultrasonically cleaned with acetone, ethanol and deionized water for 20 minutes, respectively, and blown dry with nitrogen. On the glass substrate, an anode metal film target layer 16 is prepared by a direct-current magnetron sputtering vacuum coating technology. The anode metal thin film target layer 16 is tungsten and has a thickness of about 500 nm. And then preparing the anode protective layer 17 by adopting a direct current magnetron sputtering vacuum coating technology. The anode protection layer 17 is made of aluminum and has a thickness of about 100 nm. The ceramic spacer 15 has a thickness of 1 mm. Under the constant anode voltage, the flat-panel X-ray source capable of addressable emitting X-rays can be realized by applying pulse voltage to the grid of the high-voltage TFT.
The working principle of the invention is that when the cold cathode electron source array works, high-voltage direct current or pulse voltage is applied to the anode, and low-voltage direct current or pulse voltage is applied to the grid electrode of the corresponding high-voltage TFT, and the corresponding cold cathode electron source array can realize the emission and the regulation of electrons under the driving action of the high-voltage TFT. By selectively applying a voltage to the gate of the high voltage TFT, low voltage driven addressable electron emission can be achieved. Meanwhile, the cold cathode electron source array is vertically integrated right above the high-voltage TFT, and the invention has the capability of high-resolution addressable electron emission. And the annealing of the high-voltage TFT can be completed while the growth process of the cold cathode electron source array is completed, and the two can be integrated on the glass substrate through the compatible preparation process. Therefore, the preparation of large-size electron source array devices can be realized, and the cold cathode electron source array can be applied to a flat-panel X-ray source to realize an addressable flat-panel X-ray source.
It should be noted that the actual manufacturing process is not limited to the above-mentioned examples, and other similar micromachining methods may be used to realize the device structure, and other similar growing methods may be used to realize the growth of the cold cathode electron source array.
It should be understood that the above-described embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the claims of the present invention.
Claims (10)
1. An addressable cold cathode flat X-ray source device driven by TFT, comprising an anode substrate and a cathode substrate, wherein an insulating isolator is arranged between the anode substrate and the cathode substrate,
the anode substrate comprises a metal thin film target layer;
the cathode substrate comprises a nanometer cold cathode array and a high-voltage TFT; the high-voltage TFT is used for reaching a voltage environment of more than 1000V;
the high-voltage TFT is an active driving device and comprises a grid electrode, a source electrode and a drain electrode;
the high-voltage TFT and the nano cold cathode array are arranged on the same substrate;
the preparation method of the addressable cold cathode flat-plate X-ray source device driven by the TFT comprises the following steps:
1) manufacturing a cathode substrate:
a) cleaning the substrate;
b) manufacturing a grid electrode on a substrate;
c) covering the gate electrode with a gate insulating layer;
d) manufacturing an active layer on the gate insulating layer;
e) forming a source electrode and a drain electrode above the active layer, with an offset drain structure between the gate electrode and the drain electrode;
f) covering a passivation layer above the source electrode and the drain electrode, and etching and opening the passivation layer to form an etching through hole to expose the drain electrode;
g) manufacturing a cold cathode electrode above the passivation layer, wherein the cold cathode electrode is connected with the drain electrode through the etching through hole;
h) making a cold cathode pre-growth film on the top of the cold cathode electrode in a localized manner;
i) heating the cold cathode pre-grown film to 200-650 ℃ in an oxygen-containing atmosphere, preserving the heat for 30 minutes-12 hours, and finally naturally cooling to obtain a nano cold cathode array;
2) manufacturing an anode substrate:
a) manufacturing an anode metal film target layer on a substrate;
b) manufacturing an anode protective layer on the anode metal film target layer;
3) the anode substrate and the cathode substrate are parallel and opposite, and the insulating separator is arranged between the anode substrate and the cathode substrate.
2. The TFT-driven addressable cold cathode flat panel X-ray source device according to claim 1, wherein the addressable cold cathode flat panel X-ray source device is operated under vacuum packaging or dynamic vacuum.
3. The TFT-driven addressable cold cathode flat panel X-ray source device of claim 1, wherein each cell of the array of nano-cold cathodes is driven individually by the high voltage TFT.
4. A method for preparing an addressable cold cathode flat plate X-ray source device driven by a TFT (thin film transistor) is characterized by comprising the following steps of:
1) manufacturing a cathode substrate:
a) cleaning the substrate;
b) manufacturing a grid electrode on a substrate;
c) covering the gate electrode with a gate insulating layer;
d) manufacturing an active layer on the gate insulating layer;
e) forming a source electrode and a drain electrode above the active layer, with an offset drain structure between the gate electrode and the drain electrode;
f) covering a passivation layer above the source electrode and the drain electrode, and etching and opening the passivation layer to form an etching through hole to expose the drain electrode;
g) manufacturing a cold cathode electrode above the passivation layer, wherein the cold cathode electrode is connected with the drain electrode through the etching through hole;
h) making a cold cathode pre-growth film on the top of the cold cathode electrode in a localized manner;
i) heating the cold cathode pre-grown film to 200-650 ℃ in an oxygen-containing atmosphere, preserving the heat for 30 minutes-12 hours, and finally naturally cooling to obtain a nano cold cathode array;
2) manufacturing an anode substrate:
a) manufacturing an anode metal film target layer on a substrate;
b) manufacturing an anode protective layer on the anode metal film target layer;
3) the anode substrate and the cathode substrate are parallel and opposite, and the insulating separator is arranged between the anode substrate and the cathode substrate.
5. The method of claim 4, wherein the insulating spacer is one of glass, quartz, ceramic or insulating plastic, and the thickness of the insulating spacer is 0.1 mm-500 mm.
6. The method for manufacturing the addressable cold cathode flat panel X-ray source device driven by the TFT according to claim 4, wherein the metal thin film target layer is one or a combination of any several of tungsten, molybdenum, rhodium, silver, copper, gold, chromium, aluminum, niobium, tantalum and rhenium, the thickness of the metal thin film target layer is 0.1-1500 μm, the anode protection layer is an oxidation-resistant alloy thin film, and the thickness of the anode protection layer is 20-200 nm.
7. The method for manufacturing an addressable cold cathode flat panel X-ray source device driven by a TFT according to claim 4, wherein the gate electrode, the source electrode, and the drain electrode are circular or circular and have coinciding centers, and the length of the offset drain structure ranges from 1% to 50% of the channel length.
8. The method of claim 4, wherein the active layer comprises at least one of a-IGZO, a-IZTO, a-Si, or p-Si.
9. The method for manufacturing an addressable cold cathode flat panel X-ray source device driven by a TFT according to claim 4, wherein the thickness of the gate insulating layer is 100nm to 500nm, and the thickness of the passivation layer is 0.1 μm to 1 μm.
10. The method of claim 4, wherein the material of the cold cathode pre-grown thin film is one or more of oxidizable metal materials, and the cold cathode electrode comprises one of one-dimensional nano materials or two-dimensional nano cold cathode thin film materials.
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