CN109766310A - A kind of method that multi-channel high-speed communicates between digital fault oscilloscope internal plug - Google Patents
A kind of method that multi-channel high-speed communicates between digital fault oscilloscope internal plug Download PDFInfo
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- CN109766310A CN109766310A CN201910038252.6A CN201910038252A CN109766310A CN 109766310 A CN109766310 A CN 109766310A CN 201910038252 A CN201910038252 A CN 201910038252A CN 109766310 A CN109766310 A CN 109766310A
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Abstract
The present invention relates to electric power digital fault wave recording device fields.Digital fault oscilloscope is made of multi-block data acquisition plug-in unit, 1 block of data processing plug-in unit and 1 administrative unit.The present invention 1 block of data processing plug-in unit and 1-4 block number according to acquisition insert design in a cabinet.Data processing plug-in unit and every block number are according to 32 pairs of BLVDS high-speed differential signal channels for being up to one-to-one connection between acquisition plug-in unit.Communication uses anti-interference coding, scrambling code encoding and decoding and response feedback to guarantee that communication is correct.Each pair of BLVDS signal highest communication speed reaches 500 megabits per second.BLVDS can be with two-way transmission signals.Data processing plug-in unit and every block number contain 1 programmable logic chip according to acquisition plug-in unit.Data processing plug-in unit has the 4-32 channel BLVDS, and each data acquisition plug-in unit connects the 1-8 channel BLVDS.The present invention is to realize that aforementioned communication function need to only occupy less programmable logic chip resource.The advantages of this design is: communication speed is high, communication channel is more, it is flexible, at low cost with digital fault oscilloscope configuration to take up less resources.
Description
Technical field
The present invention relates to electric power digital fault wave recording device fields, are related specifically to inside digital fault oscilloscope
How communication between plug-in unit, which designs, could make that communication speed is higher, communication channel is more and it is less to occupy resource.
Background technique
As shown in Figure 1, digital fault oscilloscope will connect several network signals.These network signals come from combining unit
(MU) or the network switch from substation.Digital fault oscilloscope will may also be handed on rare occasion with special installation
Change a small amount of data.Digital fault oscilloscope is by multi-block data acquisition plug-in unit, 1 block of data processing plug-in unit and 1 administrative unit
Composition.Data acquire plug-in unit and acquire above-mentioned network signal, may also want the other individual signals of preliminary treatment on rare occasion.Number
Processing function of the information for acquiring plug-in unit from data being classified and extracted etc. is completed according to processing plug-in unit.Data acquire plug-in unit
Programmable logic chip is usually included, the network signal interface more with number in this way is easier.Data processing plug-in unit is generally
Containing programmable logic chip.Data processing plug-in unit is communicated with multi-block data acquisition plug-in unit.Each network signal from MU
It includes analog value (SV), network speed is 100 megabits per second.Each network signal from the network switch includes switching value
(GOOSE), analog value (SV) or other digital signals, network speed are 100 megabits per second or 1 kilomegabit per second.Here gigabit
Network signal network speed refers to the average network speed in every frame, but considers requirement of the current user to digital fault oscilloscope, every frame
Between may have a gap, it is per second in average network speed be actually not more than 400 megabits per second.At present to digital fault oscilloscope
Maximum configured for, combining unit (MU) number for needing to connect is no less than 24, selected sampled value (SV) port number
No less than 128 tunnels, switching value (GOOSE) control block are no less than 64, and selected on-off model is no less than 512 tunnels, access
Overall network data volume be greater than 400 megabits per second.Since it is desired that the total number of network signal of acquisition is relatively more, information rate compares
Fast and total amount of data is bigger, it is therefore desirable to which multi-block data acquires plug-in unit, acquires plug-in unit to data processing plug-in unit and multi-block data
Between communication need it is relatively high.
Communication between data processing plug-in unit and multi-block data acquisition plug-in unit may be selected parallel interface, PCIE interface, USB and connect
Mouth and Ethernet interface etc..Because CPU and programmable logic chip usually not quantity are more, the higher USB interface of performance, because
This is seldom selected using USB interface.
Summary of the invention
The object of the present invention is to which acquiring the communication between plug-in unit for data processing plug-in unit and multi-block data provides a kind of side
Method makes communication speed than very fast, communication channel number is more and communication data total amount is bigger, and configuration is relatively more flexible, accounts for
It is fewer relatively low with cost with resource.
As shown in Fig. 2, the technical solution adopted by the present invention is as follows.It is 1-4 block that data, which acquire plug-in unit, and each data acquisition is inserted
2-8 hundred megabit networks signals of part connection, 1-2 giga-bit network signal or a small amount of distinctive signal, total amount of data are no more than
2 kilomegabit per second.The advantages of designing in this way is that the every block of data processing plug-in unit and multi-block data of design acquire plug-in unit area and connect
Line terminals size is suitable, data processing plug-in unit and multi-block data acquisition plug-in unit can be put in a cabinet, be reduced costs；
The data acquisition plug-in unit and different configuration of network signal of flexible configuration difference block number, that is, number when meeting maximum configured when production
The requirement of word fault wave recording device, but when reducing smaller configuration digital fault oscilloscope cost.
Each channel communications between data processing plug-in unit and multi-block data acquisition plug-in unit are all the principal and subordinate side of one-to-one connection
Formula communication.Each channel high-speed differential signal is all BLVDS bus-type differential signal, can have tri-state, input and defeated with transmitted in both directions
Three kinds of states out, most high speed reach 500 megabits per second.Here differential signal uses bus-type, and advantage is with a pair of of differential signal
A frame information can be sent can then receive feedback information again, reduce the differential signal sum of device.Most high speed design
It is 500 megabits per second, selects low-cost Cyclone type FPGA that can accomplish.Every Cyclone type FPGA can have tens pairs
The BLVDS differential signal of 500 megabits of communication speeds per second, FPGA work clock is also up to 500 megahertzs.Here using one-to-one
Rather than one-to-many connection type, it solves wave impedance and is not easy matched difficult point, reduce high speed transmission of signals to manufacture work
The requirement of skill.Here it is communicated using master-slave mode, so that bit synchronization, byte of sync and frame synchronization programming simplify, reduces occupancy
FPGA resource.
Each channel communications between data processing plug-in unit and multi-block data acquisition plug-in unit, use with the communication side of question-response
Formula transmits data and feedback information.Data all use that anti-interference coding, to include scrambling code encoding and decoding synchronous with clock with feedback information
Information, discovery transmission mistake then abandon and then repeatedly transmit same frame.Design is just without transmitting synchronizing clock signals in this way
Additional channels only need to reduce data processing by the FPGA at communication both ends respectively since extracting synchronizing clock signals in channel information
Plug-in unit and data acquire the number of channels between plug-in unit or reduce the PLL module number of FPGA.
The difference that can be configured according to digital fault oscilloscope selects different configuration of data to acquire plug-in unit.Some data
Acquire 8 tunnel of plug-in card configuration, hundred megabit networks interface, some data acquisition 2 tunnel kilobit network interfaces of plug-in card configuration or other configurations.
It is also possible to select different configuration of data processing plug-in unit.Some data processing plug-in card configurations 4 are to BLVDS, 20 pairs of some configurations
BLVDS or other configurations.The purpose of flexible configuration in this way is to meet digital fault oscilloscope requirement, and improving property
Valence ratio.
Every block number all uses a Cyclone type FPGA according to acquisition plug-in unit.This FPGA completion acquisition network signal function,
With the function of data processing plug-in unit communication and the function of other a small amount of distinctive signal processing.This FPGA can also complete intelligent control
Function.This FPGA can record the time of network information arrival, and error is less than 100 nanoseconds.Have inside FPGA for saving number frame
The high-speed RAM of data can be used as the caching before exchanging every frame data with data processing plug-in unit.Because having selected such
FPGA just without cpu chip and large capacity RAM chip, thus is reduced costs.
Data processing plug-in unit uses the stronger Cyclone type FPGA of a function.This FPGA completes to insert with data acquisition
The function of part communication and other largely work unrelated with aforementioned communication.There is the high-speed RAM of enough capacity inside FPGA, as number
According to the caching of processing plug-in unit communication data, there are also other purposes.Data acquisition plug-in unit also uses cpu chip, large capacity RAM core
Piece and other important chips, to complete other functions.
Advantage of the present invention compared with use parallel interface communication is: communication speed is faster, communication connection radical lacks
It is more, communication distance is much longer, is able to satisfy the maximum configured of digital fault oscilloscope, reduce each plug-in unit volume and reduce
Requirement to manufacturing process.
Advantage of the present invention compared with using PCIE interface communication is: needing using when PCIE interface in data processing plug-in unit
It acquires in plug-in unit with data all using programmable logic chip that is more expensive, being of little use；This chip must be with enough multichannels
PCIE interface；Buying can be relatively difficult when thus using PCIE interface, and increased cost can be significant.
Advantage of the present invention compared with being communicated using Ethernet interface is: needing using when Ethernet interface in data processing
Network interface chip is used in plug-in unit and data acquisition plug-in unit, thus occupies more resource and biggish arrangement space；This is not
Such as using can be connected directly when BLVDS in addition to needing several resistance with signal, thus increase the volume and cost of each plug-in unit.
The advantages of using when Ethernet interface is that communication distance is significantly longer, and the communication between different cabinets can be used.The present invention
Data processing plug-in unit and all data acquisition insert design are reduced device volume and cost in a cabinet, and solved
Certainly in terms of communication distance the problem of.
The advantage of the present invention compared with prior art has:
(1) data processing plug-in unit and all data acquisition plug-in unit reduce device volume and cost in a cabinet；
(2) data processing plug-in unit and every block of data processing plug-in unit all only have a programmable logic chip, and communication occupies resource
It is few, it is small in size；
(3) each pair of BLVDS signal that communication uses, highest communication speed reach 500 megabits per second, can be with transmitted in both directions；
(4) data processing plug-in unit has 4-32 high-speed differential signal channel, and it is 1-4 block, every block number evidence that data, which acquire plug-in unit,
Acquisition plug-in unit has 1-8 high-speed differential signal channel.Then plug-in unit area and connecting terminal size are suitable for design in this way, configuration spirit
It is living, reduce cost.The division of each pin function is more appropriate, and other parts, version are not influenced when needing to do small modifications to plug-in unit
This upgrading is easier to；
(5) one-to-one master-slave mode is carried out using high-speed differential signal between data processing plug-in unit and multi-block data acquisition plug-in unit
Communication, communication information all use anti-interference coding, include scrambling code encoding and decoding and clock synchronization information.Without transmitting synchronised clock letter
Number additional channels.Reduce communication channel sum or the PLL module number of FPGA；
(6) selects more common chip, and purchase channel is guaranteed, general not have to make a reservation for, and reduces cost；
(7) fault wave recording device structure is compacter, and small volume reduces cost.
Detailed description of the invention
Fig. 1 is the schematic diagram of digital fault oscilloscope connection network signal.
Fig. 2 is the composition block diagram of digital fault oscilloscope of the present invention.
Fig. 3 is the block diagram of means of communication embodiment between data processing plug-in unit and data processing plug-in unit of the present invention.
Specific embodiment
As shown in figure 3, fault wave recording device is configured to 24 Lu Baizhao network signals of record and 2 road gigabit network signals.
Since it is desired that record network signal sum is more, informational capacity is big, therefore 4 block numbers are configured according to acquisition plug-in unit.Preceding 3 block number evidence
Acquisition plug-in unit all configures 8 Lu Baizhao network signals, and the 4th block number is according to acquisition 2 road gigabit network signal of plug-in card configuration.
Preceding 3 block number is identical according to acquisition insert design.Every block number has 4 couples of BLVDS according to acquisition insert design, and theoretical most high speed is total
2 megabits per second.Situations such as considering code efficiency and response, 1.2 megabits per second altogether of practical communication speed.4th block number is inserted according to acquisition
Part design has 8 couples of BLVDS, and theoretical most high speed is 4 megabits per second total.The practical communication speed of situations such as considering code efficiency and response is total
2.4 megabits per second.
The fpga chip that data acquire plug-in unit is all EP4CE6F17, includes most 66 couples of BLVDS, 6272 LE, 2 PLL
Block and 270K high-speed RAMs.High-speed RAM can keep in 16 frame network data.These data need to be sent to data processing plug-in unit in time
With persistence.If to keep in 1 millisecond of network data in data acquisition plug-in unit, it is necessary to about 1 Mbytes of high-speed RAM,
So the present invention does not design in this way.
The fpga chip of data processing plug-in unit is EP4CGX22CF19, includes most 64 couples of BLVDS, 21180 LE, 4
PLL block, 756K high-speed RAM and a PCIE stone.High-speed RAM can cache 42 frame network data, these network datas need by
It is processed in time, be saved in large capacity DDR and hard disk etc..Data processing plug-in unit has used 20 couples of BLVDS in the present embodiment.
125M hertz, 250M hertz and 500M hertz of fpga chip dominant frequency etc..125M hertz of dominant frequency uses most.500M
The dominant frequency of hertz is only mainly used in the range of 1 LE block.Actual measurement shows that the BLVDS of selected FPGA can be every in communication speed
Data are correctly transmitted at the second 500M.
Claims (6)
1. a kind of method that multi-channel high-speed communicates between digital fault oscilloscope internal plug, digital fault oscilloscope is by more
Block number acquires plug-in unit and completes the acquisition network information according to acquisition plug-in unit, 1 block of data processing plug-in unit and 1 administrative unit composition, data
With the function of the presumable individual distinctive signals of preliminary treatment, data processing plug-in unit is completed to the information from data acquisition plug-in unit
Classified and extracted etc. processing function, data processing plug-in unit is communicated with multi-block data acquisition plug-in unit, this number therefore
The multi-channel high-speed means of communication are characterized in that between barrier wave recording device internal plug: data processing plug-in unit and 1-4 block number are according to acquisition
For plug-in unit in a cabinet, data processing plug-in unit and every block of data processing plug-in unit all include a programmable logic chip, these
Programmable logic chip generates the high-speed differential signal for being used to draw several channels of this plug-in unit, the 4-32 of data processing plug-in unit
A high-speed differential signal connects and composes multichannel height according to the high-speed differential signal progress for acquiring plug-in unit is one-to-one with every block number respectively
Fast communication, communication are used anti-interference coding, scrambling code encoding and decoding and response feedback to guarantee that communication is correct, are patrolled using aforementioned may be programmed
The RAM block in chip is collected as the cache for sending and receiving data.
2. the method that multi-channel high-speed communicates between a kind of digital fault oscilloscope internal plug according to claim 1,
It is characterized in that, data processing plug-in unit has 4-32 high-speed differential signal channel, every block number has 1-8 high according to acquisition plug-in unit
Fast differential signal channel.
3. the method that multi-channel high-speed communicates between a kind of digital fault oscilloscope internal plug according to claim 1,
It is characterized in that, the communication in each channel is completed by two side of principal and subordinate, the one-to-one connection of two sides, masters are data processing plug-in units,
Driven side is data acquisition plug-in unit, and every side has a pair of of high-speed differential signal, and each pair of high-speed differential signal is made of both threads, nothing
The additional channels that synchronizing clock signals need to be transmitted, by communicating the aforementioned programmable logic chip at both ends respectively since mentioning in channel information
Take synchronizing clock signals.
4. the method that multi-channel high-speed communicates between a kind of digital fault oscilloscope internal plug according to claim 1,
It is characterized in that, the high-speed differential signal in each channel is all BLVDS bus-type differential signal, there can be tri-state, defeated with transmitted in both directions
Enter and export three kinds of states, highest communication speed reaches 500 megabits per second.
5. the method that multi-channel high-speed communicates between a kind of digital fault oscilloscope internal plug according to claim 1,
It is characterized in that, every aforementioned programmable logic chip all uses FPGA, sub-fraction resource therein is used to generate high speed difference
Sub-signal, other major part resources are used to complete other functions of digital fault oscilloscope.
6. the method that multi-channel high-speed communicates between a kind of digital fault oscilloscope internal plug according to claim 1,
It is characterized in that, the aforementioned programmable logic chip in data acquisition plug-in unit, is also used to receive and cache the information from network
These information are transmitted to data processing plug-in unit, use with the time for recording the arrival of these information and then by communication channel above-mentioned
Carry out the presumable other individual distinctive signals of preliminary treatment, also be used to complete the function of intelligent control, data acquire plug-in unit because
Use aforementioned programmable logic chip then without cpu chip and large capacity RAM chip.
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| CN201910038252.6A CN109766310A (en) | 2019-01-16 | 2019-01-16 | A kind of method that multi-channel high-speed communicates between digital fault oscilloscope internal plug |
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| CN201910038252.6A CN109766310A (en) | 2019-01-16 | 2019-01-16 | A kind of method that multi-channel high-speed communicates between digital fault oscilloscope internal plug |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110221152A (en) * | 2019-07-19 | 2019-09-10 | 华北电力大学 | A kind of high speed communication circuit module between relay-protection tester internal plug |
| CN114280974A (en) * | 2021-11-17 | 2022-04-05 | 南京国电南自维美德自动化有限公司 | Centralized alternating current data sampling synchronization method and device based on FPGA |
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