CN109712557A - A kind of shift register and its driving method, gate driving circuit, display device - Google Patents
A kind of shift register and its driving method, gate driving circuit, display device Download PDFInfo
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- CN109712557A CN109712557A CN201910209348.4A CN201910209348A CN109712557A CN 109712557 A CN109712557 A CN 109712557A CN 201910209348 A CN201910209348 A CN 201910209348A CN 109712557 A CN109712557 A CN 109712557A
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Abstract
The embodiment of the present invention provides a kind of shift register and its driving method, gate driving circuit, display device, is related to field of display technology, can reduce the noise that signal output end switches between high potential and low potential and generated；Sub-circuit is inputted in the shift register inputs a signal into the voltage output at end to the first control node；First output controls sub-circuit for the voltage output of the first clock signal terminal to the second control node；Second output control sub-circuit exports the medium voltage at second voltage end to the second control node under the control of second clock signal end and third clock signal terminal；Sub-circuit is exported under the control of the first control node, the second control node is exported to signal output end；Reset subcircuit is under reset signal end and the control of second clock signal end, by the voltage output at first voltage end to the first control node；Sub-circuit is pulled down under the control of reset signal end and second clock signal end, by the voltage output at first voltage end to signal output end.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of shift registers and its driving method, gate driving electricity
Road, display device.
Background technique
GOA (Gate Driver on Array, array substrate row driving) is a kind of gate driving circuit to be integrated in battle array
Technology on column substrate, wherein GOA circuit is made of the shift register of multi-stage cascade, the output of every level-one shift register
End is connected with a grid line in array substrate (display panel), for exporting gated sweep signal to the grid line, aobvious
When showing that panel is shown, progressively scanned by a plurality of grid line of GOA circuit drives.
Wherein, during the work time, the current potential of the output end of each shift register can be in high level and low electricity for GOA circuit
It is switched between flat, for example, output end switches to high level from low level from charge node to output stage；To can be
The higher noise of amplitude (noise) is inspired on display panel, so that certain negative effect can be caused to display panel；Especially
It is for the display panel using active pen, the functional effect of above-mentioned noise meeting severe jamming active pen.
Summary of the invention
The embodiment of the present invention provides a kind of shift register and its driving method, gate driving circuit, display device, energy
Reduce the noise generated because the signal output end of shift register switches between high potential and low potential.
In order to achieve the above objectives, the embodiment of the present invention adopts the following technical scheme that
The embodiment of the present invention provides a kind of shift register, comprising: input sub-circuit, output sub-circuit, reset subcircuit,
Pull down sub-circuit, the first output control sub-circuit, the second output control sub-circuit, the first energy storage sub-circuit；The input electricity
Road is connect with signal input part, second clock signal end, the first control node, for the voltage in the second clock signal end
Control under, by the voltage output of the signal input part to first control node；The first output control sub-circuit
It is connect with the first clock signal terminal, the second control node, under the control of the voltage of first clock signal terminal, by institute
The voltage output of the first clock signal terminal is stated to the second control node；The second output control sub-circuit and the second clock
Signal end, third clock signal terminal, second control node, the connection of second voltage end, in the second clock signal
Under the control of the voltage of end and the third clock signal terminal, the medium voltage at the second voltage end is exported to described second
Control node；Wherein, the medium voltage at the second voltage end be greater than each clock signal terminal low level voltage, and be less than it is each when
The high level voltage of clock signal end；The output sub-circuit and first control node, second control node, signal are defeated
Outlet connection, under the control of the voltage of first control node, extremely by the voltage output of second control node
The signal output end；The reset subcircuit and reset signal end, the second clock signal end, first control save
Point, the connection of first voltage end, under the control of the reset signal end and the voltage of the second clock signal end, by institute
The voltage output at first voltage end is stated to first control node；It is the drop-down sub-circuit and the reset signal end, described
Second clock signal end, the signal output end, first voltage end connection, at the reset signal end and described the
Under the control of the voltage of two clock signal terminals, by the voltage output at the first voltage end to the signal output end；Described
One energy storage sub-circuit is connect with first control node and the signal output end, for by the electricity of first control node
Pressure is stored, and is also used to discharge to first control node.
In some embodiments, the input sub-circuit includes the first transistor；The grid of the first transistor and institute
The connection of second clock signal end is stated, the first pole is connect with the signal input part, and the second pole is connect with first control node.
In some embodiments, the first energy storage sub-circuit includes first capacitor；The first end of the first capacitor with
The first control node connection, the second pole is connect with the signal output end.
In some embodiments, the output sub-circuit includes second transistor；The grid of the second transistor and institute
The connection of the first control node, the first pole and second control node are stated, the second pole is connect with the signal output end.
In some embodiments, the first output control sub-circuit includes third transistor；The third transistor
Grid and the first pole are connect with first clock signal terminal, and the second pole is connect with second control node.
In some embodiments, the second output control sub-circuit includes the 4th transistor and the 5th transistor；It is described
The grid of 4th transistor is connect with the third clock signal terminal, and the first pole is connect with the second voltage end, the second pole with
First pole of the 5th transistor connects；The grid of 5th transistor is connect with the second clock signal end, and second
Pole is connect with second control node.
In some embodiments, the reset subcircuit includes the 6th transistor and the 7th transistor；6th crystal
The grid of pipe is connect with the reset signal end, and the first pole is connect with first control node, the second pole and the 7th crystalline substance
First pole of body pipe connects；The grid of 7th transistor is connect with the second clock signal end, the second pole and described the
The connection of one voltage end.
In some embodiments, the drop-down sub-circuit includes the 8th transistor and the 9th transistor；8th crystal
The grid of pipe is connect with the reset signal end, and the first pole is connect with the signal output end, the second pole and the 9th crystal
First pole of pipe connects；The grid of 9th transistor is connect with the second clock signal end, the second pole and described first
Voltage end connection.
In some embodiments, the second voltage end is AVDD voltage end.
The embodiment of the present invention also provides a kind of gate driving circuit, including by positioned at odd level and successively cascade as before
The first driving unit that the shift register stated is constituted, and by be located at even level and successively cascade displacement as the aforementioned post
The second driving unit that storage is constituted.
In first driving unit, the signal input part of the first odd level shift register connects the first initial signal
End, other than the first odd level shift register, the signal input part and the odd number of any odd level shift register
The signal output end of the upper odd level shift register of grade shift register is connected；In addition to last odd level shift LD
Other than device, the reset signal end of any odd level shift register is posted with the upper odd level displacement of the odd level shift register
The signal output end of storage is connected；Last described odd level shift register is separately provided reset signal end, or with institute
State the connection of the first starting signal end；In second driving unit, the signal input part of the first even level shift register connects
The second initial signal end is connect, other than the first even level shift register, the signal of any even level shift register
Input terminal is connected with the signal output end of the upper even level shift register of the even level shift register；In addition to last
Other than even level shift register, the reset signal end of any even level shift register is upper with the even level shift register
The signal output end of one even level shift register is connected；Reset letter is separately provided in last described even level shift register
Number end, or connect with second initial signal end；In the gate driving circuit, the level Four shift register that is arranged successively
A shifting deposit unit is constituted, different shifting deposit units is made of different level Four shift registers.
In each shifting deposit unit: the first clock signal terminal of first order shift register, second clock signal end,
Third clock signal terminal is successively believed with the first system clock signal terminal, third clock signal of system end, the 4th system clock respectively
Number end connection.First clock signal terminal of second level shift register, second clock signal end, third clock signal terminal respectively according to
It is secondary to be connect with second system clock signal terminal, the 4th clock signal of system end, the first system clock signal terminal；Third level displacement is posted
First clock signal terminal of storage, second clock signal end, third clock signal terminal respectively successively with third clock signal of system
End, the connection of the first system clock signal terminal, second system clock signal terminal；First clock signal of fourth stage shift register
End, second clock signal end, third clock signal terminal respectively successively with the 4th clock signal of system end, second system clock signal
End, the connection of third clock signal of system end.
The embodiment of the present invention also provides a kind of display device, including gate driving circuit above-mentioned.
The embodiment of the present invention also provides a kind of driving method of shift register as the aforementioned, comprising:
Charging stage: under the control of the voltage from the second clock signal end, the input sub-circuit is opened, will
The voltage output of the signal input part is stored into the first storage sub-circuit to first control node.
Intermediate output stage: under the control of the voltage from the second clock signal end, the input sub-circuit is protected
Unlatching is held, by the voltage output of the signal input part to first control node；In the voltage of first control node
Control under, the output sub-circuit is opened；Also, coming from the second clock signal end and the third clock signal terminal
Voltage control under, it is described second output control sub-circuit open, will from the medium voltage at the second voltage end export
To the signal output end.
First output stage: the first energy storage sub-circuit discharges to first control node, in first control
Under the control of the voltage of node, the output sub-circuit is opened, and institute under the control of the voltage in first clock signal terminal
The first output control sub-circuit is stated to open, it will be defeated by the output sub-circuit from the voltage of first clock signal terminal
Out to the signal output end.
Second output stage: the first energy storage sub-circuit discharges to first control node, in first control
Under the control of the voltage of node, the output sub-circuit is kept it turning on, under the control of the voltage of first clock signal terminal
The first output control sub-circuit is kept it turning on, and the voltage from first clock signal terminal is persistently exported to described
Signal output end.
Reseting stage: described under the control of the voltage from the reset signal end and the second clock signal end
Reset subcircuit is opened, and the voltage output from the first voltage end to first control node is resetted；Coming
From under the control of the reset signal end and the voltage of the second clock signal end, the drop-down sub-circuit is opened, and will be come from
The voltage output at the first voltage end to the signal output end is resetted.
The embodiment of the present invention provides a kind of shift register and its driving method, gate driving circuit, display device, the shifting
Bit register include: input sub-circuit, output sub-circuit, reset subcircuit, drop-down sub-circuit, first output control sub-circuit,
Second output control sub-circuit, the first energy storage sub-circuit；Input sub-circuit and signal input part, second clock signal end, first
Control node connection, under the control of the voltage of second clock signal end, inputting a signal into the voltage output at end to first
Control node；First output control sub-circuit is connect with the first clock signal terminal, the second control node, for believing in the first clock
Number end voltage control under, by the voltage output of the first clock signal terminal to the second control node；Second output control son electricity
Road is connect with the second clock signal end, third clock signal terminal, second control node, second voltage end, is used for
Under the control of the voltage of second clock signal end and third clock signal terminal, the medium voltage at second voltage end is exported to second
Control node；Wherein, the medium voltage at second voltage end is greater than the low level voltage of each clock signal terminal, and is less than each clock and believes
Number end high level voltage；Output sub-circuit is connect with the first control node, the second control node, signal output end, is used for
Under the control of the voltage of first control node, by the voltage output of the second control node to signal output end；Reset subcircuit with
Reset signal end, second clock signal end, the first control node, the connection of first voltage end, at reset signal end and second
Under the control of the voltage of clock signal terminal, by the voltage output at first voltage end to the first control node；It pulls down sub-circuit and answers
Position signal end, second clock signal end, signal output end, the connection of first voltage end, in reset signal end and second clock
Under the control of the voltage of signal end, by the voltage output at first voltage end to signal output end；First energy storage sub-circuit and first
Control node is connected with signal output end, for storing the voltage of the first control node, is also used to the first control section
Point discharges.
In conclusion at work compared to shift register in the related technology, because signal output end can be in high potential
It, can be in the charging stage using shift register provided in an embodiment of the present invention for switching between low potential and generating noise
Between normal output stage (the first output stage, the second output stage), pass through the second output control sub-circuit and output
Sub-circuit, by medium voltage (current potential between the high potential and low potential) output at second voltage end to signal output end；
That is, the signal output end of the shift register in the present invention has one in output signal between low potential and high potential
The transition stage of a intermediate potential generates to reduce because signal output end switches directly between high potential and low potential
Noise.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is a kind of structural schematic diagram for shift register that the relevant technologies of the present invention provide；
Fig. 2 is a kind of structural schematic diagram of shift register provided in an embodiment of the present invention；
Fig. 3 is a kind of structural schematic diagram of gate driving circuit provided in an embodiment of the present invention；
Fig. 4 is a kind of timing control schematic diagram of shift register provided in an embodiment of the present invention；
Fig. 5 is a kind of driving method flow diagram of shift register provided in an embodiment of the present invention；
Fig. 6 is a kind of one of driving process schematic of shift register provided in an embodiment of the present invention；
Fig. 7 is a kind of one of driving process schematic of shift register provided in an embodiment of the present invention；
Fig. 8 is a kind of one of driving process schematic of shift register provided in an embodiment of the present invention；
Fig. 9 is a kind of one of driving process schematic of shift register provided in an embodiment of the present invention；
Figure 10 is a kind of one of driving process schematic of shift register provided in an embodiment of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
Unless otherwise defined, technical term or scientific term used in the embodiment of the present invention are should be belonging to the present invention
The ordinary meaning that personage in field with general technical ability is understood." first ", " second " used in the embodiment of the present invention with
And similar word is not offered as any sequence, quantity or importance, and be used only to distinguish different component parts." packet
Including " element or object that either the similar word such as "comprising" means to occur before the word cover and appear in the word presented hereinafter
Element perhaps object and its equivalent and be not excluded for other elements or object.The similar word such as " connection " or " connected "
It is not limited to physics or mechanical connection, but may include electrical connection, it is either direct or indirect.
"upper", "lower", "left", "right" etc. are only used for indicating relative positional relationship, after the absolute position for being described object changes, then should
Relative positional relationship may also correspondingly change.
The relevant technologies of the present invention provide a kind of shift register, as shown in Figure 1, the shift register uses 4T1C (4 crystalline substances
Body pipe and 1 capacitor), certainly it will be appreciated by those skilled in the art that arriving, in practice, there is also have the displacement with the 4T1C to post
Storage is a plurality of types of other shift registers, such as the shift register of 12T1C etc. that model improves；However,
At work (namely when being progressively scanned), signal output end Output's GOA circuit being made of these shift registers exists
Voltage can switch (such as from charging stage to output stage) between high level and low level at the time of different, so as to cause
The higher noise of amplitude is inspired on display panel, and then adverse effect is caused to display.
Based on this, the embodiment of the present invention provides a kind of shift register, as shown in Fig. 2, the shift register includes: input
Sub-circuit 101, resets son at the output output control output control of sub-circuit 1031, second of sub-circuit 102, first sub-circuit 1032
Circuit 104, drop-down sub-circuit 105, the first energy storage sub-circuit 106.
Wherein, input sub-circuit 101 and signal input part Input, second clock signal end CK2, the first control node A connect
It connects.The input sub-circuit 101 is used under the control of the voltage of second clock signal end CK2, inputs a signal into the electricity of end Input
Pressure is exported to the first control node A.
First output control sub-circuit 1031 is connect with the first clock signal terminal CK1, the second control node B.This is first defeated
Control sub-circuit 1031 is used under the control of the voltage of the first clock signal terminal CK1 out, by the electricity of the first clock signal terminal CK1
Pressure is exported to the second control node B.
Second output control sub-circuit 1032 and second clock signal end CK2, third clock signal terminal CK2, the second control
Node B, the V2 connection of second voltage end.The second output control sub-circuit 1032 is used in second clock signal end CK2 and third
Under the control of the voltage of clock signal terminal CK3, the medium voltage of second voltage end V2 is exported to the second control node B；Wherein,
The medium voltage of second voltage end V2 is greater than the low level voltage of each clock signal terminal, and is less than the high level of each clock signal terminal
Voltage.
Certainly, it will be appreciated by those skilled in the art that, each clock connected in same shift register is believed
Number end, such as the first clock signal terminal CK1, second clock signal end CK2, the clock signal in third clock signal terminal CK3 and
Speech, the high level voltage (high potential) in each clock signal be it is identical, low level voltage (low potential) is also identical；Its area
It is not only that, the successive timing of high and low level pulse is different.
In practice, in order to avoid circuit structure being separately provided come voltage between generating among the above, preferably, can be set this
Two voltage end V2 are AVDD voltage end.
Certainly, those skilled in the art is it is understood that for display panel, itself is provided with boost conversion
Device generates AVDD voltage to drive source drive IC, and the AVDD voltage just meets above-mentioned second voltage end V2 to voltage
The size requirements of (medium voltage)；It is preferred, therefore, that can directly using AVDD voltage end as above-mentioned second voltage end, thus
It can simplify circuit structure, reduce cost of manufacture.Signal, the high level voltage of clock signal is 25V in display panel, low
Level voltage is -10V, AVDD voltage 9V.
Output sub-circuit 102 is connect with the first control node A, the second control node B, signal output end Output.This is defeated
Sub-circuit 102 is used under the control of the voltage of the first control node A out, by the voltage output of the second control node B to signal
Output end Output.
Reset subcircuit 104 and reset signal end Reset, second clock signal end CK2, the first control node A, the first electricity
Pressure side VSS connection.The reset subcircuit 104 is used for the control in the voltage of reset signal end Reset and second clock signal end CK2
Under system, by the voltage output of first voltage end CK2 to the first control node A.
Pull down sub-circuit 105 and reset signal end Reset, second clock signal end CK2, signal output end Output, the
One voltage end VSS connection.The drop-down sub-circuit 105 is used for the voltage in reset signal end Reset and second clock signal end CK2
Control under, by the voltage output of first voltage end VSS to signal output end Output.
First energy storage sub-circuit 106 is connect with the first control node A and signal output end Output.First energy storage son electricity
Road 106 is for storing the voltage of the first control node A；The first energy storage sub-circuit 106 is also used to the first control section
Point A discharges.
In conclusion at work compared to shift register in the related technology, because signal output end can be in high potential
It, can be in the charging stage using shift register provided in an embodiment of the present invention for switching between low potential and generating noise
Between normal output stage (the first output stage, the second output stage), pass through the second output control sub-circuit and output
Sub-circuit, by medium voltage (current potential between the high potential and low potential) output at second voltage end to signal output end；
That is, the signal output end of the shift register in the present invention has one in output signal between low potential and high potential
The transition stage of a intermediate potential generates to reduce because signal output end switches directly between high potential and low potential
Noise.
The specific setting structure of above-mentioned each sub-circuit is described further below, but the setting structure of each sub-circuit is simultaneously
It is not limited to this.
In some embodiments, as shown in Fig. 2, input sub-circuit 101 may include the first transistor M1.Wherein, first
The grid of transistor M1 is connect with second clock signal end CK2, and the first pole of the first transistor M1 and signal input part Input connect
It connects, the second pole of the first transistor M1 is connect with the first control node A.
In some embodiments, as shown in Fig. 2, the first energy storage sub-circuit 106 may include first capacitor C1.Wherein,
The first end of one capacitor C1 is connect with the first control node A, and the second pole of first capacitor C1 is connect with signal output end Output.
In some embodiments, as shown in Fig. 2, output sub-circuit 102 may include second transistor M2.Wherein, second
The grid of transistor M2 is connect with the first control node A, and the first pole of second transistor M2 and the second control node B, second is brilliant
The second pole of body pipe M2 is connect with signal output end Output.
In some embodiments, as shown in Fig. 2, the first output control sub-circuit 1031 may include third transistor M3.
Wherein, the grid of third transistor M3 and the first pole are connect with the first clock signal terminal CK1, the second pole of third transistor M3 with
Second control node B connection.
In some embodiments, as shown in Fig. 2, second output control sub-circuit 1032 may include the 4th transistor M4 and
5th transistor M5.
Wherein, the grid of the 4th transistor M4 is connect with third clock signal terminal CK3, the first pole of the 4th transistor M4 with
The V2 connection of second voltage end, the second pole of the 4th transistor M4 is connect with the first pole of the 5th transistor M5；5th transistor M5
Grid connect with second clock signal end CK2, the second pole of the 5th transistor M5 is connect with the second control node B.
In some embodiments, as shown in Fig. 2, the reset subcircuit 104 may include the 6th transistor M6 and the 7th
Transistor M7.
Wherein, the grid of the 6th transistor M6 is connect with reset signal end Reset, the first pole of the 6th transistor M6 and the
One control node A connection, the second pole of the 6th transistor M6 is connect with the first pole of the 7th transistor M7；7th transistor M7's
Grid is connect with second clock signal end CK2, and the second pole of the 7th transistor M7 is connect with first voltage end VSS.
In some embodiments, as shown in Fig. 2, drop-down sub-circuit 105 may include the 8th transistor M8 and the 9th crystal
Pipe M9.
Wherein, the grid of the 8th transistor M8 is connect with reset signal end Reset, the first pole of the 8th transistor M8 and letter
Number output end Output connection, the second pole of the 8th transistor M8 is connect with the first pole of the 9th transistor M9；9th transistor
The grid of M9 is connect with second clock signal end CK2, and the second pole of the 9th transistor M9 is connect with first voltage end VSS.
It should be noted that above-mentioned transistor can be N-type transistor, or P-type transistor is (in the present invention preferably
Use N-type transistor)；It can be enhancement transistor, or depletion mode transistor；It can be brilliant using amorphous silicon membrane
Body pipe, polycrystalline SiTFT or amorphous-indium gallium zinc thin film transistor (TFT)；Also, the first pole of above-mentioned transistor can be with
For source electrode, second extremely can be the first of drain electrode or above-mentioned transistor extremely can be drain electrode, the second extremely source electrode, of the invention
This is not construed as limiting.
The embodiment of the present invention provides a kind of gate driving circuit, as shown in figure 3, the gate driving circuit includes by being located at surprise
The first driving unit 01 (corresponding bold portion) that several levels and successively cascade shift register as the aforementioned are constituted, Yi Jiyou
Positioned at even level and successively the second driving unit 02 (respective dashed part) that cascade shift register as the aforementioned is constituted.
Wherein, in the first driving unit 01:
The signal input part Input connection first of first odd level shift register RS1 originates signal end STV1, in addition to the
Other than one odd level shift register RS1, the signal input part Input and the odd level of any odd level shift register are shifted
The signal output end Output of the upper odd level shift register of register is connected；In addition to last odd level shift LD
Other than device, the reset signal end Reset of any odd level shift register and a upper odd level for the odd level shift register
The signal output end Output of shift register is connected；Reset signal end is separately provided in last odd level shift register
Reset, or connect with the first starting signal end STV1.
In the second driving unit 02:
Signal input part Input connection the second initial signal end STV2 of first even level shift register RS2, in addition to
Other than one even level shift register RS2, the signal input part Input and the even level of any even level shift register are shifted
The signal output end Output of the upper even level shift register of register is connected (for example, the second odd level shift LD
Device RS3 is connected with the signal output end Output of an odd level shift register RS1 thereon)；In addition to last even level moves
Other than bit register, the reset signal end Reset of any even level shift register and upper the one of the even level shift register
The signal output end Output of even level shift register is connected (for example, the second even level shift register RS4 and thereon one
The signal output end Output of even level shift register RS2 is connected)；Last even level shift register is separately provided multiple
Position signal end Reset, or connect with the second initial signal end STV2.
On this basis, as shown in figure 3, in the gate driving circuit, the level Four shift register being arranged successively is constituted
One shifting deposit unit 10 (such as first, second, third and fourth grade of shift register constitutes a shifting deposit unit), it is different
Shifting deposit unit 10 is made of different level Four shift registers.
In each shifting deposit unit 10:
The first clock signal terminal CK1, the second clock signal end CK2, of first order shift register (RS1, RS5 ...)
Three clock signal terminal CK3 respectively successively with the first system clock signal terminal ck1, third clock signal of system end ck3, the 4th system
Clock signal terminal ck4 connection.
The first clock signal terminal CK1, the second clock signal end CK2, of second level shift register (RS2, RS6 ...)
Three clock signal terminal CK3 respectively successively with second system clock signal terminal ck2, the 4th clock signal of system end ck4, the first system
Clock signal terminal ck1 connection.
The first clock signal terminal CK1, the second clock signal end CK2, of third level shift register (RS3, RS7 ...)
Three clock signal terminal CK3 respectively successively with third clock signal of system end ck3, the first system clock signal terminal ck1, second system
Clock signal terminal ck2 connection.
The first clock signal terminal CK1, the second clock signal end CK2, of fourth stage shift register (RS4, RS8 ...)
Three clock signal terminal CK3 respectively successively with the 4th clock signal of system end ck4, second system clock signal terminal ck2, third system
Clock signal terminal ck3 connection.
Since the gate driving circuit includes shift register as described above, there is the displacement provided with previous embodiment
The identical structure of register and beneficial effect.Since previous embodiment carries out the structure of shift register and beneficial effect
Detailed description, details are not described herein again.
The embodiment of the present invention also provides a kind of display device, including aforementioned gate driving circuit, equally includes shifting above-mentioned
Bit register has structure identical with the shift register that previous embodiment provides and beneficial effect.Due to previous embodiment
The structure of shift register and beneficial effect are described in detail, details are not described herein again.
It should be noted that in embodiments of the present invention, display device specifically at least may include liquid crystal display panel and
Organic LED display panel, the display device can be with are as follows: liquid crystal display panel, Electronic Paper, oled panel, mobile phone, plate
Any products or components having a display function such as computer, television set, display, laptop, Digital Frame, navigator.
The embodiment of the present invention also provides a kind of driving method of shift register as the aforementioned.
Signal, below with the gate driving circuit of shift register combination Fig. 3 of Fig. 2, (signal of 4 timing diagram of corresponding diagram
, it is the N=in level V the shift register RS5, i.e. Fig. 4 in the gate driving circuit of Fig. 3 with the shift register in Fig. 2
For 5, Output (N), Input (N), Reset (N), PU (N) are abbreviated as by following word segment and attached drawing respectively
Output,Input,Reset,PU)；In addition, below in conjunction with transistor on-off (refer to Fig. 6, Fig. 7, Fig. 8, Fig. 9, Figure 10,
" X " on middle transistor indicates that the transistor is in off state, does not have " X " to indicate that the transistor is on shape on transistor
State), which is described further.
Specifically, as shown in figure 5, the driving method may include:
Charging stage S1:
With reference to Fig. 6, under the control of the voltage from second clock signal end CK2, input sub-circuit 101 is opened, and will be believed
The voltage output of number input terminal Input is stored into the first storage sub-circuit 102 to the first control node A；Meanwhile
Sub-circuit 102 is exported under the control of the voltage of one control node A to open.
Specifically, with reference to Fig. 6 and Fig. 4, in charging stage S1, in the high level letter from second clock signal end CK2
Number control under, the first transistor M1 conducting, input a signal into end Input high level signal export to the first control node A,
And it stores into first capacitor C1；In addition, second transistor M2 is led under the control of the high level signal of the first control node A
It is logical.
In addition, being in conducting in charging stage S1, the 5th transistor M5, the 7th transistor M7, the 9th transistor M9
State；Third transistor M3, the 4th transistor M4, the 6th transistor M6, the 8th transistor M8 are in off state.
Intermediate output stage S2:
With reference to Fig. 7, under the control of the voltage from second clock signal end CK2, input sub-circuit 101 is kept it turning on,
It inputs a signal into and holds the voltage output of Input to the first control node A；Under the control of the voltage of the first control node A, output
Sub-circuit 102 is opened；Also, under the control of the voltage from second clock signal end CK2 and third clock signal terminal CK3,
Second output control sub-circuit 1032 is opened, and will be exported from the medium voltage of second voltage end V2 by exporting sub-circuit 102
To signal output end Output.
Specifically, with reference to Fig. 7 and Fig. 4, output stage S2 among this, in the height electricity from second clock signal end CK2
Under the control of ordinary mail number, the first transistor M1 is held on, and the high level signal for inputting a signal into end Input is exported to the first control
Node A processed；Under the control of the high level signal of the first control node A, second transistor M2 is held on；Also, it is coming from
Under the control of the high level signal of second clock signal end CK2 and third clock signal terminal CK3, the 4th transistor M4 and the 5th is brilliant
Body pipe M5 conducting, to exporting the medium voltage from second voltage end V2 to signal output end Output.
In addition, output stage S2 among this, third transistor M3, the 6th transistor M6, the 8th transistor M8 are in
Off state, the 7th transistor M7 and the 9th transistor M9 are on state.
First output stage S3:
With reference to Fig. 8, the first energy storage sub-circuit 107 discharges to the first control node A, in the voltage of the first control node A
Under control, output sub-circuit 102 is opened, and under the control of the voltage in the first clock signal terminal CK1, the first output control son electricity
Road 1031 is opened, and will pass through output sub-circuit 102 output to signal output end from the voltage of the first clock signal terminal CK1
Output。
Specifically, with reference to Fig. 8 and Fig. 4, first output stage S3, first capacitor C1 will be in charging stage S1 and centre
The high level signal stored in output stage S2 discharges (namely the first control node A charges) to the first control node A；From
And under the control of the high level signal in the first control node A, second transistor M2 conducting；And coming from the first clock signal
Under the control for holding the high level signal of CK1, third transistor M3 conducting, thus by the height electricity from the first clock signal terminal CK1
Ordinary mail number (as scanning signal) is exported to signal output end Output.
In addition, in first output stage S3, the first transistor M1, the 5th transistor M5, the 6th transistor M6, the 7th crystalline substance
Body pipe M7, the 8th transistor M8, the 9th transistor M9 are in off state；4th transistor M4 is in the conductive state.
Second output stage S4:
With reference to Fig. 9, the first energy storage sub-circuit 107 continues to discharge to the first control node A, in the electricity of the first control node A
Under the control of pressure, the first output control sub-circuit 1031 and output sub-circuit 102 are kept it turning on；And in the first clock signal terminal
The first output control sub-circuit 1031 is kept it turning under the control of the voltage of CK1, will be from the electricity of the first clock signal terminal CK1
Pressure holding is continuous to be exported to signal output end Output.
Specifically, with reference to Fig. 9 and Fig. 4, in second output stage S4, the 6th transistor M6 and the 8th transistor M8 by
The off state of one output stage S3 is switched to conducting or half on state；4th transistor M4 is led by the first output stage S3's
Logical state is switched to off state；Remaining transistor and the state consistency in the first output stage S3, details are not described herein again.
Reseting stage S5:
With reference to Figure 10 and Fig. 4, under the control of the voltage from reset signal end Reset and second clock signal end CK2,
Reset subcircuit 104 is opened, and the voltage output from first voltage end VSS to the first control node A is resetted；Meanwhile
Under the control of the voltage from reset signal end Reset and second clock signal end CK2, drop-down sub-circuit 105 is opened, in the future
It is resetted from the voltage output of first voltage end VSS to signal output end Output.
Specifically, in reseting stage S5, believing from reset signal end Reset and second clock with reference to Figure 10 and Fig. 4
Number end CK2 high level signal control under, the 6th transistor M6 and the 7th transistor M7 conducting, first voltage end will be come from
The low level signal of VSS, which is exported to the first control node A, to be resetted；Meanwhile when coming from reset signal end Reset and second
Under the control of the high level signal of clock signal end CK2, the 8th transistor M8 and the 9th transistor M9 conducting will come from first voltage
The low level signal of end VSS, which is exported to signal output end Output, to be resetted.
In addition, in reseting stage S5, the first transistor M1, second transistor M2, third transistor M3, the 4th transistor
M4 is in off state, and the 5th transistor M5 is in the conductive state.
The switching process of transistor is the first voltage end using all transistors as N-type transistor in above embodiments
VSS is the explanation that carries out for low level voltage end.When all transistors are p-type, need to first voltage end and Fig. 4
In each control signal overturn.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain
Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.
Claims (10)
1. a kind of shift register characterized by comprising input sub-circuit, output sub-circuit, reset subcircuit, lower rock
Circuit, the first output control sub-circuit, the second output control sub-circuit, the first energy storage sub-circuit；
The input sub-circuit is connect with signal input part, second clock signal end, the first control node, for described second
Under the control of the voltage of clock signal terminal, by the voltage output of the signal input part to first control node；
The first output control sub-circuit is connect with the first clock signal terminal, the second control node, at described first
Under the control of the voltage of clock signal end, by the voltage output of first clock signal terminal to the second control node；
The second output control sub-circuit and the second clock signal end, third clock signal terminal, second control save
Point, the connection of second voltage end, under the control of the second clock signal end and the voltage of the third clock signal terminal,
The medium voltage at the second voltage end is exported to second control node；Wherein, the intermediate electricity at the second voltage end
Pressure is greater than the low level voltage of each clock signal terminal, and is less than the high level voltage of each clock signal terminal；
The output sub-circuit is connect with first control node, second control node, signal output end, in institute
Under the control for stating the voltage of the first control node, by the voltage output of second control node to the signal output end；
The reset subcircuit and reset signal end, the second clock signal end, first control node, first voltage end
Connection, under the control of the reset signal end and the voltage of the second clock signal end, by the first voltage end
Voltage output to first control node；
The drop-down sub-circuit and the reset signal end, the second clock signal end, the signal output end, described first
Voltage end connection, under the control of the reset signal end and the voltage of the second clock signal end, by described first
The voltage output of voltage end is to the signal output end；
The first energy storage sub-circuit is connect with first control node and the signal output end, for controlling described first
The voltage of node processed is stored, and is also used to discharge to first control node.
2. shift register according to claim 1, which is characterized in that the input sub-circuit includes the first transistor；
The grid of the first transistor is connect with the second clock signal end, and the first pole is connect with the signal input part, and second
Pole is connect with first control node；
The first energy storage sub-circuit includes first capacitor；The first end of the first capacitor and first control node connect
It connects, the second pole is connect with the signal output end.
3. shift register according to claim 1 or 2, which is characterized in that
The output sub-circuit includes second transistor；The grid of the second transistor is connect with first control node,
First pole and second control node, the second pole is connect with the signal output end.
4. shift register according to claim 1 or 2, which is characterized in that
The first output control sub-circuit includes third transistor；The grid of the third transistor and the first pole and described the
The connection of one clock signal terminal, the second pole is connect with second control node；
The second output control sub-circuit includes the 4th transistor and the 5th transistor；The grid of 4th transistor and institute
The connection of third clock signal terminal is stated, the first pole is connect with the second voltage end, the second pole and the first of the 5th transistor
Pole connection；The grid of 5th transistor is connect with the second clock signal end, the second pole and second control node
Connection.
5. shift register according to claim 1 or 2, which is characterized in that
The reset subcircuit includes the 6th transistor and the 7th transistor；
The grid of 6th transistor is connect with the reset signal end, and the first pole is connect with first control node, the
Two poles are connect with the first pole of the 7th transistor；The grid and the second clock signal end of 7th transistor connect
It connects, the second pole is connect with the first voltage end.
6. shift register according to claim 1 or 2, which is characterized in that
The drop-down sub-circuit includes the 8th transistor and the 9th transistor；
The grid of 8th transistor is connect with the reset signal end, and the first pole is connect with the signal output end, and second
Pole is connect with the first pole of the 9th transistor；The grid of 9th transistor is connect with the second clock signal end,
Second pole is connect with the first voltage end.
7. shift register according to claim 1, which is characterized in that the second voltage end is AVDD voltage end.
8. a kind of gate driving circuit, which is characterized in that including by being located at odd level and successively cascade such as claim 1-7
The first driving unit that described in any item shift registers are constituted, and by being located at even level and successively cascade such as right
It is required that the second driving unit that the described in any item shift registers of 1-7 are constituted；
In first driving unit, signal input part connection the first starting signal end of the first odd level shift register,
Other than the first odd level shift register, the signal input part and the odd level of any odd level shift register are moved
The signal output end of the upper odd level shift register of bit register is connected；In addition to last odd level shift register with
Outside, the upper odd level shift register at the reset signal end of any odd level shift register and the odd level shift register
Signal output end be connected；Last described odd level shift register is separately provided reset signal end, or with described
One starting signal end connection；
In second driving unit, the signal input part of the first even level shift register connects the second initial signal end,
Other than the first even level shift register, the signal input part and the even level of any even level shift register are moved
The signal output end of the upper even level shift register of bit register is connected；In addition to last even level shift register with
Outside, the upper even level shift register at the reset signal end of any even level shift register and the even level shift register
Signal output end be connected；Last described even level shift register is separately provided reset signal end, or with described
The connection of two initial signal ends；
In the gate driving circuit, the level Four shift register being arranged successively constitutes a shifting deposit unit, different shiftings
Position deposit unit is made of different level Four shift registers；
In each shifting deposit unit:
First clock signal terminal of first order shift register, second clock signal end, third clock signal terminal respectively successively with
The first system clock signal terminal, third clock signal of system end, the connection of the 4th clock signal of system end；
First clock signal terminal of second level shift register, second clock signal end, third clock signal terminal respectively successively with
Second system clock signal terminal, the 4th clock signal of system end, the connection of the first system clock signal terminal；
First clock signal terminal of third level shift register, second clock signal end, third clock signal terminal respectively successively with
Third clock signal of system end, the first system clock signal terminal, the connection of second system clock signal terminal；
First clock signal terminal of fourth stage shift register, second clock signal end, third clock signal terminal respectively successively with
4th clock signal of system end, second system clock signal terminal, the connection of third clock signal of system end.
9. a kind of display device, which is characterized in that including gate driving circuit according to any one of claims 8.
10. a kind of driving method of such as described in any item shift registers of claim 1-7 characterized by comprising
Charging stage:
Under the control of the voltage from the second clock signal end, the input sub-circuit is opened, and the signal is inputted
The voltage output at end is stored into the first storage sub-circuit to first control node；
Intermediate output stage:
Under the control of the voltage from the second clock signal end, the input sub-circuit is kept it turning on, by the signal
The voltage output of input terminal is to first control node；Under the control of the voltage of first control node, the output
Sub-circuit is opened；Also, under the control of the voltage from the second clock signal end and the third clock signal terminal, institute
It states the second output control sub-circuit to open, will be exported from the medium voltage at the second voltage end by the output sub-circuit
To the signal output end；
First output stage:
The first energy storage sub-circuit discharges to first control node, in the control of the voltage of first control node
Under, the output sub-circuit is opened, and the first output control under the control of the voltage in first clock signal terminal
Circuit is opened, and the voltage from first clock signal terminal is exported by the output sub-circuit to the signal and is exported
End；
Second output stage:
The first energy storage sub-circuit discharges to first control node, in the control of the voltage of first control node
Under, the output sub-circuit is kept it turning on, the first output control under the control of the voltage of first clock signal terminal
Sub-circuit is kept it turning on, and the voltage from first clock signal terminal is persistently exported to the signal output end；
Reseting stage:
Under the control of the voltage from the reset signal end and the second clock signal end, the reset subcircuit is opened
It opens, the voltage output from the first voltage end to first control node is resetted；
Under the control of the voltage from the reset signal end and the second clock signal end, the drop-down sub-circuit is opened
It opens, the voltage output from the first voltage end to the signal output end is resetted.
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