CN109683523B - Accelerator control method and system based on programmable gate array FPGA - Google Patents
Accelerator control method and system based on programmable gate array FPGA Download PDFInfo
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- G05B19/00—Programme-control systems
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- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
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Abstract
The embodiment of the invention discloses an accelerator control method and system based on a programmable gate array FPGA, wherein the system comprises the following steps: an input circuit; an output circuit in signal connection with the input circuit; the optical fiber trigger output circuit is in signal connection with the output circuit; the power supply is in signal connection with the optical fiber trigger output circuit to provide variable voltage; and the field programmable gate array circuit is in signal connection with the light trigger output circuit so as to control the time sequence of the trigger time sequence control circuit for receiving synchronous signal input, magnetron trigger enable, electron gun trigger enable, high-voltage discharge and ultra-low dose mode. The embodiment of the invention has the beneficial effects that: the FPGA uses special logic processing hardware, the speed is high, and all processing paths are parallel; the FPGA can be reconfigured, the same hardware can be reconstructed according to different tasks, and the flexibility of the use mode is nearly infinite; the FPGA can configure the number and functions of I/O according to the needs.
Description
Technical Field
The invention relates to the technical field of accelerators, in particular to an accelerator control method and system based on a programmable gate array (FPGA).
Background
The working mode of the accelerator is pulse type, different time sequence trigger drive parts and functional components work cooperatively, in the traditional accelerator, a time sequence trigger circuit consists of discrete devices such as a resistance-capacitance chip and a digital logic chip, the precision is low, the interference is easy to occur, and the nanosecond time sequence fine adjustment is difficult to realize. And the circuit cannot add new functionality once it is determined.
Disclosure of Invention
The invention aims to provide an accelerator control method and system based on a programmable gate array (FPGA), which are used for solving the problems of low precision, high possibility of interference and poor expansibility of the conventional time sequence control.
In order to achieve the above object, an embodiment of the present invention discloses an accelerator control method based on a programmable gate array FPGA, which receives a timing sequence of a synchronization signal input, a magnetron trigger enable, an electron gun trigger enable, a high-voltage discharge, and an ultra-low dose mode through a field programmable gate array control trigger timing control circuit to output an IGBT trigger signal, an electron gun trigger signal, and an electron gun pressure mode control signal.
Optionally, the IGBT trigger signal is output from 10 or 12 optical fiber output ports.
Optionally, the electron gun trigger signal and the electron gun pressure mode control signal are both output by a switching value output terminal.
On the other hand, the embodiment of the invention discloses an accelerator control system based on a programmable gate array FPGA, which comprises the following components:
the input end of the input circuit adopts optical coupling electric isolation;
the output circuit is in signal connection with the input circuit and is used for outputting an IGBT (insulated gate bipolar transistor) trigger signal, an electron gun trigger signal and an electron gun pressure mode control signal;
the optical fiber triggering output circuit is in signal connection with the output circuit, 1 path of magnetron triggering pulse is divided into a plurality of paths of pulses according to the time sequence requirement in the field programmable gate array circuit, the minimum time sequence adjustment precision among the pulses is Xns, and the time sequence relation among the plurality of paths of triggering pulses is adjusted to change the rising front edge of the magnetron pulse current and the flatness of the pulse current;
the power supply is in signal connection with the optical fiber trigger output circuit to provide variable voltage;
and the field programmable gate array circuit is in signal connection with the light trigger output circuit so as to control the time sequence of the trigger time sequence control circuit for receiving synchronous signal input, magnetron trigger enable, electron gun trigger enable, high-voltage discharge and ultra-low dose mode.
Optionally, the program in the field programmable gate array circuit is burned through JTAG and the burning process is monitored.
Optionally, the control system further includes a dial switch in signal connection with the field programmable gate array circuit, so as to be used for setting hardware of the board card. Such as magnetron trigger pulse width, magnetron trigger and electron gun trigger timing relationship, 12-way trigger timing relationship setting, high and low energy parameter setting, local dial parameter or communication setting parameter, etc., and once the dial position is determined in debugging, the dial position can not be changed. If not, the system is out of synchronization, and if not, the hardware is damaged by changing the system power.
Optionally, an RS485 soft core is embedded in the field programmable gate array circuit, where the MAX485CSA is an RS485 interface chip, communication is implemented in a half-duplex manner, where pins 2 and 3 of the U6 are receive or transmit enable controls, enable logics inside the chip are opposite, it is ensured that only one-way data exists on a communication line at a certain time, pin 41 is a receive and transmit port, and U4 and U5 are dual-channel high-speed optical intervals, and signal isolation and level conversion are performed between the field programmable gate array circuit and the MAX 485.
Optionally, the input terminal of the input circuit includes:
TrigIn +, an external trigger input, enabled in the linear modulator mode;
energy +, external Energy indication input, Energy indication in the linear modulator mode, and synchronous signal generation in the solid modulator mode while Energy indication;
TrigENA +, the magnetron triggers and allows, the high level only produces the IGBT trigger output;
an ExIn + discharge control input which generates a discharge trigger when it changes from a high level to a low level; when the accelerator does not have a high-voltage condition, the modulator direct-current charging time sequence trigger unit outputs 30-second trigger pulses on 12 paths of optical fibers, and the electric quantity on the energy storage capacitor CS in the solid-state switch unit is released, so that possible damage caused by factors such as cover opening maintenance and the like is avoided;
LIN1, electron gun triggered enable, which when high generates an electron gun trigger output;
LIN2, electron gun non-ultra low dose mode input, when it is high, the electron gun power supply outputs a non-ultra low dose mode gun pressure, otherwise outputs an ultra low dose mode gun pressure.
Optionally, the output terminal of the output circuit includes:
LO01, an electron gun power supply is triggered, the sequential relation between the electron gun power supply and 12-path optical fiber triggering is determined according to a set value after time sequence adjustment in the FPGA, and the electron gun power supply is output to a modulator;
LO02 and LO03, the electron gun power supply output voltage is selected, 2 bit outputs can be combined into 4 states, and the 4 states are connected to the electron gun power supply input terminal of the modulator, and correspond to 4 different electron gun output voltages;
LO04, frequency readback, output to X-ray head control panel input for sensing system beam-out frequency.
The embodiment of the invention has the following advantages:
FPGA (field programmable gate array) uses logic processing special hardware, the speed is high, and all processing paths are parallel; the FPGA can be reconfigured, the same hardware can be reconstructed according to different tasks, and the flexibility of the use mode is nearly infinite; the FPGA can configure the number and functions of I/O according to the needs;
the trigger time sequence is controlled by the field programmable gate array, namely the time sequence of receiving synchronous signal input, magnetron trigger enable, electron gun trigger enable, high-voltage discharge and ultra-low dosage mode is controlled to output IGBT trigger signals, electron gun trigger signals and electron gun pressure mode control signals, so that the time sequence control precision is high, the interference is not easy to occur, and the expansibility is high; the system works stably and reliably.
Drawings
FIG. 1 is a circuit diagram of an embodiment of an input circuit;
FIG. 2 is a circuit diagram of an embodiment of an output circuit;
FIG. 3 is a circuit diagram of an embodiment of a fiber optic trigger output circuit;
FIG. 4 is a signal diagram of a first arrangement of one embodiment of a dip switch;
FIG. 5 is a signal diagram of a second configuration of one embodiment of the dip switch;
fig. 6 is a circuit diagram of an embodiment of an RS485 communication interface.
Detailed Description
The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention.
The embodiment of the invention discloses an accelerator control method based on a programmable gate array FPGA (field programmable gate array). A field programmable gate array control trigger time sequence control circuit receives the time sequences of synchronous signal input, magnetron trigger enable, electron gun trigger enable, high-voltage discharge and ultra-low dose mode to output an IGBT (insulated gate bipolar transistor) trigger signal, an electron gun trigger signal and an electron gun pressure mode control signal.
The Field Programmable Gate Array (FPGA) is a product of further development based on Programmable devices such as PAL, GAL, CPLD, etc. The circuit is a semi-custom circuit in the field of Application Specific Integrated Circuits (ASIC), not only overcomes the defects of the custom circuit, but also overcomes the defect that the number of gate circuits of the original programmable device is limited.
The trigger time sequence is controlled by the field programmable gate array, namely the time sequence of receiving synchronous signal input, magnetron trigger enable, electron gun trigger enable, high-voltage discharge and ultra-low dosage mode is controlled to output IGBT trigger signals, electron gun trigger signals and electron gun pressure mode control signals, so that the time sequence control precision is high, the interference is not easy to occur, and the expansibility is high; the system works stably and reliably.
The system selects Fusion series FPGA of Actel company. The series of FPGA is based on a Flash architecture, has power-down non-volatility, and does not need to configure chip configuration data (which is different from the FPGA based on the SRAM); in addition, the structure is high in reliability based on a Flash structure relative to an SRAM structure, because high-energy ions in the atmosphere cause state change in the process of colliding with transistors of the SRAM structure, errors are caused, and failure is caused, while the change of the transistor state of the Flash structure needs a certain voltage, and general high-energy ions cannot reach the level, so that the structure is suitable for application in accelerator occasions.
Specifically, the IGBT trigger signal is output by 10 or 12 optical fiber output ports.
Specifically, the electron gun trigger signal and the electron gun pressure mode control signal are both output by a switching value output end.
On the other hand, the embodiment of the invention discloses an accelerator control system based on a programmable gate array FPGA, which comprises the following components:
the input end of the input circuit adopts optical coupling electric isolation;
the output circuit is in signal connection with the input circuit and is used for outputting an IGBT (insulated gate bipolar transistor) trigger signal, an electron gun trigger signal and an electron gun pressure mode control signal;
the optical fiber triggering output circuit is in signal connection with the output circuit, 1 path of magnetron triggering pulse is divided into multiple paths (such as 12 paths) of pulses according to the time sequence requirement in the field programmable gate array circuit, the minimum time sequence adjustment precision among the pulses is Xns (such as X is 20), and the time sequence relation among the multiple paths of triggering pulses is adjusted to change the rising front edge of the magnetron pulse current and the flatness of the pulse current;
the power supply is in signal connection with the optical fiber trigger output circuit to provide variable voltage, the power supply is divided into 4 parts, and 1-way DC/DC changes 24VDC into 5 VDC; 2 DC/DC converts 5V into 3.3V to supply power I/O for FPGA; 5V is converted into 1.5V by the 3-path DC/DC to supply power for the FPGA core; the 4 paths of DC/DC are 5V to supply power to the RS485 communication circuit;
and the field programmable gate array circuit is in signal connection with the light trigger output circuit so as to control the time sequence of the trigger time sequence control circuit for receiving synchronous signal input, magnetron trigger enable, electron gun trigger enable, high-voltage discharge and ultra-low dose mode.
In addition, the program in the field programmable gate array circuit is burned through JTAG and the burning process is monitored.
The control system also comprises a dial switch in signal connection with the field programmable gate array circuit, so as to be used for hardware setting of the board card. Such as magnetron trigger pulse width, magnetron trigger and electron gun trigger timing relationship, 12-way trigger timing relationship setting, high and low energy parameter setting, local dial parameter or communication setting parameter, etc., and once the dial position is determined in debugging, the dial position can not be changed. If not, the system is out of synchronization, and if not, the hardware is damaged by changing the system power.
The dial is used for hardware setting of the board card, such as magnetron trigger pulse width, magnetron trigger and electron gun trigger timing relation, 12-way trigger timing relation setting, high and low energy parameter setting, local dial parameter or communication setting parameter using and the like, and once the dial position is determined in debugging, the dial position cannot be changed. If not, the system is out of synchronization, and if not, the hardware is damaged by changing the system power.
Tables 2-6S 1/S2/S3 Dial Definitions
(note: wherein 1, 5 of the switch are high, 4, 8 are low)
S1[5:8 ]: trigger pulse width setting. If the 4 bits are all 0, the basic trigger width is 2.0us, the minimum step is 0.2us, and the maximum pulse width is 5.0 us;
s1[1:4 ]: the solid-state switch 12-way trigger pulse time delay setting. The delay opening time of 2 adjacent trigger pulses is indicated, if the 4 bits are all 0, the opening is free of delay, and if the 4 bits are all 1 (maximum delay), the latter pulse is opened 0.14us after the delay.
Examples are: set S1[5:8] ═ 1010 (pulse width 4us) and S1[1:4] ═ 0000 (no delay), see fig. 4.
② setting S1[5:8] ═ 1010 (pulse width 4us), S1[1:4] ═ 0010 (inter-pulse delay 0.02us), see FIG. 5.
S2[5:8 ]: gun magnetic trigger pulse delay setting 1. The magnetic trigger pulse is set relative to the gun trigger delay, 4-bit dialing is carried out, the minimum delay is 0.2us, and the maximum delay is 3 us.
S2[1:4 ]: gun magnetic trigger pulse delay setting 2. The magnetic trigger pulse is set relative to the gun trigger delay, 4-bit dialing is carried out, the minimum delay is 0.2us, and the maximum delay is 3 us.
And the total delay value is gun magnetic trigger pulse delay setting 1+ gun magnetic trigger pulse delay setting 2.
S3[1 ]: and selecting a parameter channel. When the switch is ON, hardware parameters are selected (the level dial switch is effective), and when the switch is OFF, the parameters are communication parameters, including time delay, pulse width and working mode.
S3[2]: triggering source selection. When ON, an inner trigger is selected.
S3[3 ]: and selecting hardware energy. The function is played when the hardware parameter is selected, and the function is dual-energy when the hardware parameter is ON.
S3[4 ]: the hardware triggers the mode selection. And functions when selecting hardware parameters, and is a double trigger source when the hardware parameters are ON.
(linear modulator mode) and OFF, for a one-trigger source (solid state modulator mode).
In addition, the field programmable gate array circuit is embedded with an RS485 soft core, referring to FIG. 6, wherein MAX485CSA is an RS485 interface chip, communication is realized in a half-duplex mode, wherein pins 2 and 3 of U6 are enable control of receiving or sending, enable logics inside the chip are opposite, only one-way data is ensured to exist on a communication line at a certain moment, pins 41 are receiving and sending ports, U4 and U5 are dual-channel high-speed optical isolation, and signal isolation and level conversion are realized between the field programmable gate array circuit and MAX 485. Because the relevant parameters are set through the dial switch, the communication setting is not needed.
Referring to fig. 1 to 6, the input level is defined as 24VDC in the accelerator system, and the unit has 6 inputs in total, and the input terminals are electrically isolated by opto-couplers for the purpose of improving interference resistance and level conversion, which are defined as follows:
TrigIn +, external trigger input, enabled in linear modulator (dual trigger source) mode (the system is useless);
energy + external Energy indication input, which is Energy indication in a linear modulator (double trigger source) mode, and simultaneously generates a synchronous signal (the system is trigger input) while being Energy indication in a solid modulator mode;
TrigENA +, the magnetron triggers and allows, the high level only produces the IGBT trigger output;
an ExIn + discharge control input which generates a discharge trigger when it changes from a high level to a low level; when the accelerator does not have a high-voltage condition, the modulator direct-current charging time sequence trigger unit outputs 30-second trigger pulses on 12 paths of optical fibers, and the electric quantity on the energy storage capacitor CS in the solid-state switch unit is released, so that possible damage caused by factors such as cover opening maintenance and the like is avoided;
LIN1, electron gun triggered enable, which when high generates an electron gun trigger output (the system is always high);
LIN2, electron gun non-ultra low dose mode input, when it is high, the electron gun power supply outputs non-ultra low dose mode gun pressure, otherwise outputs ultra low dose mode gun pressure (the system is always high).
In addition, referring to fig. 2, the output circuit includes:
LO01, an electron gun power supply is triggered, the sequential relation between the electron gun power supply and 12-path optical fiber triggering is determined according to a set value after time sequence adjustment in the FPGA, and the electron gun power supply is output to a modulator;
LO02 and LO03, the electron gun power supply output voltage is selected, 2 bit outputs can be combined into 4 states, and the 4 states are connected to the electron gun power supply input terminal of the modulator, and correspond to 4 different electron gun output voltages;
LO04, frequency readback, output to X-ray head control panel input for sensing system beam-out frequency.
Although the invention has been described in detail above with reference to a general description and specific examples, it will be apparent to one skilled in the art that modifications or improvements may be made thereto based on the invention. Accordingly, such modifications and improvements are intended to be within the scope of the invention as claimed.
Claims (9)
1. An accelerator control method based on a programmable gate array FPGA is characterized in that a field programmable gate array control trigger time sequence control circuit based on a Flash framework receives time sequences of synchronous signal input, magnetron trigger enable, electron gun trigger enable, high-voltage discharge and an ultra-low dose mode so as to output an IGBT trigger signal, an electron gun trigger signal and an electron gun pressure mode control signal; dividing 1 path of magnetron trigger pulse into multiple paths of pulses according to the time sequence requirement in the FPGA circuit, adjusting the minimum time sequence between the pulses to Xns, and adjusting the time sequence relation between the multiple paths of trigger pulses to change the rising front edge of the magnetron pulse current and the flatness of the pulse current.
2. The accelerator control method based on the FPGA of claim 1, wherein the IGBT trigger signal is output by 10 or 12 fiber output ports.
3. The accelerator control method based on the FPGA of claim 1, wherein the electron gun trigger signal and the electron gun pressure mode control signal are both output from a switching value output terminal.
4. A system for executing the accelerator control method based on a programmable gate array FGPA according to claim 1, characterized by comprising:
the input end of the input circuit adopts optical coupling electric isolation;
the output circuit is in signal connection with the input circuit and is used for outputting an IGBT (insulated gate bipolar transistor) trigger signal, an electron gun trigger signal and an electron gun pressure mode control signal;
the optical fiber triggering output circuit is in signal connection with the output circuit, 1 path of magnetron triggering pulses are divided into a plurality of paths of pulses according to the time sequence requirement in a field programmable gate array circuit based on a Flash framework, the minimum time sequence adjustment precision among the pulses is Xns, and the time sequence relation among the plurality of paths of triggering pulses is adjusted to change the rising front edge of the magnetron pulse current and the flatness of the pulse current;
the power supply is in signal connection with the optical fiber trigger output circuit to provide variable voltage;
and the field programmable gate array circuit is in signal connection with the light trigger output circuit so as to control the time sequence of the trigger time sequence control circuit for receiving synchronous signal input, magnetron trigger enable, electron gun trigger enable, high-voltage discharge and ultra-low dose mode.
5. The accelerator control system based on the programmable gate array FPGA of claim 4, characterized in that the programming in the field programmable gate array circuit is burned and the burning process is monitored through JTAG.
6. The accelerator control system based on the FPGA of claim 5, further comprising a dial switch in signal connection with the FPGA circuit for hardware setting of the board.
7. The accelerator control system based on the FPGA of claim 6, wherein the FPGA circuit is embedded with an RS485 soft core, wherein the MAX485CSA is an RS485 interface chip, the communication is realized in a half-duplex manner, wherein pins 2 and 3 of U6 are the enable control of receiving or transmitting, the enable logics inside the chip are opposite, only one-way data is ensured to exist on the communication line at a certain moment, pins 41 are the receiving and transmitting ports, U4 and U5 are two-channel high-speed optical gaps, and the FPGA circuit and the MAX485 circuit play roles of signal isolation and level conversion.
8. The accelerator control system based on the programmable gate array FPGA of claim 5, wherein the input end of the input circuit comprises:
TrigIn +, an external trigger input, enabled in the linear modulator mode;
energy +, external Energy indication input, Energy indication in the linear modulator mode, and synchronous signal generation in the solid modulator mode while Energy indication;
TrigENA +, the magnetron triggers and allows, the high level only produces the IGBT trigger output;
an ExIn + discharge control input which generates a discharge trigger when it changes from a high level to a low level; when the accelerator does not have a high-voltage condition, the modulator direct-current charging time sequence trigger unit outputs 30-second trigger pulses on 12 paths of optical fibers, and the electric quantity on the energy storage capacitor CS in the solid-state switch unit is released, so that possible damage caused by factors such as cover opening maintenance and the like is avoided;
LIN1, electron gun triggered enable, which when high generates an electron gun trigger output;
LIN2, electron gun non-ultra low dose mode input, when it is high, the electron gun power supply outputs a non-ultra low dose mode gun pressure, otherwise outputs an ultra low dose mode gun pressure.
9. The accelerator control system based on the programmable gate array FPGA of claim 8, wherein an output of said output circuit comprises:
LO01, an electron gun power supply is triggered, the sequential relation between the electron gun power supply and 12-path optical fiber triggering is determined according to a set value after time sequence adjustment in the FPGA, and the electron gun power supply is output to a modulator;
LO02 and LO03, the electron gun power supply output voltage is selected, 2 bit outputs can be combined into 4 states, and the 4 states are connected to the electron gun power supply input terminal of the modulator, and correspond to 4 different electron gun output voltages;
LO04, frequency readback, output to X-ray head control panel input for sensing system beam-out frequency.
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| CN100589676C (en) * | 2005-12-31 | 2010-02-10 | 清华大学 | A kind of electron linear accelerator and using method thereof |
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