CN109656304B - Current generating circuit and Hall circuit thereof - Google Patents

Current generating circuit and Hall circuit thereof Download PDF

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Publication number
CN109656304B
CN109656304B CN201811523462.6A CN201811523462A CN109656304B CN 109656304 B CN109656304 B CN 109656304B CN 201811523462 A CN201811523462 A CN 201811523462A CN 109656304 B CN109656304 B CN 109656304B
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output
circuit
current
clock signal
voltage
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CN109656304A (en
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杨志江
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Chengdu Monolithic Power Systems Co Ltd
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Chengdu Monolithic Power Systems Co Ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals

Abstract

A current generating circuit is disclosed. The current generation circuit includes a reference clock generation circuit, a phase-locked loop circuit, and an output circuit. The reference clock generation circuit provides a reference clock signal, wherein the frequency of the reference clock signal is associated with a reference voltage. The phase-locked loop circuit outputs a calibration clock signal, receives the reference clock signal and the calibration clock signal output by the phase-locked loop circuit, and adjusts the calibration clock signal according to a phase difference between the calibration clock signal and the reference clock signal so that the phase difference between the calibration clock signal and the reference clock signal is reduced. The output circuit is coupled to the phase-locked loop circuit, and the phase-locked loop circuit controls the output circuit to enable the output circuit to generate an output current according to a phase difference between the calibration clock signal and the reference clock signal. The current generation circuit provided by the invention can generate output current proportional to the reference voltage and can be applied to circuits as required.

Description

Current generating circuit and Hall circuit thereof
Technical Field
The present invention relates to an electronic circuit, and more particularly, to a current generation circuit and a hall circuit.
Background
In some applications, such as some hall circuits, it is desirable to generate a current proportional to a reference voltage. For example, for a typical PTAT (proportional to absolute temperature) current generating circuit, the PTAT current generated by the circuit is related to absolute temperature and is not related to a reference voltage. However, for certain applications, such as for example, for certain hall circuit bias currents, it is desirable that the PTAT current associated with the reference voltage varies with, e.g., is proportional to, e.g., proportional to, the reference voltage.
Therefore, it is desirable to provide a current generation circuit that correlates an output current to a reference voltage.
Disclosure of Invention
According to an aspect of an embodiment of the present invention, there is provided a current generation circuit including: a reference clock generating circuit providing a reference clock signal, wherein a frequency of the reference clock signal is associated with a reference voltage; the phase-locked loop circuit outputs a calibration clock signal, receives the reference clock signal and the calibration clock signal output by the phase-locked loop circuit, and adjusts the calibration clock signal according to the phase difference between the calibration clock signal and the reference clock signal so as to reduce the phase difference between the calibration clock signal and the reference clock signal; and an output circuit coupled to the phase-locked loop circuit, the phase-locked loop circuit controlling the output circuit such that the output circuit generates an output current according to a phase difference between the calibration clock signal and the reference clock signal.
According to another aspect of the embodiments of the present invention, there is provided a hall circuit including: a current generating circuit generating an output current; the Hall sensor is coupled to the current generating circuit to receive the output current, and generates a Hall voltage according to the output current; and the amplifying system is coupled to the Hall sensor to receive the Hall voltage and generate an output voltage according to the Hall voltage. Wherein, the current generation circuit includes: a reference clock generating circuit providing a reference clock signal, wherein a frequency of the reference clock signal is associated with a reference voltage; the phase-locked loop circuit outputs a calibration clock signal, receives the reference clock signal and the calibration clock signal output by the phase-locked loop circuit, and adjusts the calibration clock signal according to the phase difference between the calibration clock signal and the reference clock signal so as to reduce the phase difference between the calibration clock signal and the reference clock signal; and an output circuit coupled to the phase-locked loop circuit, the phase-locked loop circuit controlling the output circuit such that the output circuit generates an output current according to a phase difference between the calibration clock signal and the reference clock signal.
The current generation circuit provided by the embodiment of the invention can generate the current proportional to the reference voltage, and can be applied to circuits such as Hall circuits which are required.
Drawings
Fig. 1 shows a current generation circuit 100 according to an embodiment of the invention.
FIG. 2 illustrates a reference clock generating circuit 200 used as the reference clock generating circuit 101 of FIG. 1 according to an embodiment of the present invention.
Fig. 3 illustrates a phase-locked loop circuit 300 for use as the phase-locked loop circuit 102 of fig. 1, in accordance with one embodiment of the present invention.
Fig. 4 shows a voltage controlled oscillator circuit 400 for the voltage controlled oscillator circuit VCO of fig. 3, according to an embodiment of the invention.
Fig. 5 shows an output circuit 500 according to an embodiment of the invention.
FIG. 6 shows a current generation circuit 600 that combines the circuits of FIGS. 2-5.
Fig. 7 is a graph showing a simulation result of the current generation circuit 600 shown in fig. 6.
Fig. 8 shows a hall circuit 800 according to an embodiment of the invention.
Detailed Description
Specific embodiments of the present invention will be described in detail below, and it should be noted that the embodiments described herein are only for illustration and are not intended to limit the present invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that: it is not necessary to employ these specific details to practice the present invention. In other instances, well-known circuits, materials, or methods have not been described in detail in order to avoid obscuring the present invention.
Throughout the specification, reference to "one embodiment," "an embodiment," "one example," or "an example" means: the particular features, structures, or characteristics described in connection with the embodiment or example are included in at least one embodiment of the invention. Thus, the appearances of the phrases "in one embodiment," "in an embodiment," "one example" or "an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combination and/or sub-combination in one or more embodiments or examples. Further, those of ordinary skill in the art will appreciate that the illustrations provided herein are for illustrative purposes and are not necessarily drawn to scale. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Like reference numerals refer to like elements. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Fig. 1 shows a current generation circuit 100 according to an embodiment of the invention. As shown in fig. 1, the current generation circuit 100 illustratively includes a reference clock generation circuit 101, a phase-locked loop circuit 102, and an output circuit 103. The reference clock generation circuit 101 provides a reference clock signal CLK1, wherein the reference clock signal CLK1 has a frequency fCLK1And wherein the frequency fCLK1And a reference voltage VREFAssociated, i.e. frequency fCLK1With reference to a voltage VREFMay vary. More specifically, the frequency fCLK1And a reference voltage VREFIs in direct proportion.
FIG. 2 illustrates a reference clock generating circuit 200 used as the reference clock generating circuit 101 of FIG. 1 according to an embodiment of the present invention. As shown in FIG. 2, the reference clock generation circuit 200 illustratively includes a reference current source CS1A first capacitor C1A first switch S1A first comparator CMP1 and a first inverter INV 1. Reference current source CS1Having an output terminal, a reference current source CS1Providing a reference current I at the outputREFReference current IREFAnd a reference voltage VREFIn direct proportion, i.e. IREF＝k×VREFWhere k is a scale factor and reference current IREFWith a slave reference current source CS1The direction of outflow. A first capacitor C1And a first switch S1Are all coupled to a reference current source CS1Between the output terminal of (1) and ground reference GND, a first capacitor C1Has a first capacitor voltage VC1. The first comparator CMP1 has a first input terminal receiving the first voltage V, a second input terminal, and an output terminal1A second input terminal coupled to the reference current source CS1To receive the first capacitor C1First capacitor voltage VC1. In one embodiment, the first voltage V1For the band-gap reference voltage, the band-gap reference voltage is adopted as the first voltage V1The accuracy of the reference clock generating circuit 200 can be controlled to within 2%. In one embodiment, the first input terminal of the first comparator CMP1 is an in-phase terminal, and the second input terminal of the first comparator CMP1 is an inverted terminal. The first comparator CMP1 applies the first voltage V1And a first capacitor voltage VC1Comparing and generating a first comparison signal S at its outputCMP1. The first inverter INV1 has an input terminal and an output terminal, wherein the input terminal of the first inverter INV1 is coupled to the output terminal of the first comparator CMP1 for receiving the first comparison signal SCMP1An output terminal of the first inverter INV1 provides the reference clock signal CLK1, and an output terminal of the first inverter INV1 is coupled to the first switch S1To control the first switch S1On and off.
When the reference clock generating circuit 200 is in operation, the reference current IREFFor the first capacitor C1Charging, first capacitor C1First capacitor voltage VC1Gradually increases from zero until it increases to a first voltage V1. In the process, the voltage V is generated due to the first capacitorC1Is less than the first voltage V1The first comparator CMP1 outputs the first comparison signal S of high levelCMP1And the high-level first comparison signal S is compared with the high-level first comparison signal S through the first inverter INVlCMP1After the inversion, the reference clock generating circuit 200 generates the reference clock signal CLK1 at a low level. The low level reference clock signal CLK1 is provided to the first switch S1Controlling the first switch S1Is turned off so that the first capacitor C1Charging can be performed all the time during this process. At the first capacitor voltage VC1To a first voltage V1Thereafter, the first comparator CMP1 outputs the first comparison signal S of low levelCMP1And the low level first comparison signal S is compared through the first inverter INV1CMP1After the inversion, the reference clock generating circuit 200 generates the reference clock signal CLK1 at a high level. The high level reference clock signal CLK1 is provided to the first switch S1Controlling the first switch S1Is conducted to make the first capacitor C1Discharge, first capacitor voltage VC1Reset to zero. Thus, the reference clock generating circuit 200 enters the next new cycle with the reference current IREFThen to the first capacitor C1Charging, first capacitor C1First capacitor voltage VC1Again, starting with zero, the reference clock generation circuit 200 operates in cycles.
From the above operation, it can be easily derived that the frequency f of the reference clock signal CLK1CLK1Comprises the following steps:
Figure BDA0001903336150000051
the phase-locked loop circuit 102 is used for generating a calibration clock signalNumber CLK 2. The pll circuit 102 is coupled to the reference clock generating circuit 101 to receive the reference clock signal CLK1, and the pll circuit 102 also receives the calibrated clock signal CLK2 outputted therefrom. The PLL circuit 102 adjusts the phase difference D between the calibrated clock signal CLK2 and the reference clock signal CLK1 according to the phase differencePHThe calibrated clock signal CLK2 is adjusted such that the phase difference D between the calibrated clock signal CLK2 and the reference clock signal CLK1PHGradually decreasing, finally, the phase of the calibrated clock signal CLK2 is aligned with the phase of the reference clock signal CLK1, and the phase-locked loop circuit 102 locks the phase of the calibrated clock signal CLK 2.
Fig. 3 illustrates a phase-locked loop circuit 300 for use as the phase-locked loop circuit 102 of fig. 1, in accordance with one embodiment of the present invention. As shown in fig. 3, the phase-locked loop circuit 300 illustratively includes a phase detection circuit PD, a low pass filter circuit LPF, and a voltage controlled oscillation circuit VCO. The phase detection circuit PD has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the phase detection circuit PD receives the reference clock signal CLK1, the second input terminal of the phase detection circuit PD receives the calibration clock signal CLK2, and the phase detection circuit PD is based on the phase difference D between the calibration clock signal CLK2 and the reference clock signal CLK1PHGenerating an error voltage signal SPDError voltage signal SPDPhase difference DPHHave a functional relationship, which may be cosine, sawtooth, or triangular, etc. In one embodiment, the error voltage signal SPDAverage value of (D) and phase difference DPHAnd has a linear relationship. In a further embodiment, the error voltage signal SPDAverage value of (D) and phase difference DPHIn a direct proportional relationship. In another embodiment, the phase detection circuit PD may be implemented by an xor gate.
The low pass filter circuit LPF has an input terminal and an output terminal, wherein the input terminal of the low pass filter circuit LPF is coupled to the phase detection circuit PD to receive the error voltage signal SPDThe low pass filter circuit LPF is used for filtering the error voltage signal SPDHigh-frequency filtering to obtain a filtered signal V at its outputLPF. In one embodiment, the low pass filter circuit LPF is a typical LC low pass filter circuit.
The VCO has an input terminal coupled to the LPF for receiving the filtered signal V and an output terminalLPFThe voltage-controlled oscillating circuit VCO generates a calibrated clock signal CLK2 at an output terminal, the voltage-controlled oscillating circuit VCO being responsive to the filtered signal VLPFThe calibrated clock signal CLK2 is adjusted to change the frequency of the calibrated clock signal CLK2 such that the phase difference between the calibrated clock signal CLK2 and the reference clock signal CLKl is reduced.
Fig. 4 shows a voltage controlled oscillator circuit 400 for the voltage controlled oscillator circuit VCO of fig. 3, according to an embodiment of the invention. As shown in fig. 4, the voltage controlled oscillation circuit 400 illustratively includes a controlled current source CS2And a calibration clock generation circuit 402. Wherein the controlled current source CS2Receiving the filtered signal VLPFAnd on the basis of the filtered signal VLPFGenerating a controlled current ILPF. In one embodiment, the controlled current ILPFAnd a filtered signal VLPFIs in direct proportion.
The calibration clock generating circuit 402 is coupled to the controlled current source CS2And according to the controlled current ILPFGenerating a calibrated clock signal CLK2, calibrating the frequency f of the clock signal CLK2CLK2With a controlled current ILPFIs in direct proportion. The calibration clock generating circuit 402 includes a second capacitor C2A second switch S2A second comparator CMP2 and a second inverter INV 2. Second capacitor C2And a second switch S2Are all coupled to a controlled current source CS2And ground GND, a second capacitor C2Has a second capacitor voltage VC2. The second comparator CMP2 has a first input terminal receiving the second voltage V, a second input terminal, and an output terminal2A second input terminal coupled to the controlled current source CS2To receive the second capacitor C2Second capacitor voltage VC2. In one embodiment, the second voltage V2Is a common triode junction voltage V in a bandgap reference current sourceTln8, wherein VTIs a thermal voltage. In one embodiment, the first input terminal of the second comparator CMP2 is the in-phase terminal, and the second input terminal of the second comparator CMP2 is the in-phase terminalThe input end is an inverting end. The second comparator CMP2 applies a second voltage V2And a second capacitor voltage VC2Comparing and generating a second comparison signal S at its outputCMP2. The second inverter INV2 has an input terminal and an output terminal, wherein the input terminal of the second inverter INV2 is coupled to the output terminal of the second comparator CMP2, the output terminal of the second inverter INV2 provides the reference clock signal CLK2, and the output terminal of the second inverter INV2 is coupled to the second switch S2To control the second switch S2On and off.
The calibration clock generating circuit 402 is operated with a controlled current ILPFFor the second capacitor C2Charging, second capacitor C2Second capacitor voltage VC2Gradually increases from zero until increasing to a second voltage V2. In the process, the voltage V is generated due to the second capacitorC2Is less than the second voltage V2The second comparator CMP2 outputs the second comparison signal S of high levelCMP2And the high level second comparison signal S is compared through the second inverter INV2CMP2After the inversion, the calibration clock generating circuit 402 generates the calibration clock signal CLK2 at a low level. The low level calibrated clock signal CLK2 is provided to the second switch S2Controlling the second switch S2Is turned off so that the second capacitor C2Charging can be performed all the time during this process. And at a second capacitor voltage VC2To a second voltage V2Thereafter, the second comparator CMP2 outputs the second comparison signal S of low levelCMP2And the low level second comparison signal S is compared through the second inverter INV2CMP2After the inversion, the calibration clock generating circuit 402 generates the calibration clock signal CLK2 at a high level. The high level calibrated clock signal CLK2 is provided to the second switch S2Controlling the second switch S2Is conducted to make the second capacitor C2Discharge, second capacitor voltage VC2Reset to zero. Thus, the calibration clock generating circuit 402 enters the next new cycle and is controlled by the controlled current ILPFThen for the second capacitor C2Charging, second capacitor C2Second capacitor voltage VC2Gradually increasing from zero again to calibrate the clock generation circuit402 operate in cycles.
From the above working procedure it can be easily derived that the frequency f of the clock signal CLK2 is calibratedCLK2Comprises the following steps:
Figure BDA0001903336150000081
it will be appreciated by those skilled in the art that the configuration of the calibration clock generation circuit 402 shown in FIG. 4 is merely exemplary, and that other suitable configurations enable the frequency f of the calibration clock signal CLK2CLK2With a controlled current ILPFProportional arrangements are also suitable for use with the present invention.
Fig. 5 illustrates an output circuit 500 for use in fig. 4 in accordance with an embodiment of the present invention. As shown in fig. 5, the output circuit 500 includes a current mirror CM. The current mirror CM has an input terminal, a first output terminal and a second output terminal, wherein the input terminal of the current mirror CM is coupled to the controlled current source CS2Current mirror CM according to controlled current ILPFGenerating and controlling a current I at a first outputLPFProportional output current IOUTAnd a current I is generated and controlled at the second output terminalLPFProportional calibration current ICLK2. Referring to FIG. 4, the calibration clock generating circuit 402 is coupled to the current mirror CM for receiving the calibration current ICLK2And according to the calibration current ICLK0Generating a calibrated clock signal CLK2, wherein the frequency of the calibrated clock signal CLK2 and the calibration current ICLK2Is in direct proportion. Further, the current mirror CM includes a first switching tube M1, a second switching tube M2, and a third switching tube M3. The first switch tube M1, the second switch tube M2 and the third switch tube M3 each have a first end, a second end and a control end. First terminals of the first switch transistor M1, the second switch transistor M2 and the third switch transistor M3 are coupled to a supply voltage VCCThe control terminals of the first switch transistor M1, the second switch transistor M2, and the third switch transistor M3 are all coupled together. The second terminal of the first switch transistor M1 is coupled to the controlled current source CS as the input terminal of the current mirror CM2To receive a controlled current ILPFThe second ends of the second switch tube M2 and the third switch tube M3 are respectively used as the first output end and the second output end of the current mirror CMThe terminal takes the output current as the output current I of the output circuitOUTAnd a calibration current ICLK2. According to the working principle of the current mirror, the current ICLK2And IOUTEqualized controlled current ILPFProportionally, the proportionality coefficient is related to the size of the second switching tube M2 and the third switching tube M3 relative to the first switching tube M1. In one embodiment, the second switching tube M2 and the third switching tube M3 have the same size. It will be appreciated by those skilled in the art that the configuration of the output circuit 500 shown in FIG. 5 is merely exemplary, and that other suitable configurations are possible to enable the output current IOUTAnd a calibration current ICLK2Proportional structures are also suitable for use with the present invention. For example, in one embodiment, the output circuit may include a first controlled current source having an input and an output, wherein the input of the first controlled current source is coupled to the low pass filter circuit to receive the filtered signal, and the first controlled current source generates a current proportional to the filtered signal as the output current under control of the filtered signal.
Thus, the current I is outputOUTAnd a calibration current ICLK2The ratio between the two is also proportional. The output circuit 500 shown in FIG. 5 is applied to the current generation circuit 100 shown in FIG. 1 in combination with the voltage-controlled oscillation circuit 400 shown in FIG. 4 and the phase-locked loop circuit 300 shown in FIG. 3, because of the output current IOUTAnd a calibration current ICLK2Proportional to each other, and the frequency f of the clock signal CLK2 is calibratedCLK2With a controlled current ILPFIs in direct proportion, ensures the output current IOUTAnd calibrating the frequency f of the clock signal CLK2CLK2Is also proportional. In addition, the frequency f of the clock signal CLK2 is calibratedCLK2Is subjected to a reference clock signal CLK1 and then to a reference voltage VREFWill follow the reference voltage VREFMay vary. Thus, the output current IOUTWill follow the reference voltage VREFIs varied with a reference voltage VREFAnd (4) associating.
FIG. 6 shows a current generation circuit 600 that combines the circuits of FIGS. 2-5. The operating principle description of the reference clock generating circuit 200 in fig. 2 has already given that:
Figure BDA0001903336150000091
the operating principle description of the calibration clock generating circuit 402 shown in fig. 4 has already been given:
Figure BDA0001903336150000092
as can be seen from the description of the operation principle of the phase-locked loop circuit 300 shown in fig. 3, it controls:
fCLK1＝fCLK2
in combination with f aboveCLK1And fCLK2The specific formula of (a) can be found as follows:
Figure BDA0001903336150000101
in one embodiment, V is used1＝Vbg，V2＝VTln8, where Vbg represents a bandgap reference voltage, VTRepresenting the thermal voltage, and using a capacitance of C1 ═ C2, we can derive:
Figure BDA0001903336150000102
in the embodiment shown in fig. 5, with the switching tubes M1, M2 and M3 all of the same size, it can be found that:
IOUT＝ICLK2＝ILPF
finally, an output current I can be obtainedOUT：
Figure BDA0001903336150000103
It can be seen that the output current I obtained by adopting the circuitOUTAnd a reference voltage VREFProportional ratio, and can be used for the required outputIn the case where the current draw is proportional to the reference voltage. In particular, the output current may be used as a PTAT current that needs to be proportional to a reference voltage.
FIG. 7 is a graph showing simulation results of the current generation circuit 600 shown in FIG. 6, in which the ordinate indicates the output current, and FIG. 7 shows the reference voltage VREF3V, 3.3V and 3.6V, respectively. As can be seen from the simulation result graph shown in FIG. 7, with reference to the reference voltage VREFThe output current is changed correspondingly, i.e. the output current and the reference voltage VREFAnd (4) associating.
Fig. 8 shows a hall circuit 800 according to an embodiment of the invention. As shown in FIG. 8, the Hall circuit 800 includes a current generating circuit 801 that generates an output current IOUTWherein the output current IOUTProportional to a reference voltage. The current generating circuit 801 may be implemented using any combination of the circuits shown in fig. 1-7. The hall circuit 800 further comprises a hall sensor H coupled to the current generating circuit 801 to receive the output current IOUTHall sensor H according to output current IOUTGenerating a Hall voltage VIN. More specifically, the hall sensor H has a first contact point H1, a second contact point H2, a third contact point H3 and a fourth contact point H4, wherein the first contact point H1 is coupled to the current generating circuit 801 to receive the output current IOUTThe second contact point H2 is coupled to the reference ground, and the third contact point H3 and the fourth contact point H4 respectively serve as a non-inverting output terminal and an inverting output terminal of the Hall voltage to output a two-terminal Hall voltage VIN. The hall circuit 800 further comprises an amplification system a coupled to the hall sensor H to receive the hall voltage VINAnd according to Hall voltage VINGenerating an output voltage VOUT. More specifically, the amplifying system a has a first input terminal, a second output terminal and an output terminal, the first input terminal and the second input terminal of the amplifying system a are respectively coupled to the third contact point H3 and the fourth contact point H4 of the hall sensor H to receive the two-terminal hall voltage VINThe amplifying system A amplifies the double-end Hall voltage VINAmplifying to generate an output voltage V at an output terminalOUT。
Due to the adoption of the Hall circuit 800 capable of generating the output current IOUTA current generating circuit 801 proportional to the reference voltage, the hall circuit 800 enabling the hall voltage V, as known from the operating principle of the hall sensor H and the amplification system aINThen the output voltage V is enabledOUTAre all proportional to the reference voltage, which can be desirable for certain hall circuit applications as may be desired.
While the present invention has been described with reference to several exemplary embodiments, it is understood that the terminology used is intended to be in the nature of words of description and illustration, rather than of limitation. As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiments are not limited by any of the details of the foregoing description, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the meets and bounds of the claims, or equivalences of such meets and bounds are therefore intended to be embraced by the appended claims.

Claims (11)

1. A current generating circuit comprising:
a reference clock generating circuit providing a reference clock signal, wherein a frequency of the reference clock signal is associated with a reference voltage;
the phase-locked loop circuit outputs a calibration clock signal, receives the reference clock signal and the calibration clock signal output by the phase-locked loop circuit, and adjusts the calibration clock signal according to the phase difference between the calibration clock signal and the reference clock signal so as to reduce the phase difference between the calibration clock signal and the reference clock signal; and
and an output circuit coupled to the phase-locked loop circuit, the phase-locked loop circuit controlling the output circuit such that the output circuit generates an output current according to a phase difference between the calibration clock signal and the reference clock signal, the output current being correlated with the reference voltage.
2. The current generating circuit of claim 1, wherein the frequency of the reference clock signal is proportional to the reference voltage.
3. The current generating circuit of claim 2, wherein the reference clock generating circuit comprises:
a reference current source having an output, the reference current source providing a reference current at the output proportional to a reference voltage;
the first capacitor and the first switch are both coupled between the output end of the reference current source and the reference ground, and the first capacitor is provided with a first capacitor voltage;
the first comparator is provided with a first input end, a second input end and an output end, wherein the first input end of the first comparator receives a first voltage, the second input end of the first comparator is coupled to the output end of the reference current source, the first comparator compares the first voltage with the first capacitor voltage, and outputs a first comparison signal at the output end of the first comparator; and
and the first inverter is provided with an input end and an output end, wherein the input end of the first inverter is coupled to the output end of the first comparator, the output end of the first inverter outputs a reference clock signal, and the output end of the first inverter is coupled to the first switch so as to control the on and off of the first switch.
4. The current generating circuit of claim 1, wherein the phase locked loop circuit comprises:
the phase detection circuit is provided with a first input end, a second input end and an output end, wherein the first input end of the phase detection circuit is coupled to the reference clock generation circuit to receive the reference clock signal, the second input end of the phase detection circuit receives the calibration clock signal, and the phase detection circuit generates an error voltage signal according to the phase difference between the calibration clock signal and the reference clock signal;
a low pass filter circuit having an input terminal and an output terminal, wherein the input terminal of the low pass filter circuit is coupled to the phase detection circuit to receive the error voltage signal, and the low pass filter circuit performs high frequency filtering on the error voltage signal to obtain a filtered signal at the output terminal; and
the voltage-controlled oscillation circuit is provided with an input end and an output end, the input end of the voltage-controlled oscillation circuit is coupled to the low-pass filter circuit to receive the filter signal, the voltage-controlled oscillation circuit generates a calibration clock signal at the output end, and the voltage-controlled oscillation circuit changes the frequency of the calibration clock signal according to the filter signal so that the phase difference between the generated calibration clock signal and the reference clock signal is reduced.
5. The current generating circuit of claim 4, wherein the average value of the error voltage signal is linear with the phase difference between the calibration clock signal and the reference clock signal.
6. The current generation circuit of claim 4 wherein the voltage controlled oscillator circuit comprises:
the controlled current source is coupled to the low-pass filter circuit to receive the filter signal, and the controlled current source generates a controlled current in proportion to the filter signal under the control of the filter signal; and
and the calibration clock generating circuit is coupled to the controlled current source and generates a calibration clock signal according to the controlled current, wherein the frequency of the calibration clock signal is proportional to the controlled current.
7. The current generating circuit of claim 6, wherein the calibration clock generating circuit comprises:
the second capacitor and the second switch are coupled between the controlled current source and the reference ground, and the second capacitor has a second capacitor voltage;
a second comparator having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the second comparator receives a second voltage, the second input terminal of the second comparator is coupled to the second capacitor to receive a second capacitor voltage, the second comparator compares the second voltage with the second capacitor voltage, and outputs a second comparison signal at the output terminal of the second comparator; and
and the second inverter is provided with an input end and an output end, wherein the input end of the second inverter is coupled to the output end of the second comparator, and the output end of the second inverter outputs the calibration clock signal and is coupled to the second switch so as to control the on and off of the second switch.
8. The current generating circuit of claim 6, wherein the output circuit comprises a current mirror having an input, a first output, and a second output, wherein the input of the current mirror is coupled to the controlled current source to receive the controlled current, the current mirror generates an output current proportional to the controlled current at the first output according to the controlled current and generates a calibration current proportional to the controlled current at the second output, and wherein the calibration clock generating circuit is coupled to the second output of the current mirror to receive the calibration current and generates the calibration clock signal according to the calibration current.
9. The current generating circuit of claim 4, wherein the output circuit comprises a first controlled current source having an input and an output, wherein the input of the first controlled current source is coupled to the low pass filter circuit to receive the filtered signal, the first controlled current source generating a current proportional to the filtered signal as the output current under control of the filtered signal.
10. A hall circuit, comprising:
a current generating circuit according to any one of claims 1 to 9, generating an output current;
the Hall sensor is coupled to the current generating circuit to receive the output current, and generates a Hall voltage according to the output current; and
and the amplifying system is coupled to the Hall sensor to receive the Hall voltage and generate an output voltage according to the Hall voltage.
11. The Hall circuit of claim 10, wherein,
the Hall sensor is provided with a first contact point, a second contact point, a third contact point and a fourth contact point, wherein the first contact point is coupled to the current generation circuit to receive the output current, the second contact point is coupled to the reference ground, and the third contact point and the fourth contact point are used as an in-phase end and an anti-phase end to output double-end Hall voltage; and
the amplifying system has a first input terminal, a second output terminal, and an output terminal, the first input terminal and the second input terminal of the amplifying system are respectively coupled to the third contact point and the fourth contact point of the hall sensor to receive the double-ended hall voltage, and the amplifying system amplifies the double-ended hall voltage to generate an output voltage at the output terminal.
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