CN109637971A - A kind of semiconductor devices with improvement performance - Google Patents
A kind of semiconductor devices with improvement performance Download PDFInfo
- Publication number
- CN109637971A CN109637971A CN201811495425.9A CN201811495425A CN109637971A CN 109637971 A CN109637971 A CN 109637971A CN 201811495425 A CN201811495425 A CN 201811495425A CN 109637971 A CN109637971 A CN 109637971A
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- Prior art keywords
- layer
- semiconductor devices
- silicon substrate
- well region
- dielectric layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 230000006872 improvement Effects 0.000 title description 5
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 45
- 239000010703 silicon Substances 0.000 claims abstract description 45
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 230000004888 barrier function Effects 0.000 claims abstract description 21
- 230000000994 depressogenic effect Effects 0.000 claims abstract description 18
- 150000004767 nitrides Chemical class 0.000 claims abstract description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 6
- WGLPBDUCMAPZCE-UHFFFAOYSA-N Trioxochromium Chemical compound O=[Cr](=O)=O WGLPBDUCMAPZCE-UHFFFAOYSA-N 0.000 claims description 5
- 229910000423 chromium oxide Inorganic materials 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 229910017083 AlN Inorganic materials 0.000 claims description 4
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical group [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 5
- 230000008569 process Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000009434 installation Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000005381 potential energy Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Element Separation (AREA)
Abstract
The present invention relates to technical field of semiconductor device, more particularly to a kind of with the semiconductor devices for improving performance, including a silicon substrate, silicon substrate has first surface, second surface, dielectric layer, the first oxide layer, silicon top layer, the first mask layer are successively arranged on its first surface, the second oxide layer, barrier layer, the second mask layer are successively arranged on its second surface, dielectric layer is equipped with the well region through it, nitride is filled in well region, barrier layer is equipped with to be vacuum-treated inside its depressed area, depressed area.The present invention is by the way that well region to be arranged on the dielectric layer, and filling nitride, so that dielectric layer reduces the influence to semiconductor devices forming process, the setting of well region simultaneously, avoid influence of the intrinsic junction capacity formed between silicon substrate and silicon top layer to carrier in silicon substrate, and then efficiency of the signal by semiconductor devices is improved, and reduce the distortion rate of signal.
Description
Technical field
The present invention relates to technical field of semiconductor device, and in particular to a kind of with the semiconductor devices for improving performance.
Background technique
Higher and higher for the volume requirement of semiconductor components and devices now, bulky semiconductor accounts for during installation
There is very big installation space, is unfavorable for chip to the features such as light, small development, while chip also needs the anti-interference ability of signal
It improves, can exist due to thering is buried oxide layer to be isolated between the silicon substrate and top layer silicon of soi wafer, between silicon substrate and top layer silicon intrinsic
Junction capacity, in some cases, the radiofrequency signal of process may interfere the carrier of silicon substrate in semiconductor devices, make
The junction capacity that is formed above silicon substrate and silicon substrate between the region of device can be generated with radiofrequency signal it is irregular, non-thread
Property variation, and then cause by semiconductor devices signal waveform be distorted.
Summary of the invention
It is an object of the invention to overcome problems of the prior art, provide a kind of with the semiconductor for improving performance
Device, it may be implemented to reduce cost, reduces distortion rate.
To realize above-mentioned technical purpose and the technique effect, the present invention is achieved by the following technical solutions:
A kind of semiconductor devices with improvement performance, including a silicon substrate, the silicon substrate have first surface, second
Surface, is successively arranged dielectric layer, the first oxide layer, silicon top layer, the first mask layer on first surface, on second surface successively
Equipped with the second oxide layer, barrier layer, the second mask layer, the dielectric layer is equipped with the well region through it, filling in the well region
There is nitride, the barrier layer is equipped with to be vacuum-treated inside its depressed area, the depressed area.
Further, the nitride is aluminium nitride.
Further, first oxide layer, the second oxide layer are made of silica, chromium oxide any one material.
Further, the depressed area quantity is 8-10.
Further, production method includes the following steps:
S1, a silicon substrate is provided；
S2, dielectric layer formed by dry etching on the first surface of silicon substrate；
S3, well region is etched on the dielectric layer；
S4, nitride is filled in well region；
S5, the first oxide layer is formed on the dielectric layer；
S6, silicon top layer is formed in the first oxide layer；
S7, the first mask layer is deposited on silicon top layer；
S8, the second oxide layer, barrier layer are sequentially formed on the second surface of silicon substrate；
S9, over the barrier layer etching notched area；
S10, the second mask layer is deposited over the barrier layer.
Beneficial effects of the present invention: by the way that well region to be arranged on the dielectric layer, and filling nitride, so that dielectric layer reduces
Influence to semiconductor devices forming process, while the setting of well region avoid the intrinsic knot formed between silicon substrate and silicon top layer electric
Hold the influence to carrier in silicon substrate, and then improve efficiency of the signal by semiconductor devices, and reduces the distortion rate of signal,
Depressed area is set and will be vacuum-treated inside depressed area, makes semiconductor devices in working condition, carrier thereon is logical
When crossing depressed area, rate increases, to improve the efficiency of semiconductor devices signal transmission, while reducing signal distortion rate, is arranged
Barrier layer increases the potential energy of electronics in semiconductor devices, to guarantee the efficiency of transmission, in production method, is situated between by dry etching
Electric layer is not easily susceptible to destroy since dry etching directionality is stronger so that the interatomic bond after dielectric layer etch closes structure, thus
It reduces to the influence during carrier transport, reduces distortion rate.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, will be described below to embodiment required
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for ability
For the those of ordinary skill of domain, without creative efforts, it can also be obtained according to these attached drawings other attached
Figure.
Fig. 1 is a kind of structural schematic diagram with the semiconductor devices for improving performance in the embodiment of the present invention 1；
Fig. 2 is a kind of structural schematic diagram with the semiconductor devices for improving performance in the embodiment of the present invention 2；
Fig. 3 is a kind of production method flow diagram with the semiconductor devices for improving performance of the present invention；
In attached drawing, component representated by each label is as follows:
1- silicon substrate, 2- dielectric layer, 3- well region, the first oxide layer of 4-, 5- silicon top layer, the first mask layer of 6-, the second oxygen of 7-
Change layer, the barrier layer 8-, the depressed area 9-, the second mask layer of 10-, 11- dividing groove.
Specific embodiment
In order to be easy to understand the technical means, the creative features, the aims and the efficiencies achieved by the present invention, below will
It is described with reference to the drawings, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described implementation
Example is only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is common
Technical staff's all other embodiment obtained without creative efforts belongs to the model that the present invention protects
It encloses.
Embodiment 1
A kind of semiconductor devices with improvement performance as shown in Figure 1, including a silicon substrate 1, the silicon substrate 1 have
First surface, second surface are successively arranged dielectric layer 2, the first oxide layer 4, silicon top layer 5, the first mask layer on first surface
6, the second oxide layer 7, barrier layer 8, the second mask layer 10 are successively arranged on second surface, the dielectric layer 2, which is equipped with, to be run through
Its well region 3, the well region 3 is interior to be filled with nitride, and the barrier layer 8 is equipped with through its depressed area 9, the depressed area
It is vacuum-treated inside 9.
The nitride is aluminium nitride.
First oxide layer 4, the second oxide layer 7 are made of silica, chromium oxide any one material, the present embodiment
It is set as silica.
9 quantity of depressed area is 8-10.
As shown in figure 3, its production method includes the following steps:
S1, a silicon substrate 1 is provided；
S2, pass through dry etching formation dielectric layer 2 on the first surface of silicon substrate 1；
S3, well region 3 is etched on dielectric layer 2；
S4, nitride is filled in well region 3；
S5, the first oxide layer 4 is formed on dielectric layer 2；
S6, silicon top layer 5 is formed in the first oxide layer 4；
S7, the first mask layer 6 is deposited on silicon top layer 5；
S8, the second oxide layer 7, barrier layer 8 are sequentially formed on the second surface of silicon substrate 1；
S9, the etching notched area 9 on barrier layer 8；
S10, the second mask layer 10 is deposited on barrier layer 8.
Embodiment 2
A kind of semiconductor devices with improvement performance as shown in Figure 2, including a silicon substrate 1, the silicon substrate 1 have
First surface, second surface are successively arranged dielectric layer 2, the first oxide layer 4, silicon top layer 5, the first mask layer on first surface
6, the second oxide layer 7, barrier layer 8, the second mask layer 10 are successively arranged on second surface, the dielectric layer 2, which is equipped with, to be run through
Its well region 3, the well region 3 is interior to be filled with nitride, and the barrier layer 8 is equipped with through its depressed area 9, the depressed area
It is vacuum-treated inside 9.
The nitride is aluminium nitride.
First oxide layer 4, the second oxide layer 7 are made of silica, chromium oxide any one material, the present embodiment
It is set as chromium oxide.
9 quantity of depressed area is 8-10.
3 two sides of well region are equipped with dividing groove 11, make dielectric layer 2 in semiconductor devices pressure-bearing, are able to carry out partial pressure.
Its production method and embodiment 1 are consistent.
Present invention disclosed above preferred embodiment is only intended to help to illustrate the present invention.There is no detailed for preferred embodiment
All details are described, are not limited the invention to the specific embodiments described.Obviously, according to the content of this specification,
It can make many modifications and variations.These embodiments are chosen and specifically described to this specification, is in order to better explain the present invention
Principle and practical application, so that skilled artisan be enable to better understand and utilize the present invention.The present invention is only
It is limited by claims and its full scope and equivalent.
Claims (5)
1. a kind of with the semiconductor devices for improving performance, which is characterized in that including a silicon substrate (1), silicon substrate (1) tool
There are first surface, second surface, dielectric layer (2), the first oxide layer (4), silicon top layer (5), are successively arranged on first surface
One mask layer (6) is successively arranged the second oxide layer (7), barrier layer (8), the second mask layer (10) on second surface, is given an account of
Electric layer (2) is equipped with the well region (3) through it, and nitride is filled in the well region (3), and the barrier layer (8) is equipped with and passes through
Its depressed area (9) is worn, is vacuum-treated inside the depressed area (9).
2. according to claim 1 a kind of with the semiconductor devices for improving performance, which is characterized in that the nitride is
Aluminium nitride.
3. according to claim 1 a kind of with the semiconductor devices for improving performance, which is characterized in that first oxidation
Layer (4), the second oxide layer (7) are made of silica, chromium oxide any one material.
4. according to claim 1 a kind of with the semiconductor devices for improving performance, which is characterized in that the depressed area
(9) quantity is 8-10.
5. according to claim 1 a kind of with the semiconductor devices for improving performance, which is characterized in that its production method packet
Include following steps:
S1, a silicon substrate (1) is provided；
S2, pass through dry etching formation dielectric layer (2) on the first surface of silicon substrate (1)；
S3, well region (3) are etched on dielectric layer (2)；
S4, nitride is filled in well region (3)；
S5, the first oxide layer (4) are formed on dielectric layer (2)；
S6, silicon top layer (5) are formed on the first oxide layer (4)；
S7, the first mask layer (6) are deposited on silicon top layer (5)；
S8, the second oxide layer (7), barrier layer (8) are sequentially formed on the second surface of silicon substrate (1)；
S9, the etching notched area (9) on barrier layer (8)；
S10, the second mask layer (10) are deposited on barrier layer (8).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811495425.9A CN109637971B (en) | 2018-12-07 | 2018-12-07 | Semiconductor device with improved performance |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811495425.9A CN109637971B (en) | 2018-12-07 | 2018-12-07 | Semiconductor device with improved performance |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109637971A true CN109637971A (en) | 2019-04-16 |
| CN109637971B CN109637971B (en) | 2021-08-10 |
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| CN201811495425.9A Active CN109637971B (en) | 2018-12-07 | 2018-12-07 | Semiconductor device with improved performance |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19962053B4 (en) * | 1998-12-24 | 2005-08-25 | Mitsubishi Denki K.K. | Semiconductor device with SOI structure and partial separation regions |
| CN103022054A (en) * | 2012-12-21 | 2013-04-03 | 上海宏力半导体制造有限公司 | SOI (silicon-on-insulator) radio-frequency device and SOI substrate |
| CN103824837A (en) * | 2014-03-10 | 2014-05-28 | 上海华虹宏力半导体制造有限公司 | Semiconductor device structure and manufacturing method thereof |
| CN105633002A (en) * | 2015-12-29 | 2016-06-01 | 中国科学院上海微系统与信息技术研究所 | Graphic silicon-on-insulator material and preparation method thereof |
| WO2016149113A1 (en) * | 2015-03-17 | 2016-09-22 | Sunedison Semiconductor Limited | Thermally stable charge trapping layer for use in manufacture of semiconductor-on-insulator structures |
| CN107170750A (en) * | 2017-05-08 | 2017-09-15 | 合肥市华达半导体有限公司 | A kind of semiconductor components and devices structure and preparation method thereof |
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| US20180337043A1 (en) * | 2017-05-19 | 2018-11-22 | Psemi Corporation | Managed Substrate Effects for Stabilized SOI FETs |
-
2018
- 2018-12-07 CN CN201811495425.9A patent/CN109637971B/en active Active
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| US20180337043A1 (en) * | 2017-05-19 | 2018-11-22 | Psemi Corporation | Managed Substrate Effects for Stabilized SOI FETs |
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|---|
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Effective date of registration: 20220615 Address after: 230000 Room 301 and 302, building 4, phase I, mechanical and Electrical Industrial Park, No. 767, Yulan Avenue, high tech Zone, Hefei City, Anhui Province Patentee after: Hefei Huayu Semiconductor Co.,Ltd. Address before: 230088 6th floor, building B, science and technology innovation public service and applied technology R & D center, hewubeng Experimental Zone, No. 860, Wangjiang West Road, high tech Zone, Hefei, Anhui Province Patentee before: HEFEI HUADA SEMICONDUCTOR Co.,Ltd. |
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Address after: 230000, No. 66 Tiantangzhai Road, High tech Zone, Hefei City, Anhui Province Patentee after: Hefei Huayu Semiconductor Co.,Ltd. Country or region after: China Address before: 230000 Room 301 and 302, building 4, phase I, mechanical and Electrical Industrial Park, No. 767, Yulan Avenue, high tech Zone, Hefei City, Anhui Province Patentee before: Hefei Huayu Semiconductor Co.,Ltd. Country or region before: China |
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