CN109525518A - A kind of IP packet method for network address translation and device based on FPGA - Google Patents
A kind of IP packet method for network address translation and device based on FPGA Download PDFInfo
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- CN109525518A CN109525518A CN201811592943.2A CN201811592943A CN109525518A CN 109525518 A CN109525518 A CN 109525518A CN 201811592943 A CN201811592943 A CN 201811592943A CN 109525518 A CN109525518 A CN 109525518A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
- H04L49/9057—Arrangements for supporting packet reassembly or resequencing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
- H04L47/62—Queue scheduling characterised by scheduling criteria
- H04L47/622—Queue service order
- H04L47/6225—Fixed service order, e.g. Round Robin
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L61/00—Network arrangements, protocols or services for addressing or naming
- H04L61/09—Mapping addresses
- H04L61/25—Mapping addresses of the same type
- H04L61/2503—Translation of Internet protocol [IP] addresses
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- Computer Networks & Wireless Communication (AREA)
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- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The embodiment of the invention discloses a kind of IP packet method for network address translation and device based on FPGA.The method is applied in programmable logic device, comprising: receiving IP packet and difference cutting parallel by ethernet port is cell unit；Packet parsing is carried out to first cell unit, IP packet attribute information is obtained, the cell unit for belonging to same IP packet is stored in packet buffer area according to port；Using port polling scheduling mechanism, cell unit corresponding with a port is successively obtained in packet buffer area as current cell unit, and according to the type of current cell unit, assembling processing is carried out to current cell unit；When determining that whole cell unit corresponding with an IP packet is assembled completion, IP packet is forwarded by port corresponding with IP packet.The technical solution of the embodiment of the present invention carries out network address translation to IP packet by FPGA, improves processing speed and versatility.
Description
Technical field
The present embodiments relate to network communication field technology more particularly to a kind of IP packet network address based on FPGA
Conversion method and device.
Background technique
With the continuous development of the communication technology, the usage quantity of computer increases sharply, and IP address (Internet occurs
ProtocolAddress, Internet protocol address) space failure the problem of.Privately owned net may be implemented in NAT technology
The function of network access public network, this mode that more private IP address is represented by using a small amount of public ip address,
Help to slow down the failure of available IP address space.
When the implicit IP address for having secrecy needs or network can not be in external Web vector graphic, the network switching equipment needs
Carry out IP packet network address translation, the prior art mainly pass through special network processor (Network Processor,
NP) and the mode of host to realize carries out network address translation to IP packet, but in many commonly used equipments currently on the market
Do not include special network processor, and the equipment comprising special network processor is used to spend cost relatively high, causes to make
It is compared with the customer group that the equipment comprising special network processor carries out network address translation less, therefore this method is not
With versatility.For the equipment for not including special network processor, common method is by multi-core CPU (Central
Processing Unit, central processing unit) Lai Shixian IP packet network address translation, still, it is this by multi-core CPU into
Traditional CPU hardware scheme of row network address translation, needs to handle a large amount of instruction, not only relatively slow in processing speed, Er Qiehui
So that whole system processing is complex.
Summary of the invention
The embodiment of the present invention provides a kind of IP packet method for network address translation and device based on FPGA, by that can compile
Journey logical device FPGA (Field-Programmable Gate Array, field programmable gate array) is realized quickly, effectively
Ground carries out network address translation to IP packet.
In a first aspect, the embodiment of the invention provides a kind of IP packet method for network address translation based on FPGA, application
In programmable logic device, comprising:
Multiple IP packets are received parallel by multiple ethernet ports, and received each IP packet is distinguished into cutting and is
Multiple cell units include IP packet attribute information in the first cell unit in the IP packet；
Packet parsing is carried out to each head cell unit, obtains IP packet attribute letter corresponding with the head cell unit
Breath, and belong to other cell units of same IP packet according to port by the head cell unit and with the head cell unit
Correspondence is stored in packet buffer area；
Using port polling scheduling mechanism, cell unit corresponding with a port is successively obtained in packet buffer area and is made
For current cell unit, and according to the type of the current cell unit, take corresponding processing mode to the current cell
Unit carries out cell unit assembling processing；
When determining that whole cell unit corresponding with an IP packet is assembled completion, by corresponding with the IP packet
Port the IP packet is forwarded.
Optionally, according to the type of the current cell unit, take corresponding processing mode mono- to the current cell
Member carries out cell unit assembling processing, comprising:
If cell unit headed by current cell unit, packet parsing is carried out to the current cell unit, will be parsed
Obtained IP packet attribute information carries out network address translation, obtain new IP packet attribute information re-write it is described current
Cell unit, and according to the current cell unit construction assembling message structure；If the current cell unit not headed by
Then the current cell unit is added in the tail portion of the assembling message structure with the current cell units match in cell unit.
Optionally, it using port polling scheduling mechanism, is successively obtained in packet buffer area corresponding with a port
Cell unit is specifically included as current cell unit:
When determining poll to target port using port polling scheduling mechanism, detect whether to receive and the target side
The matched scheduling controlling instruction of mouth；
If so, obtaining cell unit corresponding with the target port in the packet buffer area as current cell
Unit；
Wherein, the scheduling controlling instruction is corresponding to the target port of current scheduling when packet buffer area non-empty
It generates.
Optionally, in other cell for belonging to same IP packet by the head cell unit and with the head cell unit
After unit is stored in packet buffer area according to port is corresponding, further includes:
After determining that cell unit corresponding with same IP packet is all cached in the packet buffer area, determines and be somebody's turn to do
The corresponding cell unit of IP packet participates in port polling scheduling.
Optionally, the IP packet attribute information that parsing is obtained carries out network address translation, obtains new IP packet
Attribute information re-writes the current cell unit, comprising:
The IP packet attribute information that parsing obtains is matched with network address translation table, if successful match,
According to matching result, obtains conversion IP packet attribute information corresponding with the IP packet attribute information and the current cell is written
In unit；
It wherein, include: new IP information, new TCP (Transmission in the conversion IP packet attribute information
Control Protocol, transmission control protocol)/UDP (User Datagram Protocol, User Datagram Protocol) port
Information, new IP verification and with new TCP/UDP verification and；
If it fails to match, target value is set by the value of the ethernet type parameter in the current cell unit, and
Message data in current cell unit is returned into network exchanging chip；
Wherein, the target value in the ethernet type parameter passes through the Ethernet with the FPGA for notifying
The connected network exchanging chip of interface is added and the IP of the current cell unit in the network address translation table of the FPGA
The corresponding network address translation table item of message attribute information.
Optionally, described to use port polling scheduling mechanism, it is successively obtained in packet buffer area corresponding with a port
Cell unit as current cell unit, comprising:
According to port cell element number poll port, if the port cell element number of present port is not 0, from working as
Front port dispatches a cell unit, and otherwise, present port continues poll next port without cell cell scheduling；
Wherein, when a cell unit is stored in packet buffer area according to port is corresponding, the port cell of the port is mono-
First quantity adds 1, and when a cell of port is scheduled outgoing packet buffer area, the port cell element number of the port subtracts 1.
Optionally, before receiving multiple IP packets parallel by multiple ethernet ports, further includes:
Confirm network address translation desired bandwidth, according to the desired bandwidth calculate cell unit bit wide parameter,
The working clock frequency parameter of FPGA and packet buffer area；
Wherein, the packet buffer area includes FPGA internal RAM (Random Access Memory, random access memory
Device) and outside DDR (Double Data Rate SDRAM, Double Data Rate synchronous DRAM).
Optionally, other cell for belonging to same IP packet by the head cell unit and with the head cell unit are mono-
Member is stored in packet buffer area according to port correspondence, comprising:
By the packet buffer region of head cell unit deposit corresponding ports；
Other cell units for belonging to same IP packet with the head cell unit are empty by obtaining from free pointer chained list
Not busy pointer is connected in series to the cell unit pointer chained list of corresponding ports；
Wherein, the first pointer in the cell unit pointer chained list is directed toward head cell unit in the report of the corresponding ports
The storage location of literary buffer zone.
It is optionally, described that received each IP packet is distinguished into cutting for multiple cell units, comprising:
A port is obtained as target port according to port order；
It will be multiple cell units by the received IP packet cutting of the target port, and described more detecting
When a cell unit is stored entirely in packet buffer area corresponding with the target port, returns to execute and be obtained according to port order
Operation of a port as target port is taken, ends processing condition until meeting.
Second aspect, the embodiment of the invention also provides a kind of IP packet network address conversion device based on FPGA are answered
For in programmable logic device, comprising:
Cutting module is received, for receiving multiple IP packets parallel by multiple ethernet ports, and by received each institute
Stating IP packet difference cutting is multiple cell units, includes IP packet attribute information in the first cell unit in the IP packet；
Memory module is parsed, for carrying out packet parsing to each head cell unit, is obtained and the head cell unit
Corresponding IP packet attribute information belongs to other of same IP packet by the head cell unit and with the head cell unit
Cell unit is stored in packet buffer area according to port correspondence；
Schedule process module successively obtains in packet buffer area and an end for using port polling scheduling mechanism
The corresponding cell unit of mouth takes corresponding processing as current cell unit, and according to the type of the current cell unit
Mode carries out cell unit assembling processing to the current cell unit；
Forwarding module, for when determining that corresponding with an IP packet whole cell unit is assembled completion, by with
The IP packet is forwarded by the corresponding port of the IP packet.
The embodiment of the present invention passes through in programmable logic device FPGA that received IP packet cutting is mono- for multiple cell
Member only carries out packet parsing, network address translation table matching and message information to the first cell unit comprising IP attribute information
After modification, the side that is forwarded after being again combined the head cell unit with other cell units for belonging to same IP packet
Formula solves existing multi -CPU processing technique and carries out network address turn to IP packet by sufficiently developing the hardware capability of FPGA
The problem of processing speed is slow when changing, poor universality realizes raising processing speed and general on the basis of reducing cost of implementation
The effect of property.
Detailed description of the invention
Fig. 1 is a kind of process for IP packet method for network address translation based on FPGA that the embodiment of the present invention one provides
Figure；
Fig. 2 a is a kind of process of IP packet method for network address translation based on FPGA provided by Embodiment 2 of the present invention
Figure；
Fig. 2 b is the interface diagram that the method for the embodiment of the present invention is applicable in；
Fig. 2 c is the concrete function structure chart for the FPGA that the method for the embodiment of the present invention is applicable in；
Fig. 3 is that a kind of structure for IP packet network address conversion device based on FPGA that the embodiment of the present invention three provides is shown
It is intended to.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention rather than limiting the invention.It also should be noted that in order to just
Only the parts related to the present invention are shown in description, attached drawing rather than entire infrastructure.
Embodiment one
Fig. 1 is a kind of process for IP packet method for network address translation based on FPGA that the embodiment of the present invention one provides
Figure, the embodiment of the present invention are applicable to the case where carrying out network address translation to IP packet by programmable logic device, the party
Method can be executed by network address conversion device, which can be realized by the mode of hardware, and generally can be applied to
In FPGA.Specifically, this method may include steps of with reference to Fig. 1:
Step 110 is received multiple IP packets parallel by multiple ethernet ports, and received each IP packet is cut respectively
It is divided into multiple cell units.
Wherein, ethernet port can specifically include: support SGMII, 1000-BaseX and ethernet mac (Media
Access Control, media access control) function gigabit interface, generally FPGA embeds IP.Above-mentioned ethernet port can
To be specifically used for: being parsed to Ethernet protocol, and receive the IP packet that network exchanging chip is sent.
Optionally, on-site programmable gate array FPGA is a kind of choosing of the programmable logic device in the embodiment of the present invention
It selects, can also include EPLD (erasable programmable logic device, Erase Programmable LogicDevice) etc.
Other programmable logic device, the embodiment of the present invention to the selection of programmable logic device without limitation.
Specifically, FPGA is connected by ethernet port with network exchanging chip, to receive network exchanging chip transmission
IP packet can be according to the maximum interface performance and FPGA interface rate of network chip and place in order to meet the needs of system
Multiple groups ethernet port is arranged between FPGA and network exchanging chip, receives multiple IP packets parallel for rationality energy.IP packet is
Refer to the IP packet for needing network exchanging chip to forward, (Access Control List is visited by the ACL of network exchanging chip
Ask control list) it matches and is redirected to the FPGA connecting with the ethernet port of network exchanging chip, logic electricity is passed through by FPGA
Road carries out the network address translation of high bandwidth to the IP packet, then is turned by ethernet port corresponding with the IP packet in FPGA
It is dealt into network exchanging chip and carries out subsequent processing.
In the present embodiment, FPGA receives multiple IP packets by multiple ethernet ports parallel, and according to port order
It is successively multiple cell units by each received IP packet cutting, IP packet is operated in the form of cell unit.Tool
Body, IP packet is operated and more flexible can store IP packet using buffer zone in the form of cell unit, is mentioned
The utilization rate in high level cache region reduces the waste of buffer zone, for example, when not having one piece of continuous spatial cache in buffer zone
When can store IP packet, by the way that IP packet is cut into lesser cell unit, the cell unit of cutting is respectively stored in
In multiple discontinuous spatial caches in buffer zone, to realize the storage to IP packet.
Optionally, according to the maximum interface performance of network exchanging chip and FPGA interface rate and process performance, in FPGA
Multiple groups ethernet port is set between network exchanging chip, receives multiple IP packets parallel, can specifically include: network address
Bandwidth needed for converting is 4G, and the Processing Interface performance of network exchanging chip is 64G, in order to realize the 4G band of network address translation
Width, FPGA need to provide 4 groups of ethernet ports, and therefore, network exchanging chip needs to provide the 4 of 4 groups of ethernet ports and FPGA
Group ethernet port is connected, and FPGA is allowed to receive the IP of 4 network exchanging chips forwarding parallel by 4 groups of ethernet ports
Message.
Specifically, being that multiple cell units can specifically include by each received IP packet cutting: according to network address
The working clock frequency of actual bandwidth required for converting and FPGA determine the size of each cell unit, from the head of IP packet
Portion start be by IP packet cutting multiple fixed sizes cell unit, wherein the size of each cell unit at least should can
With three layers of head information and four layers of head information comprising IP packet.It optionally, is that size is by each received IP packet cutting
The cell unit of 96B, it is subsequent that processing operation is carried out to IP packet in the form of the cell unit, wherein each cell unit
The working clock frequency of size actual bandwidth according to required for network address translation and FPGA are adjusted.
Step 120 carries out packet parsing to each head cell unit, obtains IP packet category corresponding with the head cell unit
Property information, and by all cell units for belonging to same IP packet according to port correspondence be stored in packet buffer area.
It wherein, include the message attribute information of the IP packet, the i.e. IP packet in the corresponding head cell unit of each IP packet
Three layers of head information and four layers of head information.Wherein, three layers of head information of IP packet mainly include IP packet length, fragment marking,
Source IP information, destination IP information, id information and OFFSET information；Four layers of head information of IP packet mainly include the end of TCP and UDP
Message breath.In the present embodiment, after received each IP packet difference cutting is multiple cell units by FPGA, according to message format pair
Each head cell unit carries out packet parsing, the message attribute information of IP packet corresponding with each head cell unit is obtained, to be used for
Carry out subsequent network address translation processing.
In order to which IP packet is stored in buffer zone in the form of cell unit, FPGA maintains one in buffer area
Free pointer chained list and maintain a cell pointer chained list respectively according to port.Optionally, each port is one corresponding
Cell unit pointer chained list, what is stored in the chained list is the storage address of cell unit corresponding with present port, the storage
Storage location of the cell unit message in packet buffer area is directed toward in location, and the different cell in same cell unit pointer chained list are mono-
The storage address of member is applied at random in packet buffer area, so that the message for reaching all of the port shares packet buffer area
Effect reduces the consumption of memory.Specifically, belonging to its of same IP packet by first cell unit and with the head cell unit
He is stored in packet buffer area cell unit according to port correspondence, may include: that first cell unit is stored in corresponding ports
Packet buffer region corresponding to cell pointer chained list；After first cell unit is stored in packet buffer region, with the head cell
Unit belongs to other cell units of same IP packet by from free pointer chained list application free pointer, and by cell unit report
Text is stored in the free pointer and is connected in series to behind the cell unit pointer chained list of corresponding ports.Wherein, FPGA passes through to corresponding ports
Cell unit pointer chained list safeguarded, all cell units for belonging to same IP packet are all linked to corresponding ports
Cell unit pointer chained list.
Optionally, in order to avoid packet loss, a fixation is arranged in each ethernet port in FPGA in packet buffer area
The RAM of size is as temporary buffer, for example, the RAM of 4 cell size is arranged as interim slow in each ethernet port
Area is deposited, when the cell unit being stored in packet buffer area originally not yet has been processed into, there are new cell unit needs to deposit
It stores up in the corresponding packet buffer area in the port, at this point it is possible to which it is corresponding interim slow that new cell unit is stored in the port
It deposits in area, to avoid packet loss.
Step 130, using port polling scheduling mechanism, successively in packet buffer area obtain it is corresponding with a port
Cell unit takes corresponding processing mode to current as current cell unit, and according to the type of current cell unit
Cell unit carries out cell unit assembling processing.
Optionally, FPGA use port polling scheduling mechanism, according to port order successively in packet buffer area obtain with
The corresponding cell unit to be scheduled of a port is taken as current cell unit, and according to the type of current cell unit
Corresponding processing mode carries out cell unit assembling processing to current cell unit.Wherein, port polling scheduling mechanism indicates, when
After the completion of the current cell cell scheduling of a port, poll next port, selection one is wait dispatch from next port
Cell unit as current cell unit, cell unit assembling processing is carried out to it.
Optionally, when being scheduled using port polling scheduling mechanism to cell unit, due to dispatching a cell unit
Need 16 periods that could complete, network exchanging chip provides 4 groups of ethernet ports and is connected with 4 groups of ethernet ports of FPGA,
Then each ethernet port is every primary by 48 cycle pollings, for example, current scheduling is cell unit in port 1, then
After 16 periods, the cell cell scheduling complete, can from port 2 select a cell unit be scheduled, so according to
4 ports of secondary poll, dispatch a cell unit respectively from each port, by the dispatching cycle of above-mentioned 4 cell units
Afterwards, and it is polled to port 1, i.e., each port is every primary by 48 cycle pollings.
When being scheduled to cell unit, need to carry out it cell unit assembling processing, due to the message category of IP packet
Property information be contained only in the first cell unit of IP packet, to IP packet carry out the assembling of cell unit processing also primarily directed to head
Cell unit is handled, therefore, the cell unit group to the first cell unit and non-head cell unit that belong to same IP packet
Dress processing is different.Optionally, according to the type of current cell unit, take corresponding processing mode mono- to current cell
Member carry out the assembling of cell unit processing can specifically include: judge current cell unit whether headed by cell unit, if so, right
Current cell unit carries out packet parsing, network address translation, message information modification and Packet reassembling operation, if it is not, then straight
It connects and Packet reassembling operation is carried out to current cell unit.
Optionally, only delay in the message that determining cell unit corresponding with same IP packet is all cached in corresponding ports
After depositing region, cell unit corresponding with the IP packet can just participate in port polling scheduling.
Step 140, when determining that corresponding with an IP packet whole cell unit is assembled completion, by with IP packet
IP packet is forwarded by corresponding port.
When whole cell unit corresponding with an IP packet is reassembled into complete IP packet, FPGA is by recombination
IP packet is sent to network exchanging chip by ethernet port corresponding with IP packet, so that after network exchanging chip is to recombination
IP packet carry out subsequent processing.
The embodiment of the present invention by FPGA by received IP packet cutting be multiple cell units, only belong to comprising IP
Property information first cell unit carry out packet parsing, network address translation table matching and message information modification after, again should
The mode that first cell unit and other cell units for belonging to same IP packet are forwarded after being combined, by sufficiently developing
The hardware capability of FPGA, solve processing speed when existing multi -CPU processing technique carries out network address translation to IP packet it is slow,
The problem of poor universality, realizes the effect for improving processing speed and versatility on the basis of reducing cost of implementation.
Embodiment two
Fig. 2 a is a kind of process of IP packet method for network address translation based on FPGA provided by Embodiment 2 of the present invention
Figure, the present embodiment can be in conjunction with each optinal plan in said one or multiple embodiments.Specifically, with reference to Fig. 2 a, it should
Method may include steps of:
Parameter needed for step 210, confirmation network address translation.
In the present embodiment, in order to realize the network address translation of high bandwidth, the processing speed to IP packet is improved, first
According to system integrated demand, bandwidth required for network address translation is confirmed, and according to the position of required bandwidth calculation cell unit
The size of wide parameter, the working clock frequency parameter of FPGA and packet buffer area；Wherein, the bit wide parameter of cell unit determines
The size of the cell unit of IP packet is formed, the working clock frequency parameter of FPGA refers to the system of the digital circuit based on FPGA
The frequency of master clock, can influence the size of cell unit, and packet buffer area may include FPGA internal RAM and outside DDR,
It is used to store IP packet in the form of cell unit.
Optionally, network exchanging chip Processing Interface performance is 64G, and bandwidth needed for network address translation is 4G, then needs
It wants network exchanging chip to provide 4 groups of Ethernet interfaces to be connected with 4 groups of Ethernet interfaces of FPGA, to realize network address translation institute
It is required that 4G bandwidth.As shown in Figure 2 b, if network exchanging chip is internally embedded CPU, it is also required to provide one group of SPI
(Serial Peripheral Interface, Serial Peripheral Interface (SPI)) slave interface is connected with FPGA, turns as network address
Change table and internal register management interface.Wherein, SPI interface be a kind of high speed, full duplex, synchronization communication bus,
Using when be divided into main (master), from (slave) both of which, be commonly used in short haul connection.
Received each IP packet is distinguished cutting for multiple cell units by step 220.
In the present embodiment, after receiving multiple IP packets parallel by multiple ethernet ports, successively according to port order
It is the cell unit of multiple fixed length by received IP packet cutting.Wherein, only will be corresponding to the received IP packet of present port
Cell unit be stored entirely in after the corresponding packet buffer area of present port, just the received IP packet of next port is cut
It is divided into the cell unit of multiple fixed length.
Step 230 carries out packet parsing to each head cell unit, and will belong to all cell units of same IP packet by
Packet buffer area is stored according to port correspondence.
Step 240, using port polling scheduling mechanism, according to port cell element number and scheduling controlling instruction scheduling
Cell unit.
Wherein, using port polling scheduling mechanism, according to port cell element number and scheduling controlling instruction scheduling
Cell unit may include: according to port order poll port, according to the corresponding port cell unit in the port being currently polled to
Quantity and scheduling controlling instruction, it is mono- successively to obtain a cell corresponding with the port being currently polled in packet buffer area
Member is used as current cell unit, and processing is scheduled to it.
Optionally, one is obtained in packet buffer area according to the corresponding port cell element number in the port being currently polled to
A cell unit corresponding with the port can specifically include as current cell unit: if the port being currently polled to is corresponding
Port cell element number be not 0, then cell unit is obtained from the corresponding packet buffer area of present port as working as
Preceding cell unit, processing is scheduled to it, and otherwise, present port continues the next end of poll without cell cell scheduling
Mouthful.Wherein, when a cell unit is stored in packet buffer area according to port is corresponding, the corresponding port cell unit in the port
Quantity adds 1, when and the corresponding cell unit of a port it is scheduled go out packet buffer area corresponding with the port when, the end
The port cell element number of mouth subtracts 1.
Optionally, it when using port polling scheduling mechanism poll to target port again, detects whether to receive and mesh
The scheduling controlling instruction for marking port match, instructs if receiving with the matched scheduling controlling of target port, in packet buffer area
It is middle to obtain corresponding with target port cell unit as current cell unit, and until being dispatched to present port next time pair
Current cell unit is scheduled.It instructs, can be directly dispatched with the matched scheduling controlling of target port if being not received by
The current cell unit to be scheduled of target port, processing is scheduled to it, does not need to be waited.Wherein, scheduling controlling
Instruction generates when packet buffer area non-empty corresponding to the target port of current scheduling, indicates that previous cell unit is not yet complete
It is handled at cell unit assembling, the current cell unit of target port cannot be scheduled at once, need to be dispatched to until next round
When target port, then cell unit assembling processing is carried out to current cell unit.
Step 250, according to the type of current cell unit, to taking corresponding processing mode to carry out current cell unit
Cell unit assembling processing.
In the present embodiment, due in the non-head cell unit of IP packet do not include the IP packet three layers of head information and four layers
Head information is therefore, different from the non-head processing mode of cell unit to the first cell unit of same IP packet.Optionally, to working as
When preceding cell unit is scheduled, first determine whether current cell unit whether be corresponding IP packet first cell unit, if worked as
Preceding cell unit is first cell unit, then carries out packet parsing to current cell unit according to message format, parsing is obtained
The message attribute information of IP packet carries out network address translation processing, obtains new IP packet attribute information, and new IP is reported
Literary attribute information re-writes in current cell unit, and constructs assembling message structure according to current cell unit；If current
Cell unit is not first cell unit, then is directly added in the tail portion of the assembling message structure with current cell units match current
Cell unit.
Optionally, the message attribute information of IP packet parsing obtained carries out network address translation processing, obtains new
IP packet attribute information, and new IP packet attribute information is re-write into current cell unit, it can specifically include: will parse
Obtained IP packet attribute information is matched with network address translation table, if successful match, is obtained and is believed with IP packet attribute
Corresponding conversion IP packet attribute information is ceased, and is re-write in current cell unit；It is if it fails to match, current cell is mono-
The value of ethernet type parameter in member is set as target value, and the message data in current cell unit is returned to network and is handed over
Chip is changed, network exchanging chip, will be in current cell unit after confirming currently received packet network address conversion failure
Message is reported to CPU, is re-established network address translation table by CPU and is updated, so that in current cell unit
Message can successfully carry out network address translation.Wherein, conversion IP packet attribute information may include: new IP information, it is new
TCP/UDP port information, new IP verification and with new TCP/UDP verification and.
Optionally, the target value in ethernet type parameter can be set to 0, pass through Ethernet interface with FPGA for notifying
List item corresponding with current cell unit is not present in connected network exchanging chip network address translation table, needs network exchange
Chip adds network address corresponding with the IP packet attribute information of current cell unit in the network address translation table of FPGA
Transformation table entries.
Fig. 2 c is the concrete function structure chart for the FPGA that the method for the embodiment of the present invention is applicable in, specifically, such as Fig. 2 c institute
Show:
Message cutting cell module respectively from 4 Ethernet interfaces receive IP packet data data0, data1, data2,
Received 4 tunnel IP packet data are distinguished the cell unit that cutting is multiple fixed length according to ethernet port sequence by data3, and
The cell unit of cutting is sent to heading parsing module 1.Heading parsing module 1 is receiving message cutting cell module
After the cell unit of the corresponding IP packet cutting of the present port of transmission, packet parsing is carried out to received head cell unit, is obtained
To the three layers of head information and four layers of head information of the corresponding IP packet of present port, and by the head information of obtained IP packet and
Corresponding cell unit is sent to packet buffer management module and is cached.
Head of the packet buffer management module in the corresponding IP packet of present port for receiving the transmission of heading parsing module 1
After information and corresponding cell unit, storage location of the first cell unit in the cell pointer chained list of present port is found,
By the storage location in head cell unit deposit packet buffer region, meanwhile, by port cell corresponding to present port
Element number is initialized as 1.It, will be mono- with the head cell after the head cell unit is stored in the packet buffer region of corresponding ports
Other cell units that member belongs to same IP packet pass sequentially through from free pointer chained list and obtain free pointer, are connected in series to the head
Behind cell unit pointer chained list where cell unit, meanwhile, one non-head cell unit of every storage is just by present port institute
Corresponding port cell element number increases 1 certainly.After completing to the storage of the corresponding IP packet data of present port, front end will be worked as
Port cell element number corresponding to mouthful is stored to control information storage area.
All cell units of IP packet corresponding to present port are all stored to after packet buffer region, on the one hand,
Message cutting cell module continues to carry out the cutting of cell unit to the corresponding IP packet data of lower Single port according to port order, separately
On the one hand, the cell unit of IP packet corresponding to present port begins participating in cell cell scheduling.
Packet buffer management module obtains a port as target port according to port order, judges that target port institute is right
Whether the port cell element number answered is 0, if cell element number in port corresponding to target port is 0, illustrates target side
Mouth does not have the cell unit that can be dispatched in corresponding packet buffer area, then target port continues without cell cell scheduling
Select next port as target port；If cell element number in port corresponding to target port is greater than 0, illustrate target side
There is the cell unit that can be scheduled in corresponding packet buffer area in mouth, at this point, detecting whether to receive and target port
The scheduling controlling instruction matched, instructs if receiving with the matched scheduling controlling of target port, obtained in packet buffer area with
The corresponding cell unit of target port is as current cell unit, and until being dispatched to target port next time to current cell
Unit is scheduled.It is instructed if being not received by with the matched scheduling controlling of target port, direct regulation goal port is worked as
Preceding cell unit to be scheduled, meanwhile, when packet buffer management module dispatches a cell unit from packet buffer area, control
Port cell element number corresponding to target port in information storage area processed subtracts 1.
Packet buffer management module judge current cell unit whether be corresponding IP packet first cell unit, if currently
Cell unit is first cell unit, then current cell unit is sent to heading parsing module 2, by heading parsing module 2
Packet parsing is carried out to current cell unit, obtains the heading information of IP packet, and current cell unit is obtained with parsing
The heading information of IP packet send jointly to network address translation table searching module, network address translation table searching module will
It parses obtained IP packet head information to be matched with network address translation table, if successful match, obtains and believe with IP packet head
Corresponding conversion IP packet head information is ceased, and conversion IP packet head information and current cell unit are sent to first cell together and compiled
Module is collected, is re-write in current cell unit by first cell editor module by IP packet head information is converted, and will be modified
Current cell unit is sent to cell reconstructed file module, and cell reconstructed file module constructs assembling report according to current cell unit
Literary structure；If it fails to match with network address translation table for the IP packet head information that parsing obtains, head cell editor module will work as
The value of ethernet type parameter in preceding cell unit is set as target value, and the message data in current cell unit is returned
To network exchanging chip, network exchanging chip is after confirming currently received packet network address conversion failure, by current cell
Message in unit is reported to CPU, is re-established network address translation table by CPU and is updated, so that current cell
Message in unit can successfully carry out network address translation；If current cell unit is not first cell unit, packet buffer
Current cell unit is directly sent to cell reconstructed file module by management module, cell reconstructed file module with current cell
Current cell unit is added in the tail portion of the assembling message structure of units match.
When whole cell unit corresponding with an IP packet is assembled to be completed, cell reconstructed file module by with IP
IP packet is forwarded by the corresponding port of message.
The embodiment of the present invention by FPGA by received IP packet cutting be multiple cell units, only belong to comprising IP
Property information first cell unit carry out packet parsing, network address translation table matching and message information modification after, again should
The mode that first cell unit and other cell units for belonging to same IP packet are forwarded after being combined, by sufficiently developing
The hardware capability of FPGA, solve processing speed when existing multi -CPU processing technique carries out network address translation to IP packet it is slow,
The problem of poor universality, realizes the effect for improving processing speed and versatility on the basis of reducing cost of implementation.
Embodiment three
Fig. 3 is that a kind of structure for IP packet network address conversion device based on FPGA that the embodiment of the present invention three provides is shown
It is intended to, the present embodiment is applicable to received IP packet cutting in FPGA be multiple cell, carries out message solution to first cell
Analysis, network address translation table matching and message information modification, with to IP packet carry out network address translation the case where.Such as Fig. 3
Shown, which is applied in FPGA, comprising:
Cutting module 310 is received, for receiving multiple IP packets parallel by multiple ethernet ports, and will be received each
It is multiple cell units that IP packet, which distinguishes cutting, includes IP packet attribute information in the first cell unit in the IP packet；
Memory module 320 is parsed, for carrying out packet parsing to each head cell unit, is obtained corresponding with head cell unit
IP packet attribute information, and by first cell unit and with first cell unit belong to other cell units of same IP packet according to
Port correspondence is stored in packet buffer area；
Schedule process module 330 successively obtains and one in packet buffer area for using port polling scheduling mechanism
The corresponding cell unit in port takes corresponding processing side as current cell unit, and according to the type of current cell unit
Formula carries out cell unit assembling processing to current cell unit；
Forwarding module 340, for passing through when determining that whole cell unit corresponding with an IP packet is assembled completion
IP packet is forwarded by port corresponding with IP packet.
The embodiment of the present invention by FPGA by received IP packet cutting be multiple cell units, only belong to comprising IP
Property information first cell unit carry out packet parsing, network address translation table matching and message information modification after, again should
The mode that first cell unit and other cell units for belonging to same IP packet are forwarded after being combined, by sufficiently developing
The hardware capability of FPGA, solve processing speed when existing multi -CPU processing technique carries out network address translation to IP packet it is slow,
The problem of poor universality, realizes the effect for improving processing speed and versatility on the basis of reducing cost of implementation.
On the basis of the various embodiments described above, further includes:
Parameter determination module, the bandwidth needed for confirming network address translation, according to the position of bandwidth calculation cell unit
Wide parameter, the working clock frequency parameter of FPGA and packet buffer area.
On the basis of the various embodiments described above, schedule process module 330 may include scheduling unit, resolution unit, conversion
Modify unit and recomposition unit；
Scheduling unit is used for according to port cell element number poll port, if the port cell unit number of present port
Amount is not 0, then dispatches a cell unit from present port, and otherwise, present port continues poll without cell cell scheduling
Next port；
Wherein, when a cell unit is stored in packet buffer area according to port is corresponding, the port cell of the port is mono-
First quantity adds 1, and when a cell of port is scheduled outgoing packet buffer area, the port cell element number of the port subtracts 1；
Resolution unit, if carrying out packet parsing to current cell unit for cell unit headed by current cell unit,
Obtain IP packet attribute information corresponding with current cell unit；
Conversion modification unit, the IP packet attribute information for obtaining parsing are matched with network address translation table,
If successful match, according to matching result, obtains conversion IP packet attribute information corresponding with the acquisition of IP packet attribute information and write
Enter in current cell unit；If it fails to match, target is set by the value of the ethernet type parameter in current cell unit
Value, and the message data in current cell unit is returned into network exchanging chip；
Wherein, converting in IP packet attribute information includes: new IP information, new TCP/UDP port information, the new school IP
Test and with new TCP/UDP verification and；
Wherein, the target value in ethernet type parameter is connected with the FPGA by Ethernet interface for notifying
Network exchanging chip added in the network address translation table of FPGA it is corresponding with the IP packet attribute information of current cell unit
Network address translation table item；
Recomposition unit, for being complete IP packet by the corresponding whole cell reconfiguration of cell of same IP packet.
Device provided in this embodiment is applicable to the method that above-mentioned any embodiment provides, and has corresponding function and has
Beneficial effect.
Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that
The invention is not limited to the specific embodiments described herein, be able to carry out for a person skilled in the art it is various it is apparent variation,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out by above embodiments to the present invention
It is described in further detail, but the present invention is not limited to the above embodiments only, without departing from the inventive concept, also
It may include more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.
Claims (10)
1. a kind of IP packet method for network address translation based on FPGA is applied in programmable logic device, which is characterized in that
Include:
Multiple IP packets are received parallel by multiple ethernet ports, and are multiple by received each IP packet difference cutting
Cell unit includes IP packet attribute information in the first cell unit in the IP packet；
Packet parsing is carried out to each head cell unit, obtains IP packet attribute information corresponding with the head cell unit,
And belong to other cell units of same IP packet according to port pair by the head cell unit and with the head cell unit
It should be stored in packet buffer area；
Using port polling scheduling mechanism, successively cell unit corresponding with a port is obtained in packet buffer area and is used as and is worked as
Preceding cell unit, and according to the type of the current cell unit, take corresponding processing mode to the current cell unit
Carry out cell unit assembling processing；
When determining that whole cell unit corresponding with an IP packet is assembled completion, pass through end corresponding with the IP packet
The IP packet is forwarded by mouth.
2. the method according to claim 1, wherein taking correspondence according to the type of the current cell unit
Processing mode cell unit assembling processing is carried out to the current cell unit, comprising:
If cell unit headed by current cell unit, packet parsing is carried out to the current cell unit, parsing is obtained
IP packet attribute information carry out network address translation, obtaining new IP packet attribute information, to re-write the current cell mono-
Member, and according to the current cell unit construction assembling message structure；
If the current cell unit not headed by cell unit, in the assembling message knot with the current cell units match
The current cell unit is added in the tail portion of structure.
3. according to the method described in claim 2, it is characterized in that, using port polling scheduling mechanism, successively in packet buffer
Cell unit corresponding with a port is obtained in area as current cell unit, is specifically included:
When determining poll to target port using port polling scheduling mechanism, detect whether to receive and the target port
The scheduling controlling instruction matched；
If so, it is mono- as current cell to obtain cell unit corresponding with the target port in the packet buffer area
Member；
Wherein, the scheduling controlling instruction is raw when packet buffer area non-empty corresponding to the target port of current scheduling
At.
4. method according to claim 1-3, which is characterized in that by the head cell unit and with it is described
After other cell units that first cell unit belongs to same IP packet are stored in packet buffer area according to port is corresponding, also wrap
It includes:
It is determining to be reported with the IP after determining that cell unit corresponding with same IP packet is all cached in the packet buffer area
The corresponding cell unit of text participates in port polling scheduling.
5. according to the method described in claim 2, it is characterized in that, the IP packet attribute information that parsing is obtained carries out net
Network address conversion obtains new IP packet attribute information and re-writes the current cell unit, comprising:
The IP packet attribute information that parsing obtains is matched with network address translation table, if successful match, basis
Matching result obtains conversion IP packet attribute information corresponding with the IP packet attribute information and the current cell unit is written
In；
It wherein, include: new IP information, new TCP/UDP port information, the new school IP in the conversion IP packet attribute information
Test and with new TCP/UDP verification and；
If it fails to match, target value is set by the value of the ethernet type parameter in the current cell unit, and will work as
Message data in preceding cell unit returns to network exchanging chip；
Wherein, the target value in the ethernet type parameter passes through the Ethernet interface with the FPGA for notifying
Connected network exchanging chip is added and the IP packet of the current cell unit in the network address translation table of the FPGA
The corresponding network address translation table item of attribute information.
6. the method according to claim 1, wherein described use port polling scheduling mechanism, successively in message
Cell unit corresponding with a port is obtained in buffer area as current cell unit, comprising:
According to port cell element number poll port, if the port cell element number of present port is not 0, from working as front end
Mouth one cell unit of scheduling, otherwise, present port continues poll next port without cell cell scheduling；
Wherein, when a cell unit is stored in packet buffer area according to port is corresponding, the port cell unit number of the port
Amount plus 1, when a cell of port is scheduled outgoing packet buffer area, the port cell element number of the port subtracts 1.
7. the method according to claim 1, wherein receiving multiple IP reports parallel by multiple ethernet ports
Before text, further includes:
The desired bandwidth for confirming network address translation calculates the bit wide parameter of cell unit, FPGA according to the desired bandwidth
Working clock frequency parameter and packet buffer area；
Wherein, the packet buffer area includes FPGA internal RAM and outside DDR.
8. the method according to claim 1, wherein by the head cell unit and with the head cell unit
Other cell units for belonging to same IP packet are stored in packet buffer area according to port correspondence, comprising:
By the packet buffer region of head cell unit deposit corresponding ports；
Belong to other cell units of same IP packet by referring to from the free pointer chained list acquisition free time with the head cell unit
Needle is connected in series to the cell unit pointer chained list of corresponding ports；
Wherein, it is slow in the message of the corresponding ports to be directed toward head cell unit for the first pointer in the cell unit pointer chained list
Deposit the storage location in region.
9. by received each IP packet difference cutting being more the method according to claim 1, wherein described
A cell unit, comprising:
A port is obtained as target port according to port order；
It will be multiple cell units by the received IP packet cutting of the target port, and the multiple detecting
When cell unit is stored entirely in packet buffer area corresponding with the target port, returns to execution and obtained according to port order
Operation of a port as target port ends processing condition until meeting.
10. a kind of IP packet network address conversion device based on FPGA is applied in programmable logic device, feature exists
In, comprising:
Cutting module is received, for receiving multiple IP packets parallel by multiple ethernet ports, and by received each IP
It is multiple cell units that message, which distinguishes cutting, includes IP packet attribute information in the first cell unit in the IP packet；
Memory module is parsed, for carrying out packet parsing to each head cell unit, is obtained corresponding with the head cell unit
IP packet attribute information, and belong to other of same IP packet by the head cell unit and with the head cell unit
Cell unit is stored in packet buffer area according to port correspondence；
Schedule process module successively obtains and a port pair in packet buffer area for using port polling scheduling mechanism
The cell unit answered takes corresponding processing mode as current cell unit, and according to the type of the current cell unit
Cell unit assembling processing is carried out to the current cell unit；
Forwarding module, for when determining that corresponding with an IP packet whole cell unit is assembled completion, by with it is described
The IP packet is forwarded by the corresponding port of IP packet.
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