CN109473483B - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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CN109473483B
CN109473483B CN201710803403.3A CN201710803403A CN109473483B CN 109473483 B CN109473483 B CN 109473483B CN 201710803403 A CN201710803403 A CN 201710803403A CN 109473483 B CN109473483 B CN 109473483B
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gallium nitride
nitride layer
cathode electrode
semiconductor device
layer
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CN109473483A (en
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邱建维
林鑫成
林永豪
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Vanguard International Semiconductor Corp
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Vanguard International Semiconductor Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/872Schottky diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/207Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds further characterised by the doping material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66196Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
    • H01L29/66204Diodes
    • H01L29/66212Schottky diodes

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
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Abstract

The invention provides a semiconductor device and a manufacturing method thereof, wherein the semiconductor device comprises a first gallium nitride layer arranged on a semiconductor substrate, wherein the first gallium nitride layer has a first conduction type, a second gallium nitride layer arranged on the first gallium nitride layer, the second gallium nitride layer has the first conduction type, the dopant concentration of the first gallium nitride layer is higher than that of the second gallium nitride layer, an anode electrode arranged on the second gallium nitride layer, a cathode electrode arranged on the first gallium nitride layer and directly contacting the first gallium nitride layer, and an insulating region arranged on the first gallium nitride layer and directly contacting the first gallium nitride layer, wherein the insulating region is positioned between the cathode electrode and the second gallium nitride layer.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The present invention relates to a semiconductor device, and more particularly, to a semi-vertical (semi-vertical) semiconductor device and a method for manufacturing the same.
Background
In the semiconductor industry, semiconductor devices can be classified into horizontal or vertical structures according to the direction of current flow, and the horizontal structure semiconductor device has the advantage of lower die cost compared to the vertical structure semiconductor device, but is prone to decrease the current density per unit area due to the current crowding effect (current crowding).
In addition, the progress of semiconductor devices and manufacturing techniques in the past decades has made the circuits smaller and more complex, and in order to reduce the device size and save the process cost, it is the direction of effort to increase the current density per unit area of the semiconductor device.
Disclosure of Invention
Embodiments of a semiconductor device and methods of fabricating the same, particularly a semi-vertical Schottky diode, are provided. The current density per unit area of the conventional horizontal gan schottky diode is easily decreased by the current crowding effect. In order to increase the current density per unit area of the gan schottky diode, in an embodiment of the present invention, a first gan layer is disposed on a semiconductor substrate, a second gan layer is disposed on the first gan layer, the first gan layer and the second gan layer have the same conductivity type, for example, N-type, and the dopant concentration of the first gan layer is higher than that of the second gan layer.
In addition, in the embodiments of the present invention, the bottom surface of the cathode electrode is set to be lower than the bottom surface of the anode electrode in the gan schottky diode, so that the entire gan schottky diode has a semi-vertical structure, which is different from the conventional two-dimensional electron gas (2DEG) generated by the difference of the band gap of the heterogeneous material. Therefore, the embodiment of the invention overcomes the current crowding effect problem of the horizontal structure by the semi-vertical structure, so as to effectively improve the current density per unit area.
Furthermore, embodiments of the present invention use gan to fabricate schottky diodes, which have the advantage of lower die cost compared to sic schottky diodes.
According to some embodiments, a semiconductor device is provided. The semiconductor device includes a first gallium nitride layer disposed on a semiconductor substrate, wherein the first gallium nitride layer has a first conductivity type. The semiconductor device also includes a second gallium nitride layer disposed on the first gallium nitride layer, wherein the second gallium nitride layer has the first conductivity type, and a dopant concentration of the first gallium nitride layer is higher than a dopant concentration of the second gallium nitride layer. The semiconductor device further comprises an anode electrode arranged on the second gallium nitride layer and a cathode electrode arranged on the first gallium nitride layer and directly contacting the first gallium nitride layer. In addition, the semiconductor device includes an insulating region disposed on and in direct contact with the first gallium nitride layer, wherein the insulating region is located between the cathode electrode and the second gallium nitride layer.
According to some embodiments, a method of manufacturing a semiconductor device is provided. The method for manufacturing the semiconductor device comprises the steps of forming a first gallium nitride layer on a semiconductor substrate, wherein the first gallium nitride layer has a first conductive type. The method also includes forming a second gallium nitride layer on the first gallium nitride layer, wherein the second gallium nitride layer has the first conductivity type and the dopant concentration of the first gallium nitride layer is higher than the dopant concentration of the second gallium nitride layer. The method further includes forming an anode electrode on the second gallium nitride layer and forming a cathode electrode on the first gallium nitride layer and in direct contact with the first gallium nitride layer. In addition, the method for manufacturing the semiconductor device comprises the step of forming an insulating region on the first gallium nitride layer and directly contacting the first gallium nitride layer, wherein the insulating region is positioned between the cathode electrode and the second gallium nitride layer.
According to the invention, through the difference of the dopant concentration, the current of the gallium nitride Schottky diode vertically flows downwards and then flows into the cathode electrode with a lower bottom surface position. Therefore, the embodiment of the invention overcomes the current crowding effect problem of the horizontal structure by the semi-vertical structure, so as to effectively improve the current density per unit area.
The semiconductor device of the present invention can be applied to various types of semiconductor devices, and in order to make the features and advantages of the present invention more comprehensible, embodiments applied to gan schottky diodes are specifically described below with reference to the accompanying drawings.
Drawings
The aspects of the embodiments of the present invention will be better understood from the following detailed description taken in conjunction with the accompanying drawings. It is noted that some components (features) may not be drawn to scale according to industry standard practice. In fact, the dimensions of the various elements may be increased or decreased for clarity of discussion.
FIG. 1 is a schematic sectional view showing a semiconductor device of a comparative example;
FIGS. 2A-2D are schematic cross-sectional views illustrating various stages in the formation of a semiconductor device, in accordance with some embodiments of the present invention;
fig. 3A-3D are schematic cross-sectional views illustrating stages in the formation of a semiconductor device, in accordance with further embodiments of the present invention.
Reference numerals:
100. 200, 300 to semiconductor devices;
101. 201, 301-semiconductor substrate;
103. 203, 303 to a buffer layer;
105-a gallium nitride layer;
107-aluminum gallium nitride layer;
109 to a cover layer;
111-a passivation layer;
113. 213, 313 to cathode electrode;
115. 215, 315 to anode electrode;
205. 305-a first gallium nitride layer;
207. 307 to a second gallium nitride layer;
209. 309-insulating material;
209 ', 309' insulation regions;
210-opening;
308-first recess;
310 to a second recess;
a-area;
t1, t 2-thickness.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different components of the provided semiconductor devices. Specific examples of components and arrangements thereof are described below to simplify the present embodiments. These are, of course, merely examples and are not intended to be limiting. For example, references in the description to a first element being formed on a second element may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements are formed between the first and second elements such that they are not in direct contact. In addition, embodiments of the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Some variations of the embodiments are described below. Like reference numerals are used to designate like elements in the various figures and described embodiments. It will be understood that additional operations may be provided before, during, or after the method, and that some of the recited operations may be substituted or deleted for other embodiments of the method.
Fig. 1 is a schematic sectional view showing a semiconductor device 100 of a comparative example. As shown in fig. 1, a semiconductor device 100, such as a gan schottky diode with a horizontal structure, includes a semiconductor substrate 101, a buffer layer 103 disposed on the semiconductor substrate 101, a gan layer 105 disposed on the buffer layer 103, an algan layer 107 disposed on the gan layer 105, a cap layer 109 disposed on the algan layer 107, and a passivation layer 111 disposed on the cap layer 109. In addition, the semiconductor device 100 also includes a cathode electrode 113 and an anode electrode 115 disposed on the aluminum gallium nitride layer 107, wherein the cathode electrode 113 and the anode electrode 115 extend into the aluminum gallium nitride layer 107, i.e., the bottom surfaces of the cathode electrode 113 and the anode electrode 115 are lower than the top surface of the aluminum gallium nitride layer 107.
As shown in fig. 1, the current of the semiconductor device 100 flows from the anode electrode 115, flows through the aluminum gallium nitride layer 107 under the anode electrode 115 to the gallium nitride layer 105 (the gallium nitride layer 105 is equivalent to the channel layer of the semiconductor device 100), then flows horizontally through the surface of the gallium nitride layer 105 close to the aluminum gallium nitride layer 107, and flows into the cathode electrode 113 through the aluminum gallium nitride layer 107 under the cathode electrode 113.
The semiconductor device 100 generates a current of two-dimensional electron gas (2DEG) through a difference in energy gap between heterogeneous materials, such as the gallium nitride layer 105 and the aluminum gallium nitride layer 107, and the horizontal structure easily generates a current crowding effect at a corner of the cathode electrode 113 near the anode electrode 115 and the aluminum gallium nitride layer 107, i.e., the region a shown in fig. 1. Therefore, the semiconductor device 100, such as a gan schottky diode with a horizontal structure, needs to overcome the problem of low current density per unit area.
Fig. 2A-2D are schematic cross-sectional views illustrating various stages in the formation of a semiconductor device 200, in accordance with some embodiments of the present invention.
According to some embodiments, such as2A, a semiconductor substrate 201 is provided. In some embodiments, the semiconductor substrate 201 may be made of silicon (Si), silicon carbide (SiC), gallium nitride (GaN), silicon dioxide (SiO)2) Sapphire (Sapphire), or a combination of the foregoing. In addition, the semiconductor substrate 201 may be a lightly doped P-type or N-type substrate.
Next, a seed layer (not shown) is formed on the semiconductor substrate 201, and a buffer layer 203 is formed on the seed layer. In some embodiments, the seed layer and the buffer layer 203 are formed by Metal Organic Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE), or a combination thereof. The seed layer may be made of aluminum nitride (AlN), aluminum oxide (Al)2O3) Aluminum gallium nitride (AlGaN), silicon carbide (SiC), aluminum (Al), or combinations thereof, and the seed layer may be a single or multi-layer structure.
The material of the buffer layer 203 is determined by the material of the seed layer and the gas introduced during the epitaxial process. In some embodiments, the buffer layer 203 may be formed of aluminum nitride (AlN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum indium gallium nitride (InAlGaN), or a combination thereof. In some embodiments, the buffer layer 203 may be a multi-layer structure doped with carbon, silicon, magnesium, or iron. In some embodiments, the thickness of the buffer layer 203 is in a range from about 1 micron to about 20 microns.
Referring again to fig. 2A, a first gallium nitride layer 205 is formed on the buffer layer 203, and a second gallium nitride layer 207 is formed on the first gallium nitride layer 205. It is noted that an N-type dopant, such As phosphorus (P) or arsenic (As), is implanted in the first gallium nitride layer 205 and the second gallium nitride layer 207, and the dopant concentration of the first gallium nitride layer 205 is higher than that of the second gallium nitride layer 207. In some embodiments, the dopant concentration of the first gallium nitride layer 205 is about 1x1019Atom/cubic centimeter (atom/cm)3) And the dopant concentration of the second gallium nitride layer 207 is about 1x1015Atom/cubic centimeter (atom/cm)3) To about 1x1018Atom/cubic centimeter (atom/cm)3) Within the range of (1).
In some embodiments, the thickness t of the second gallium nitride layer 2072Greater than the first nitrogenThickness t of gallium nitride layer 2051. In other embodiments, the thickness t of the second gallium nitride layer 2072May be less than or equal to the thickness t of the first gallium nitride layer 2051
According to some embodiments, as shown in fig. 2B, an implantation isolation (implantation isolation) process is performed to implant oxygen ions into a portion of the second gallium nitride layer 207, such that the portion of the second gallium nitride layer 207 is converted into the insulating material 209. In some embodiments, the insulating material 209 is a material of the second gallium nitride layer 207 doped with oxygen ions. In other embodiments, the implantation isolation process may use other heavy ions, such as argon (Ar) ions.
Continuing with the above, as shown in fig. 2C, an opening 210 is formed in the insulating material 209 to expose a portion of the first gallium nitride layer 205. In some embodiments, the opening 210 may be formed by a process of photolithography and etching, and the etching process may include dry etching or wet etching. After the opening 210 is formed, the remaining insulating material 209 is an insulating region 209'.
According to some embodiments, as shown in fig. 2D, a cathode electrode 213 is formed within the opening 210, the cathode electrode 213 being located on the first gallium nitride layer 205 and directly contacting the first gallium nitride layer 205, and an anode electrode 215 is formed on the second gallium nitride layer 207. Specifically, the insulating region 209 'is located between the cathode electrode 213 and the second gallium nitride layer 207, and the insulating region 209' surrounds the cathode electrode 213 such that the cathode electrode 213 is spaced apart from the second gallium nitride layer 207. Further, the bottom surface of the cathode electrode 213 is lower than the bottom surface of the anode electrode 215.
In some embodiments, as shown in fig. 2D, the cathode electrode 213 extends to the left and right insulating regions 209', and the top surface of the cathode electrode 213 is higher than the top surface of the second gallium nitride layer 207. In other embodiments, the cathode electrode 213 does not extend to the left and right insulating regions 209', and the top surface of the cathode electrode 213 is horizontal to the top surface of the second gallium nitride layer 207.
In some embodiments, the cathode electrode 213 and the anode electrode 215 are formed using Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), electroplating (electroplating), sputtering (sputtering), or other suitable methods. In addition, the cathode electrode 213 and the anode electrode 215 may include a metal material.
It is noted that the anode electrode 215 may be made of a metal material with a higher work function than the cathode electrode 215, such that an Ohmic contact (Ohmic contact) is formed between the cathode electrode 213 and the first gallium nitride layer 205, and a Schottky contact (Schottky contact) is formed between the anode electrode 215 and the second gallium nitride layer 207. For example, the cathode electrode 213 may be formed of titanium (Ti), aluminum (Al), or a combination thereof, and the anode electrode 215 may be formed of nickel (Ni), gold (Au), or a combination thereof.
Referring again to fig. 2D, the current of the semiconductor device 200 flows from the anode electrode 215, vertically flows through the second gallium nitride layer 207 below the anode electrode 215, and then horizontally flows through the first gallium nitride layer 205 near the surface of the second gallium nitride layer 207 and then flows into the cathode electrode 213. Since the semiconductor device 200 has a semi-vertical structure, the current crowding effect of the horizontal structure can be effectively overcome, so that the current density per unit area can be improved.
Fig. 3A-3D are schematic cross-sectional views illustrating various stages in the formation of a semiconductor device 300, in accordance with further embodiments of the present invention.
As shown in fig. 3A, a buffer layer 303, a first gallium nitride layer 305, and a second gallium nitride layer 307 are sequentially disposed on a semiconductor substrate 301, and a first recess 308 is formed in the second gallium nitride layer 307, the first recess 308 exposing a portion of the first gallium nitride layer 305. In some embodiments, the first recess 308 may be formed by a process of photolithography and etching, which may include dry etching or wet etching. The materials and processes of the semiconductor substrate 301, the buffer layer 303, the first gallium nitride layer 305, and the second gallium nitride layer 307 may be similar or identical to those of the semiconductor substrate 201, the buffer layer 203, the first gallium nitride layer 205, and the second gallium nitride layer 207 of fig. 2A, and thus are not repeated herein.
According to some embodiments, as shown in fig. 3B, the first recess 308 is filled with an insulating material 309. The insulating material 309 is formed using Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), High Density Plasma Chemical Vapor Deposition (HDPCVD) process, Metal Organic Chemical Vapor Deposition (MOCVD) process, Plasma Enhanced Chemical Vapor Deposition (PECVD) process, or a combination thereof.
It is noted that, unlike the semiconductor device 200, the insulating material 309 of the semiconductor device 300 is not transformed by the material of the second gallium nitride layer 307. In some embodiments, the insulating material 309 may comprise silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or other suitable insulating materials. In addition, after the insulating material 309 is filled into the first recess 308, a planarization process, such as a Chemical Mechanical Polishing (CMP) process, may be optionally performed to remove the insulating material 309 on the second gallium nitride layer 307.
Subsequently, as shown in fig. 3C, a portion of the insulating material 309 is removed to form a second recess 310 in the insulating material 309, wherein the second recess 310 exposes a portion of the first gan layer 305, and the remaining insulating material 309 forms an insulating region 309'. In some embodiments, the second recess 310 may be formed in a similar or identical manner to the first recess 308, which is not repeated herein.
According to some embodiments, as shown in fig. 3D, a cathode electrode 313 is formed within the second recess 310, the cathode electrode 313 being located on the first gallium nitride layer 305 and directly contacting the first gallium nitride layer 305, and an anode electrode 315 is formed on the second gallium nitride layer 307. Specifically, the insulating region 309' is located between the cathode electrode 313 and the second gallium nitride layer 307, such that the cathode electrode 313 is spaced apart from the second gallium nitride layer 307. Further, the bottom surface of the cathode electrode 313 is lower than the bottom surface of the anode electrode 315.
In some embodiments, as shown in fig. 3D, the cathode electrode 313 extends onto the insulating region 309', and a top surface of the cathode electrode 313 is higher than a top surface of the second gallium nitride layer 307. In other embodiments, the cathode electrode 313 does not extend onto the insulating region 309', and a top surface of the cathode electrode 313 is horizontal to a top surface of the second gallium nitride layer 307.
In addition, the materials and processes of the cathode electrode 313 and the anode electrode 315 may be similar or identical to those of the cathode electrode 213 and the anode electrode 215, which are not described herein again.
Referring again to fig. 3D, the current of the semiconductor device 300 flows from the anode electrode 315, vertically flows through the second gallium nitride layer 307 under the anode electrode 315, and then horizontally flows through the first gallium nitride layer 305 near the surface of the second gallium nitride layer 307 and then flows into the cathode electrode 313. Since the semiconductor device 300 has a semi-vertical structure, the current crowding effect of the horizontal structure can be effectively overcome, so that the current density per unit area can be improved.
The current density per unit area of the conventional horizontal gan schottky diode is easily decreased by the current crowding effect. In order to increase the current density per unit area of the gan schottky diode, in an embodiment of the present invention, a first gan layer is disposed on a semiconductor substrate, a second gan layer is disposed on the first gan layer, the first gan layer and the second gan layer have the same conductivity type, for example, N-type, and the dopant concentration of the first gan layer is higher than that of the second gan layer.
In addition, in the embodiment of the invention, the bottom surface of the cathode electrode is set to be lower than the bottom surface of the anode electrode in the gan schottky diode, so that the whole gan schottky diode has a semi-vertical structure, and the current of the gan schottky diode is enabled to vertically flow downwards through the difference of the dopant concentration and then flows into the cathode electrode with the lower bottom surface position, unlike the two-dimensional electron gas (2DEG) generated through the energy gap difference of the foreign material in the prior art. Therefore, the embodiment of the invention overcomes the current crowding effect problem of the horizontal structure by the semi-vertical structure, so as to effectively improve the current density per unit area.
Furthermore, embodiments of the present invention use gan to fabricate schottky diodes, which have the advantage of lower die cost compared to sic schottky diodes.
The foregoing outlines several embodiments so that those skilled in the art may better understand the aspects of the present embodiments. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present invention.

Claims (17)

1. A semiconductor device, comprising:
a first gallium nitride layer disposed on a semiconductor substrate, wherein the first gallium nitride layer has a first conductivity type;
a second gallium nitride layer disposed on the first gallium nitride layer, wherein the second gallium nitride layer has the first conductivity type, and the dopant concentration of the first gallium nitride layer is higher than that of the second gallium nitride layer;
an anode electrode disposed on the second gallium nitride layer;
the cathode electrode is arranged on the first gallium nitride layer and is directly contacted with the first gallium nitride layer, wherein the top surface of the cathode electrode is higher than that of the second gallium nitride layer, and the top surface of the cathode electrode is horizontal to that of the anode electrode; and
and the insulating region is arranged on the first gallium nitride layer and is directly contacted with the first gallium nitride layer, wherein the insulating region is positioned between the cathode electrode and the second gallium nitride layer, and the cathode electrode completely covers the insulating region.
2. The semiconductor device of claim 1, wherein the first conductivity type is N-type.
3. The semiconductor device of claim 1, wherein the insulating region surrounds the cathode electrode.
4. The semiconductor device according to claim 1, wherein a material of the insulating region is a material of the second gallium nitride layer doped with oxygen ions.
5. The semiconductor device of claim 1, wherein a thickness of the second gallium nitride layer is greater than a thickness of the first gallium nitride layer.
6. The semiconductor device according to claim 1, wherein the anode electrode is in schottky contact with the second gallium nitride layer, and the cathode electrode is in ohmic contact with the first gallium nitride layer.
7. The semiconductor device of claim 1, further comprising:
and the buffer layer is arranged between the semiconductor substrate and the first gallium nitride layer.
8. The semiconductor device according to claim 1, wherein a bottom surface of the cathode electrode is lower than a bottom surface of the anode electrode.
9. A method for manufacturing a semiconductor device, comprising:
forming a first gallium nitride layer on a semiconductor substrate, wherein the first gallium nitride layer has a first conductivity type;
forming a second gallium nitride layer on the first gallium nitride layer, wherein the second gallium nitride layer has the first conductive type, and the dopant concentration of the first gallium nitride layer is higher than that of the second gallium nitride layer;
forming an anode electrode on the second gallium nitride layer;
forming a cathode electrode on the first gallium nitride layer and directly contacting the first gallium nitride layer, wherein the top surface of the cathode electrode is higher than the top surface of the second gallium nitride layer, and the top surface of the cathode electrode is horizontal to the top surface of the anode electrode; and
and forming an insulating region on the first gallium nitride layer and directly contacting the first gallium nitride layer, wherein the insulating region is located between the cathode electrode and the second gallium nitride layer, and the cathode electrode completely covers the insulating region.
10. The method of claim 9, wherein the first conductivity type is N-type.
11. The method of manufacturing a semiconductor device according to claim 9, wherein the step of forming the cathode electrode comprises:
forming a first recess in the second GaN layer;
filling an insulating material into the first recess;
removing a portion of the insulating material to form a second recess in the insulating material, wherein the second recess exposes the first gallium nitride layer and the remaining insulating material forms the insulating region; and
the cathode electrode is formed in the second recess.
12. The method of manufacturing a semiconductor device according to claim 9, wherein the step of forming the cathode electrode comprises:
performing an implantation isolation process to convert a portion of the second gallium nitride layer into an insulating material;
forming an opening in the insulating material to expose the first GaN layer and form the insulating region; and
the cathode electrode is formed within the opening, wherein the insulating region surrounds the cathode electrode.
13. The method of claim 12, wherein the implantation isolation process implants oxygen ions into the portion of the second gallium nitride layer.
14. The method of manufacturing a semiconductor device according to claim 9, wherein a thickness of the second gallium nitride layer is larger than a thickness of the first gallium nitride layer.
15. The method according to claim 9, wherein a schottky contact is formed between the anode electrode and the second gallium nitride layer, and an ohmic contact is formed between the cathode electrode and the first gallium nitride layer.
16. The method of manufacturing a semiconductor device according to claim 9, further comprising:
a buffer layer is formed between the semiconductor substrate and the first GaN layer.
17. The method of manufacturing a semiconductor device according to claim 9, wherein a bottom surface of the cathode electrode is lower than a bottom surface of the anode electrode.
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