CN109326595A - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN109326595A
CN109326595A CN201710637712.8A CN201710637712A CN109326595A CN 109326595 A CN109326595 A CN 109326595A CN 201710637712 A CN201710637712 A CN 201710637712A CN 109326595 A CN109326595 A CN 109326595A
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grid
semiconductor element
dielectric layer
thickness
groove
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CN109326595B (zh
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吕佐文
林哲平
詹电针
詹书俨
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Priority to US15/876,216 priority patent/US10373958B2/en
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Priority to US16/443,880 priority patent/US10847517B2/en
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Abstract

本发明公开一种半导体元件及其制作方法。该半导体元件包含：一半导体基底，其上具有一栅极沟槽，该栅极沟槽包含一上沟槽及一下沟槽，其中该上沟槽较该下沟槽宽；一栅极，嵌入于该栅极沟槽中，其中该栅极包含一栅极上部及一栅极下部；一第一栅极介电层，设于该栅极上部与该上沟槽的侧壁之间，其中该第一栅极介电层具有一第一厚度；及一第二栅极介电层，设于该栅极下部与该下沟槽的侧壁之间，其中该第二栅极介电层具有一第二厚度，且该第二厚度小于该第一厚度。

Description

半导体元件及其制作方法
技术领域
本发明涉及半导体制作工艺技术领域，特别是涉及一种半导体元件及其制作方法。
背景技术
埋入式字符线(buried wordline)结构常应用于在动态随机存取存储器(DRAM)中，用以减少短通道效应(short channel effect)对高密度存储器阵列区(memory array)造成的影响。对于埋入式字符线结构而言，关键在于栅极介电层的品质提升及厚度的控制。
栅极介电层的品质提升及厚度控制与元件的电性表现及控制息息相关，特别是在栅极引发漏极漏电流(GIDL)及临界电压(Vt)控制问题的改善方面，该技术领域目前仍需要一有效的解决方案。
发明内容
本发明的主要目的在于提供一种改良的半导体元件及其制作方法，可以解决现有技术的不足。
根据本发明一实施例，提供一种半导体元件，包含：一半导体基底，其上具有一栅极沟槽，该栅极沟槽包含一上沟槽及一下沟槽，其中该上沟槽较该下沟槽宽；一栅极，嵌入于该栅极沟槽中，其中该栅极包含一栅极上部及一栅极下部；一第一栅极介电层，设于该栅极上部与该上沟槽的侧壁之间，其中该第一栅极介电层具有一第一厚度；及一第二栅极介电层，设于该栅极下部与该下沟槽的侧壁之间，其中该第二栅极介电层具有一第二厚度，且该第二厚度小于该第一厚度。
根据本发明另一实施例，提供一种制作半导体元件的方法。首先提供一半导体基底，再于该半导体基底中形成一上沟槽，再于该上沟槽的内壁面上沉积一第一栅极介电层，其中该第一栅极介电层具有一第一厚度，接着各向异性蚀刻该第一栅极介电层及该半导体基底，自动对准形成一下沟槽，其中该上沟槽及该下沟槽构成一栅极沟槽，再从该下沟槽的内壁面上以热成长方式，形成一第二栅极介电层，其中该第二栅极介电层具有一第二厚度，且该第二厚度小于该第一厚度。
为让本发明的上述目的、特征及优点能更明显易懂，下文特举优选实施方式，并配合所附的附图，作详细说明如下。然而如下的优选实施方式与附图仅供参考与说明用，并非用来对本发明加以限制者。
附图说明
图1为本发明一实施例所绘示的一种半导体元件的剖面示意图；
图2至图5为本发明另一实施例所绘示的一种制作半导体元件的方法的示意图。
主要元件符号说明
1 半导体元件
10 半导体基底
10a 上表面
101 P型区域
102 N型区域
200 栅极沟槽
210 上沟槽
220 下沟槽
230 过渡沟槽结构
300 栅极
300a 顶面
301 钨金属层
302 氮化钛衬层
310 栅极上部
320 栅极下部
400 凹陷区域
400a 顶面
410 上盖层
510 第一栅极介电层
510a 侧壁表面
520 第二栅极介电层
520a 侧壁表面
530 过渡厚度
d1 深度
d2 深度
t1 第一厚度
t2 第二厚度
w 宽度
w1 宽度
w2 宽度
具体实施方式
在下文中，将参照附图说明细节，该些附图中的内容也构成说明书细节描述的一部分，并且以可实行该实施例的特例描述方式来绘示。下文实施例已描述足够的细节使该领域的一般技术人士得以具以实施。
当然，也可采行其他的实施例，或是在不悖离文中所述实施例的前提下作出任何结构性、逻辑性、及电性上的改变。因此，下文的细节描述不应被视为是限制，反之，其中所包含的实施例将由随附的权利要求来加以界定。
请参阅图1，其为依据本发明一实施例所绘示的一种半导体元件1的剖面示意图。如图1所示，半导体元件1包含一半导体基底10，例如一硅基底，但不限于此。半导体基底10具有一上表面10a。根据本发明一实施例，上表面10a可以是由一硬掩模层所构成，但不限于此。
根据本发明一实施例，在半导体基底10上形成有一栅极沟槽200。根据本发明一实施例，在半导体基底10中可以形成有一P型区域101以及一N型区域102。例如，P型区域101可以是一P型阱，而N型区域102可以是N+漏极掺杂区或N+源极掺杂区，但不限于此。
根据本发明一实施例，栅极沟槽200包含一上沟槽210及一下沟槽220，其中上沟槽210的宽度w1较下沟槽220的宽度w2宽。在图1中，可以看出上沟槽210的深度d1约略等于P型区域101及N型区域102的交界处，但不限于此。
根据本发明一实施例，下沟槽220的深度则是从上沟槽210的深度d1位置再往下距离d2，因此下沟槽220的深度为d1+d2。根据本发明一实施例，下沟槽220位于P型区域101中且位于N型区域102的底部以下位置。
根据本发明一实施例，从上沟槽210的底部开始，连接至下沟槽220，可以有一从宽度w1渐缩至宽度w2的过渡沟槽结构230。
根据本发明一实施例，半导体元件1另包含一栅极300，嵌入于栅极沟槽200中。根据本发明一实施例，栅极300包含一栅极上部310及一栅极下部320。根据本发明一实施例，栅极300包含一顶面300a，其低于半导体基底10的上表面10a，形成一凹陷区域400。
根据本发明一实施例，栅极300的顶面300a被一上盖层410覆盖住。根据本发明一实施例，上盖层410填满位于栅极300的顶面300a以上的凹陷区域400。例如，上盖层400可以是一氮化硅层，但不限于此。根据本发明一实施例，上盖层400具有一顶面400a，其与半导体基底10的上表面10a齐平。
根据本发明一实施例，栅极300在栅极沟槽200中具有均一相同的宽度w。也就是说，栅极上部310的宽度等于栅极下部320的宽度。
根据本发明一实施例，半导体元件1另包含一第一栅极介电层510，设于栅极上部310与上沟槽210的侧壁之间，其中第一栅极介电层510具有一第一厚度t1。例如，第一厚度t1介于60埃(angstrom)至80埃。
根据本发明一实施例，半导体元件1另包含一第二栅极介电层520，设于栅极下部320与下沟槽220的侧壁之间，其中第二栅极介电层520具有一第二厚度t2，且第二厚度t2小于第一厚度t1。例如，第二厚度t2介于40埃至60埃。根据本发明一实施例，第二栅极介电层520的第二厚度t2可以包括对应前述过渡沟槽结构230从第一厚度t1渐薄至第一厚度t1的过渡厚度530。
根据本发明一实施例，第一栅极介电层510包含一原子层沉积(ALD)硅氧层，第二栅极介电层520包含一临场蒸汽产生(ISSG)硅氧层。根据本发明一实施例，第一栅极介电层510包含一侧壁表面510a，对准第二栅极介电层520的一侧壁表面520a。
根据本发明一实施例，栅极300可以包含一钨金属层301及一氮化钛衬层302，其中氮化钛衬层302介于钨金属层301与第一栅极介电层510间，且介于钨金属层301及第二栅极介电层520间。
本发明半导体元件1可以应用在动态随机存取存储器中，作为埋入式字符线，其中第一栅极介电层510较厚，可以改善栅极引发漏极漏电流(GIDL)问题，而利用临场蒸汽产生制作工艺形成的第二栅极介电层520，则是高品质的二氧化硅层，其厚度可以控制在所要目标范围，而改善临界电压控制问题。
请参阅图2至图5，其为依据本发明另一实施例所绘示的一种制作半导体元件的方法。
如图2所示，提供一半导体基底10，例如一硅基底，但不限于此。半导体基底10具有一上表面10a。根据本发明一实施例，在半导体基底10中可以形成有一P型区域101以及一N型区域102。例如，P型区域101可以是一P型阱，而N型区域102可以是N+漏极掺杂区或N+源极掺杂区，但不限于此。
接着，在半导体基底10中以光刻及蚀刻制作工艺形成一上沟槽210。上沟槽210具有一宽度w1。接着，在上沟槽210的内壁面上共形的沉积一第一栅极介电层510。例如，第一栅极介电层510可以是利用一原子层沉积(ALD)制作工艺沉积而成的二氧化硅层，但不限于此。其中第一栅极介电层510具有一第一厚度t1。例如，第一厚度t1介于60埃(angstrom)至80埃。
如图3所示，接着各向异性蚀刻第一栅极介电层510，在蚀穿第一栅极介电层510后，继续于蚀刻半导体基底，自动对准形成一下沟槽220，其中上沟槽210及下沟槽220构成一栅极沟槽200。
根据本发明一实施例，下沟槽220具有一宽度w2，其中上沟槽210的宽度w1较下沟槽220的宽度w2宽。在图3中，可以看出上沟槽210的深度d1约略位于P型区域101及N型区域102的交界处，但不限于此。
根据本发明一实施例，下沟槽220的深度则是从上沟槽210的深度d1位置再往下距离d2，因此下沟槽220的深度为d1+d2。根据本发明一实施例，下沟槽220位于P型区域101中且位于N型区域102的底部以下位置。
如图4所示，接着以临场蒸汽产生(ISSG)制作工艺从下沟槽220的内壁面上以热成长方式，形成一第二栅极介电层520。其中第二栅极介电层520具有一第二厚度t2，且第二厚度t2小于第一厚度t1。例如，第二厚度t2介于40埃至60埃。
此外，前述临场蒸汽产生制作工艺还可进一步改善第一栅极介电层510的薄膜品质，例如，可以修补第一栅极介电层510中的缺陷或使其结构上更加致密。在某些实施例中，经过前述临场蒸汽产生制作工艺后，第一栅极介电层510的厚度可能会稍微增加。
根据本发明一实施例，从上沟槽210的底部开始，连接至下沟槽220，可以有一从宽度w1渐缩至宽度w2的过渡沟槽结构230。第二栅极介电层520的第二厚度t2可以包括对应前述过渡沟槽结构230从第一厚度t1渐薄至第一厚度t1的过渡厚度530。
根据本发明一实施例，第一栅极介电层510包含一侧壁表面510a，对准第二栅极介电层520的一侧壁表面520a。
如图5，接着在栅极沟槽200形成一栅极300。根据本发明一实施例，栅极300可以包含一钨金属层301及一氮化钛衬层302，其中氮化钛衬层302介于钨金属层301与第一栅极介电层510间，且介于钨金属层301及第二栅极介电层520间。
根据本发明一实施例，栅极300嵌入于栅极沟槽200中。根据本发明一实施例，栅极300包含一栅极上部310及一栅极下部320。根据本发明一实施例，栅极300包含一顶面300a，其低于半导体基底10的上表面10a，形成一凹陷区域400。
根据本发明一实施例，栅极300的顶面300a被一上盖层410覆盖住。根据本发明一实施例，上盖层410填满位于栅极300的顶面300a以上的凹陷区域400。例如，上盖层400可以是一氮化硅层，但不限于此。根据本发明一实施例，上盖层400具有一顶面400a，其与半导体基底10的上表面10a齐平。
根据本发明一实施例，栅极300在栅极沟槽200中具有均一相同的宽度w。也就是说，栅极上部310的宽度等于栅极下部320的宽度。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (20)

1.一种半导体元件，包含：
半导体基底，其上具有栅极沟槽，该栅极沟槽包含上沟槽及下沟槽，其中该上沟槽较该下沟槽宽；
栅极，嵌入于该栅极沟槽中，其中该栅极包含栅极上部及栅极下部；
第一栅极介电层，设于该栅极上部与该上沟槽的侧壁之间，其中该第一栅极介电层具有一第一厚度；及
第二栅极介电层，设于该栅极下部与该下沟槽的侧壁之间，其中该第二栅极介电层具有一第二厚度，且该第二厚度小于该第一厚度。
2.如权利要求1所述的半导体元件，其中该栅极在该栅极沟槽中具有均一相同的宽度。
3.如权利要求2所述的半导体元件，其中该栅极上部的宽度等于该栅极下部的宽度。
4.如权利要求1所述的半导体元件，其中该栅极沟槽的宽度从上至下逐渐递减。
5.如权利要求1所述的半导体元件，其中该第一栅极介电层包含原子层沉积(ALD)硅氧层。
6.如权利要求5所述的半导体元件，其中该第一厚度介于60埃至80埃。
7.如权利要求1所述的半导体元件，其中该第二栅极介电层包含临场蒸汽产生(ISSG)硅氧层。
8.如权利要求7所述的半导体元件，其中该第二厚度介于40埃至60埃。
9.如权利要求1所述的半导体元件，其中该第一栅极介电层包含一侧壁表面，对准该第二栅极介电层的一侧壁表面。
10.如权利要求1所述的半导体元件，其中该栅极包含钨金属层及氮化钛衬层，该氮化钛衬层介于该钨金属层及该第一栅极介电层间，且介于该钨金属层及该第二栅极介电层间。
11.一种制作半导体元件的方法，包含：
提供一半导体基底；
在该半导体基底中形成一上沟槽；
在该上沟槽的内壁面上沉积一第一栅极介电层，其中该第一栅极介电层具有一第一厚度；
各向异性蚀刻该第一栅极介电层及该半导体基底，自动对准形成一下沟槽，其中该上沟槽及该下沟槽构成一栅极沟槽；及
从该下沟槽的内壁面上以热成长方式，形成一第二栅极介电层，其中该第二栅极介电层具有一第二厚度，且该第二厚度小于该第一厚度。
12.如权利要求11所述的制作半导体元件的方法，其中还包含：
在该栅极沟槽中形成一栅极，其中该栅极具有栅极上部及栅极下部。
13.如权利要求12所述的制作半导体元件的方法，其中该栅极在该栅极沟槽中具有均一相同的宽度。
14.如权利要求13所述的制作半导体元件的方法，其中该栅极上部的宽度等于该栅极下部的宽度。
15.如权利要求11所述的制作半导体元件的方法，其中该第一栅极介电层是利用一原子层沉积(ALD)制作工艺沉积而成。
16.如权利要求15所述的制作半导体元件的方法，其中该第一厚度介于60埃至80埃。
17.如权利要求11所述的制作半导体元件的方法，其中该第二栅极介电层是利用一临场蒸汽产生(ISSG)制作工艺形成。
18.如权利要求17所述的制作半导体元件的方法，其中该第二厚度介于40埃至60埃。
19.如权利要求11所述的制作半导体元件的方法，其中该第一栅极介电层包含一侧壁表面，对准该第二栅极介电层的一侧壁表面。
20.如权利要求12所述的制作半导体元件的方法，其中该栅极包含钨金属层及氮化钛衬层，该氮化钛衬层介于该钨金属层及该第一栅极介电层间，且介于该钨金属层及该第二栅极介电层间。
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