CN109154927A - Low delay multi-protocols retimer - Google Patents
Low delay multi-protocols retimer Download PDFInfo
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- CN109154927A CN109154927A CN201780030035.1A CN201780030035A CN109154927A CN 109154927 A CN109154927 A CN 109154927A CN 201780030035 A CN201780030035 A CN 201780030035A CN 109154927 A CN109154927 A CN 109154927A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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Abstract
Disclose a kind of multi-protocols retimer device and the method for using it.In one embodiment, a kind of for executing device when resetting between the first device and the second device according to multiple agreements includes: that can operate to receive the receiver of data；For sending the transmitter of data；First data path, it is coupled to receiver and transmitter, and it can operate so that during the specific training of agreement transmitter will be transferred to from the received data of receiver, wherein, first data path includes control circuit, the specific training of agreement for one or two of controlling transmitters and receivers in response to the instruction to an agreement in multiple agreements；And second data path, it is coupled to receiver and transmitter, the second data path has a delay lower than the first data path, and for that will be transferred to transmitter from the received data of receiver after training agreement is specific.
Description
Technical field
The embodiment of the present invention is related to the field of the interface for computer system；More specifically, implementation of the invention
Example is related to can be configured as the retimer for transmitting data according to multiple agreements.
Background technique
With the frequency increase of computer system external interface and channel improvement is while keeping backward compatibility
Continue to keep appropriateness, increased in the interface using the demand of retimer.For example, quick (PCIe) the of peripheral component interface
In 4 generations (wherein, interface is operated with 16.0GT/s), are for most of server channels (usually 20 " FR4, there are two connectors for tool)
Need retimer.Universal serial bus (USB) version 3 .1 is operated with 10GT/s, and most of platforms have been needed
Retimer.For some in the platform that is operated with 10.4GT/s, other interfaces need some form of expansion equipment.
All there are multiple challenges in each of these interfaces.It is slow for the high speed of such as super path interconnection (UPI) etc
Consistency protocol is deposited, every retimer jumps the additional delay of about 30nsec so that it is difficult to due to unacceptable performance loss
It maintains.Even if having the PCIe for some memory applications, delay has also been problem, and due to next-generation non-volatile
Memory (NVM) technology provides higher bandwidth and lower delay, is stored with Double Data Rate synchronous dynamic random-access
Device (DDR SDRAM) narrows the gap, and delay is expected to become more serious.Analog switching driver does not have latency issue.However, by
It is not involved in link initialization and balance stage in it, therefore analog switching driver cannot re-create transmitter equalization space,
This is different from re-timer, and therefore will have restricted use, especially in open socket/connector type
In the case where system.
Second challenge is by the multi protocol supporting of different physical layers (PHY), as present in the Type-C connector.
Independent retimer with the physical demultiplexer multiplexer for separating between different PHY, which can be, possible solution,
But it is expensive and can occupy valuable circuit board space and have increased power.
Third challenge be must be supported in certain platforms different retimers quantity and it is relevant verifying simultaneously
Apply interoperability challenge.
Detailed description of the invention
Attached drawing according to detailed description given below and according to various embodiments of the present invention, the present invention will be by more complete
Understand to face, however, specific embodiment should not be limited the invention to, is only used for explanation and understanding.
Figure 1A shows the link of not retimer.
Figure 1B shows the link with one or more retimers.
Fig. 1 C shows another element of the link with multiple retimers.
Fig. 2 is the block diagram of one embodiment of retimer.
Fig. 3 is another block diagram depicted for trained data path of one embodiment of retimer.
Fig. 4 be for use at least one retimer transmit between both devices data process one embodiment
Flow chart.
Fig. 5 shows one embodiment of system-level figure.
Specific embodiment
In the following description, many details are elaborated to provide to more thorough explanation of the invention.However, for ability
For field technique personnel it is evident that, the present invention can be practiced without these specific details.At other
In example, well-known structure and equipment in form of a block diagram rather than be illustrated in detail, to avoid the fuzzy present invention.
Disclose a kind of retimer for supporting multi-protocols and the method for using it.In one embodiment, all
The retimer as the link of PCIe compatible link etc may include one or more or other expansion equipments.When resetting
Device includes the active electron component for receiving and retransmitting (when resetting) digital signal.
In one embodiment, multi-protocols retimer includes two data paths for each sublink.First number
According to the low delay bypass path that path is for normal discharge.In one embodiment, when being operated under common clock mode,
First data path is used.Second data path has the delay longer than the first data path.In one embodiment, when
Under not common clock module or while training (for example, link training and/or initialization), which is used.
This is usually when being delayed inessential.
In one embodiment, multi-protocols perception retimer is using common data path and fusion link training and shape
State state machine (LTSSM), LTSSM are for the initialization that can be directed to its multiple agreement for configuring retimer and link training
It is essential.In one embodiment, LTSSM is initially identified under data rate and bit mode runs on the link
Agreement.In one embodiment, which can be presented by sideband mechanism, and the mechanism such as band (strap) or joint are surveyed
Tentative dynamic group (JTAG) or System Management Bus (SMBUS).In one embodiment, training includes link equalization program, such as
The link equalization program of PCIe.In one embodiment, retimer includes for executing any required link training
Carrying out low delay after (for example, balancing procedure for generating transmitter and/or receiver balance parameter (for example, coefficient)) makes
Bypass path.
In one embodiment, retimer can switch between two paths.In one embodiment, during training
Protocol enhancement ensure that retimer can toggle between the two data paths.These associations are described more particularly below
View enhancing.
In one embodiment, multi-protocols perception retimer determined using circuit be used for data transmit PHY or
Agreement.In one embodiment, circuit is coupled to receive with option or indicates some other sideband mechanism of PHY.Another
In embodiment, the determination to PHY is completed by detecting the training set modification to the training set for link training.
Retimer described herein has low delay and can use across multiple interconnection.This is to high delay
The independent retimer individually interconnected significantly improves.
Figure 1A shows the link of not retimer.With reference to Figure 1A, equipment 1 and equipment 2 are via link A and link B coupling
It is combined.On the contrary, Figure 1B shows the link with one or more retimers.With reference to Figure 1B, 12 coupling of equipment 1 and equipment
Close one or more retimers 101.Retimer 101 can be a component in all channels for link, or
It can be multiple retimers, the different channel groups in each retimer processing link.In one embodiment, in chain
There are multiple retimers in road, such as shown in Fig. 1 C.In the case where single retimer, retimer 101 passes through subchain
Road A1 and sublink B2 is coupled to equipment 1, and is coupled to equipment 2 by sublink A2 and sublink B1.These sublinks follow
Agreement, and retimer 101 can be configured to the agreement (that is, one of multiple agreements) followed with sublink operation and be set with realizing
Communication between standby 1 and equipment 2.
Fig. 2 is the block diagram of one embodiment of retimer.In one embodiment, retimer is between both devices
When execution is reset, and it can be configured (one at a time) for any agreement in multiple agreements.
With reference to Fig. 2, receiver 201 receives data from the first equipment to be transferred to the second equipment via transmitter 202.It receives
Device 201 and transmitter 202 are coupled in via the first data path 203, the second data path 204 and multiplexer (mux) 206
Together.In one embodiment, be used for will be from reception during the specific training of agreement (for example, link training) for data path 204
The received data of device 201 are transferred to transmitter 202.The specific training of agreement enables transmitter 202 and receiver 201 according to them
Between the agreement of link transmit data between both devices.Data path 203 in the specific training of agreement for having occurred and that
Data are transmitted between receiver 201 and transmitter 202 later.In one embodiment, data path 203 has than data road
The low delay of diameter 204.In one embodiment, data path 203 is used during common clock mode, and data path
204 for during not common clock module and during training.
In one embodiment, data path 204 is coupled to controller 205 (for example, control circuit).Controller 205 is held
The specific training of agreement of one or two of row transmitter 202 and receiver 201.In one embodiment, the specific instruction of agreement
Practice includes link training and initialization.In one embodiment, such link training includes executing balancing procedure.In a reality
It applies in example, balancing procedure generates the transmitter equalizing coefficient for controlling the equilibrium executed by transmitter 202, such as determining
The horizontal cursor coefficient to postemphasis with preshoot (preshoot).In one embodiment, balancing procedure is linear with continuous time
The form of balanced (CTLE) and decision feedback equalization (DFE) generates the receiver balance coefficient for being used for receiving side equilibrium.Note that
In one embodiment, when training receiver 201, data path 204 is also used.
In one embodiment, data path 204 includes one or more Link Training State Machines for multiple agreements,
Wherein, one or more Link Training State Machines are executed by controller 205 according to by a specified agreement of agreement instruction 210
To execute link training.In one embodiment, a state machine can execute training (for example, link is instructed for multiple agreements
Practice).In another embodiment, for each different agreement, there are individual state machines.In one embodiment, link is instructed
Practicing state machine includes link training and status state machine (LTSSM).State machine is stored in memory and is visited by controller 205
It asks.In one embodiment, when executing LTSSM, controller 205 is directed to link associated with each of multiple agreements
Training generates ordered set (OS).
In one embodiment, controller 205 is in response to specifying (multiple associations for transmitting data between both devices
In view) the agreement instruction 210 (for example, one or more signals) of agreement.Agreement instruction 210 is by agreement/PHY determiner
207 (for example, determine circuits) provide, and the agreement/PHY determiner 207 is in response to it from the received band option of data path 204
Or sideband signals 212 or agreement instruction 210 is provided to one or more of instruction 213 of training set modification.Usually by every
A agreement specifies training set modification, and the agreement has the training set modification specification defined for retimer.
In one embodiment, in response to receiving predefined training set, from use data path 203 to data path
204 switching occurs.In this case, training set modification instruction 213 can come from data path 204 and go to agreement/PHY
Determiner 207, the agreement/PHY determiner 207 provide agreement instruction 210 to controller 205, needs to be implemented so as to specified
New link training (for example, balanced) process.Note that using such switching part of data path 203 or data path 204
It is realized by multiplexer 206.Data path selection signal 211 from controller 205 makes from data path 203 or 204
Data be output to transmitter 202 to be transmitted.
Fig. 3 is another block diagram depicted for trained data path of one embodiment of retimer.Note that control
Device processed and its function are not yet shown in FIG. 3, this is because being shown in FIG. 2；Nonetheless, those skilled in the art will manage
Solution controller operates to realize retimer operation described herein.
With reference to Fig. 3, retimer includes receiver 301 (for example, receiving circuit) and transmitter 302 (for example, sending electricity
Road).In one embodiment, receiver 301 executes continuous time linear equalization (CTLE) in a manner known in the art or determines
Plan feedback equalization (DFE).Clock and data recovery (CDR) circuit 340 is coupled to receiver 301 and in a manner known in the art
Operation.
Retimer includes two data paths between receiver 301 and transmitter 302.The two is all coupled to receiver
Two inputs of 301 output and multiplexer (mux) 326, the output coupling of the multiplexer 326 to transmitter
302 input.During the data path 351 of one of data path is used for training, and at another data path (bypass path 350)
It is used after training.
Data path 351 includes multiple components.Serial-to-parallel (S2P) converter 320 is by data from serial conversion for simultaneously
Row.When receiver 301 operates in analog domain, S2P converter 320 by received data conversion at parallel form so that
Data can be processed in a digital format.
Based on agreement associated with data, then parallel data passes through the alignment of the experience of data processor 301, decoding and descrambling
(if necessary).More specifically, it may be necessary to which data are descrambled.This may be since data are just being received
Speed.It may must decode these bits.For example, data may be subjected to 8b/10b decoding or another type of decoding.Number
It it may also be necessary to experience alignment according to bit to determine when the symbol in bit stream starts.These options are with side well known in the art
Formula executes, for understanding the various agreements supported.Note that if agreement do not need alignment, decoding and descrambling in it is any
One or all, then such function is not performed.Result data is stored in elastic buffer 322.
In one embodiment, elastic buffer 322 is public elastic buffer, be can function as needing its
The wander buffer of agreement (for example, UPI, USB, Thunderbolt etc.).Elastic buffer 322 is also compensated for according to a clock
The bit stream that the clock in domain is just being sent, the clock with just by the clock domain of transmission data clock mismatch.
Data from elastic buffer 322 are sent to segmentation buffer and multiplexer (mux) 324 and more associations
Discuss Training Control block 323.
In one embodiment, multi-protocols Training Control block 323 includes link training and state shape needed for each agreement
Associated bit stream detection/modification needed for the public collection of state machine (LTSSM) subset and each agreement.For example, if association
View first is that PCIe, then PCIe LTSSM is included as the subset of public concentration, and multi-protocols Training Control block 323 can
Execute bit stream well known in the art detection, ordered set generate it is (it is used during link training) and related to PCIe standard
The bit stream of connection is modified.In one embodiment, multi-protocols Training Control block 323 includes being used for USB, display port, Lei Li
(Thunderbolt) or the link training and status state machine of one or more of consistency protocol (for example, UPI)
(LTSSM) the public collection of subset.
It is exported for any data that transmitter 302 is sent from multi-protocols Training Control block 323 and from elastic buffer 322
Data by segmentation buffer mux and mux 324 input receive, depend on by the received control selections of mux (for example,
Signal) output.
Finally, any scrambling of data experience exported from segmentation buffer and mux 324 and coding are (such as by being used for transmitting
The agreement instruction of data) and using converter 325 be converted to serial form.Serial data is output to the one of mux 326
Serial data or the data from bypass path 350 are supplied to transmitter 325 by a input.
Note that in one embodiment, various analog control circuits are (for example, the simulation of receiver 301 and transmitter 302
Control circuit) it can be operated under all data rates for the agreement supported.
Phaselocked loop (PLL) or other clock generators 311 provide clock signal to the component of retimer.
Therefore, data path 351 has the public collection of process block, and above omnibus circuit has public collection and correlation
The control circuit of connection can make the relevant control operation of required agreement and data rate to transmit according to more than one agreement
Data.In one embodiment, data path determines the PHY/ agreement in use using band or sideband signals.Alternatively, it patrols
Initial training collection can be searched and determine which PHY agreement is being used by collecting layer.In one embodiment, which resides in
In multi-protocols Training Control block 323.
Bypass path 350 be for link training after the second data path.In one embodiment, bypass path
350 be used for low delay bit transfer, and can be carried out under common clock mode normal bits spread it is defeated.
In one embodiment, even if in bypass mode, the logical layer monitoring flow in conventional path 351 is with determination
It is no to need to modify bit stream.In one embodiment, following mechanism between path 351 and bypass path 350 for converting.
In one embodiment, during link training, path 351 participates in the Tx equilibrating mechanism on two sides, such as by corresponding to
PHY protocol specification instruction.Tx equalization setting suitably keeps the speed, until there is balancing procedure again.Note that one
In a embodiment, when component detection had previously executed balanced not when working normally as determined by error rate, rebalancing method to it
Process can occur.In another embodiment, when software is higher than the similar measurement of thresholding etc based on such as error rate come by chain
When road direction reforms equilibrium, rebalancing method process can occur.
In one embodiment, PHY Normalization rule one or more special training collection (TS), resets via described herein
When device (or other expansion equipments) (for example, equipment 1 or equipment 2 of Figure 1B) equipment that is coupled complete Tx it is balanced after
The special training collection is sent to allow retimer to be switched to the wherein bypass mode using bypass path 350.Upon handover,
Retimer is lost in bit being processed in conventional path 351.Therefore, receiving device (for example, equipment 2 of Figure 1B) will be wrong
Cross a part of bit stream.In one embodiment, which is handled as follows.
First different ordered sets (OS) (referred to herein as " conventional to bypass mark ordered set ") mention to retimer
For instructing to be switched in path from conventional path 351 after it will also send equipment for the different ordered sets for serving as indicator
Bypass path 350, to re-establish block/character boundary.In one embodiment, switching occurs to follow in all components predetermined
After time.Retimer, which ensures to be delayed, is no more than this predetermined time, completely logical with permission " conventional to arrive bypass mark ordered set "
It crosses without being truncated or abandoning.
Some time after marking ordered set sends subsequent ordered set.In one embodiment, elapsed time
Bypass path 350 is switched to multiplied by retimer greater than the maximum retimer number (usually 2) on the path allowed by specification
Predetermined time later.This will be used by receiver apparatus (for example, equipment 2 of Figure 1B) to be lost some ratios due to switching
Its symbol/block boundary is re-established after special.
For the agreement of such as PCI-Express etc, due to execute it is balanced after 1 ordered set of TS and EIEOS after
It is continuous, therefore such ordered set is unnecessary.Equipment (for example, equipment 2) can simply re -training and obtain with need equipment
The block alignment of the specification modification done so.
The case where wherein retimer needs are moved to normal route 351 from bypass path 350 will be present (for example, again
It is balanced).When that happens, a part of bit stream will repeat.This can be by making identical label ordered set in training
Collection comes to complete, and is similar to content described above.
In one embodiment, when link needs to enter electrical idle, before link actually enters electrical idle
Some time sends indicator ordered set (for example, electrical idle ordered set in PCIe).Note that EIOS is enough in PCIe
It is long, and can be identified after preceding several symbols, it means that there is any position from 20UI to 96UI, this depends on link
Coding/speed before into electrical idle.It is some the significant bit stream that can be dropped after the indicator ordered set.This
Retimer is allowed to react (this occurs in conventional path 351) to ordered set and bring its channel Tx into electrical idle.
In alternative embodiments, any change is not carried out, and when exiting from electrical idle, it is contemplated that equipment side (for example, Figure 1B
Equipment 2) re -training (it is all exiting when progress from LI anyway).
Fig. 4 be for use at least one retimer transmit between both devices data process one embodiment
Flow chart.In one embodiment, process is executed by processing logic, and the processing logic may include that hardware is (circuit, dedicated
Logic etc.), the combination of software (for example, the software run in general-purpose computing system or special purpose machinery), firmware or three.
Process start from handle logic determine physical layer (PHY) type (for example, PCIe, USB, display port etc.), with
In data are transferred to transmitter (processing block 401) from receiver.In one embodiment, determine that PHY type is based on band choosing
?.In another embodiment, determine that PHY type is based on sideband signals.In another embodiment, determining PHY type is
Based on monitoring training set to match PHY type.
Then, processing logic, which provides, indicates the agreement of agreement, and according to the agreement, data are in response to determining for that will count
(process block 402) is transmitted according to physical layer (PHY) type for being transferred to transmitter from receiver.
It is indicated in response to agreement, processing logic optionally configures transceiver and/or receiver (processing block 403).Configuration can
To include training (for example, link training).In one embodiment, the specific training of agreement includes executing balancing procedure.At one
In embodiment, executing balancing procedure includes generating for controlling the balanced transmitter equalizing coefficient executed by transmitter.
Then, the receiver for handling logic multi-protocols retimer receives data, wherein data are according to multiple agreements
One of transmission (processing block 404) and send data between the receiver and transmitter of retimer, if transmission is by receiver
Received data in response to the instruction to an agreement in multiple agreements via control circuit in transmitters and receivers
Occur during or before the specific training of the agreement of one or two, then receiver and transmitter are coupled in the transmission data use
The first data path, or if transmission is occurred after training by the received data of receiver agreement is specific, the hair
Send data using the second data path for being coupled to receiver and transmitter, the second data path has lower than the first data path
Delay (processing block 405).
It in one embodiment, the use of the first data path include operation Link Training State Machine according to specified by indicating
Agreement execute link training.In one embodiment, running Link Training State Machine to execute link training includes
Ordered set is executed for link training associated with an agreement to generate.
In one embodiment, the second data path is used during common clock mode, and the first data path
For during not common clock module and during the specific training of agreement.In one embodiment, using first or second data road
Diameter includes sending control signals to multiplexer, and the multiplexer is defeated be coupled to the first data path first
Enter and be coupled to the second input of the second data path, to generate the output for being coupled to transmitter.
At some time in future, processing logic be optionally in response to receive predefined training set and from using second
Data path is switched to the first data path (processing block 406).
Fig. 5 be may include technology described above system-level figure 500 one embodiment.For example, described above
Technology can be incorporated in the interconnection in system 500 or interface.
With reference to Fig. 5, system 500 includes but is not limited to: desktop PC, laptop computer, net book, plate electricity
Brain, notebook computer, personal digital assistant (PDA), server, work station, cellular phone, mobile computing device, intelligence electricity
The calculating equipment of words, internet equipment or any other type.In another embodiment, system 500 realizes side disclosed herein
Method, and can be system on chip (SOC) system.
In one embodiment, processor 510 has the one or more processors core heart 512 to 512N, wherein 512N table
Show the N processor core inside processor 510, wherein N is positive integer.In one embodiment, system 500 includes multiple
Processor, the multiple processor include processor 510 and 505, wherein processor 505 has the logic class with processor 510
Like or identical logic.In one embodiment, system 500 includes multiple processors, and the multiple processor includes processor
510 and 505, so that processor 505 has the logic for the logic for being totally independent of processor 510.In such embodiments,
More packet systems 500 are the more packet systems of isomery, this is because processor 505 and 510 has different logic units.Implement at one
Example in, processing core 512 include but is not limited to for extracts instruct preextraction logic, the decode logic for solving code instruction,
Execution logic for executing instruction etc..In one embodiment, processor 510 have for system 500 instruction and/or
The cache memory 516 that data are cached.In another embodiment of the invention, cache memory 516
Any other configuration including the cache memory in grade one, grade two and three cache memory of grade or processor 510.
In one embodiment, processor 510 includes memory controlling hub (MCH) 514, can be operated to execute and make
The function that processor 510 is able to access that memory 530 and communicates with memory 530, the memory 530 include volatile storage
Device 532 and/or nonvolatile memory 534.In one embodiment, memory controlling hub (MCH) 514 is as independent
Integrated circuit is located at the outside of processor 510.
In one embodiment, processor 510 can be operated to communicate with memory 530 and chipset 520.In such reality
It applies in example, when SSD 580 is powered, SSD 580 executes computer executable instructions.
In one embodiment, processor 510 be additionally coupled to wireless antenna 578 with be configured to send and/or receive nothing
Any equipment of line signal communicates.In one embodiment, radio antenna interface 578 according to but be not limited to IEEE 802.11 mark
Quasi- and its related series, HomePlug AV (HPAV), ultra wide band (UWB), bluetooth, WiMAX or any type of wireless communication association
View is operated.
In one embodiment, volatile memory 532 includes but is not limited to Synchronous Dynamic Random Access Memory
(SDRAM), dynamic random access memory (DRAM), RAMBUS dynamic random access memory (RDRAM) and/or any other
The random access memory device of type.The including but not limited to flash memory of nonvolatile memory 534 (for example, NAND,
NOR), phase transition storage (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM) or it is any its
The non-volatile memory devices of his type.
Memory 530 stores the information and instruction to be executed by processor 510.In one embodiment, chipset 520 passes through
It is connect by point-to-point (PtP or P-P) interface 517 and 522 with processor 510.In one embodiment, chipset 520 makes to handle
Device is connectable to other modules in system 500.In one embodiment, interface 517 and 522 is according to such as Intel
The PtP communication protocol of QuickPath interconnection (QPI) etc. is operated.
In one embodiment, chipset 520 can operate with processor 510,505, display equipment 540 and other equipment
572, it 576,574,560,562,564,566,577 etc. is communicated.In one embodiment, chipset 520 is additionally coupled to nothing
Wire antenna 578 with any equipment for being configured as sending and/or receiving wireless signal to be communicated.
In one embodiment, chipset 520 is connected to display equipment 540 via interface 526.In one embodiment,
Show equipment 540 include but is not limited to liquid crystal display (LCD), plasma, cathode-ray tube (CRT) display or it is any its
The visual display device of his form.In addition, chipset 520 is connected to the interconnection of various modules 574,560,562,564 and 566
One or more buses 550 and 555.In one embodiment, it is mismatched if existed in bus speed or communication protocol, always
Line 550 and 555 can be interconnected via bus bridge 572.In one embodiment, chipset 520 is via interface 524, intelligence
Energy TV 576, consumer electronics 577 etc. and nonvolatile memory 560, mass-memory unit 562, keyboard/mouse
564 and network interface 566 (but being not limited to these) coupling.
In one embodiment, mass-memory unit 562 includes but is not limited to solid state drive, hard disk drive, leads to
With the computer data storage medium of universal serial bus flash memory drives or any other form.In one embodiment,
Network interface 566 is realized that the standard includes but is not limited to Ethernet interface, leads to by any kind of well-known network interface standard
With universal serial bus (USB) interface, peripheral component interconnection (PCI) fast interface, wireless interface and/or any other suitable type
Interface.
Although module shown in fig. 5 is depicted as the independent block in system 500, by some pieces of execution in these blocks
Function can integrate in single semiconductor circuit, or can be used two or more individual integrated circuits come it is real
It is existing.
In the first exemplary embodiment, one kind according to multiple agreements between the first equipment and the second equipment for executing
Device when resetting includes: that can operate to receive the receiver of data；For sending the transmitter of data；First data path,
It is coupled to receiver and transmitter, and can operate will transmit from the received data of receiver during the specific training of agreement
To transmitter, the first data path includes control circuit, be used in response to the instruction to an agreement in multiple agreements and
Control the specific training of agreement of one or two of transmitters and receivers；And second data path, it is coupled to reception
Device and transmitter, wherein the second data path have the delay lower than the first data path and for agreement it is specific it is trained it
After will be transferred to transmitter from the received data of receiver.
In a further exemplary embodiment, the theme of the first exemplary embodiment can optionally include: the specific instruction of agreement
Practice includes executing balancing procedure.In a further exemplary embodiment, the theme of the exemplary embodiment can optionally include:
Weighing apparatus process is generated for controlling the balanced transmitter equalizing coefficient executed by transmitter.
In a further exemplary embodiment, the theme of the first exemplary embodiment can optionally include: the second data road
Diameter is used during common clock mode, and the first data path is for during not common clock module and during training.
In a further exemplary embodiment, the theme of the first exemplary embodiment can optionally include: in response to receiving
Predefined training set, occur from use the second data path to the switching of the first data path.
In a further exemplary embodiment, the theme of the first exemplary embodiment can optionally include circuit, response
Instruction is provided for the data from receiver to be transferred to the physical layer (PHY) of transmitter in determining.In another exemplary
In embodiment, the theme of the exemplary embodiment can be optionally included: circuit can be operated to determine PHY based on band option,
Circuit can be operated to determine that PHY or circuit can be operated based on sideband signals and determine PHY to modify based on training set.
In a further exemplary embodiment, the theme of the first exemplary embodiment can optionally include multiplexer,
It has the first input for being coupled to the first data path and the second input for being coupled to the second data path and is coupled to hair
Send the output of device.
In a further exemplary embodiment, the theme of the first exemplary embodiment can optionally include: the first data road
Diameter further includes one or more Link Training State Machines for multiple agreements, and one or more Link Training State Machines are by controlling
Circuit is used according to by indicating that a specified agreement executes link training.In a further exemplary embodiment, this is exemplary
The theme of embodiment can optionally include: control circuit can be operated for associated with each agreement in multiple agreements
Link training executes ordered set and generates.
In a further exemplary embodiment, the theme of the first exemplary embodiment can optionally include: the first data road
Diameter further include: serial-to-parallel (S2P) converter is coupled to that will be converted to by received first serial data of receiver
One parallel data；First logic is coupled to S2P converter to execute alignment, decoding and descrambling if necessary；Elastic buffer
Device is coupled to the first logic with the storing data after any alignment, decoding and descrambling；It is segmented buffer circuit, is coupled to
Elastic buffer and control circuit, segmentation buffer circuit include own elasticity in future buffering in response to one or more control signal
The data or training data of device are supplied to the multiplexer of transmitter；And parallel-to-serial (P2S) converter, it is coupled
And it can operate to receive the second parallel data from segmentation buffer circuit and the second parallel data is converted to the second serial data.
In the second exemplary embodiment, method includes: to receive data with the receiver of multi-protocols retimer, wherein
Data are transmitted according to one of multiple agreements；And data are sent between the receiver and transmitter of retimer, if
Transmission is being sent via control circuit in response to the instruction to an agreement in multiple agreements by the received data of receiver
Occur during or before the specific training of agreement of one or two of device and receiver, then the transmission data use is coupled to
First data path of receiver and transmitter, or if transmission is specific after training in agreement by the received data of receiver
Occur, then the data that send are using being coupled to the second data path of receiver and transmitter, the second data path have than
The low delay of first data path.
In a further exemplary embodiment, the theme of the second exemplary embodiment can optionally include: the specific instruction of agreement
Practice includes executing balancing procedure.In a further exemplary embodiment, the theme of the exemplary embodiment can optionally include: hold
Row balancing procedure includes generating for controlling the balanced transmitter equalizing coefficient executed by transmitter.
In a further exemplary embodiment, the theme of the second exemplary embodiment can optionally include: the second data road
Diameter is used during common clock mode, and the first data path is for during not common clock module and the specific instruction of agreement
During white silk.
In a further exemplary embodiment, the theme of the second exemplary embodiment can optionally include: in response to receiving
Predefined training set and from using the second data path to be switched to the first data path.
In a further exemplary embodiment, the theme of the second exemplary embodiment can optionally include: in response to determination
Instruction is provided for data to be transferred to physical layer (PHY) type of transmitter from receiver.In another exemplary embodiment
In, the theme of the exemplary embodiment can optionally include: determine PHY type be based on band option, based on sideband signals or
Person is modified based on training set.
In a further exemplary embodiment, the theme of the second exemplary embodiment can optionally include: selection multichannel is multiple
With the control signal of device, the multiplexer has the first input for being coupled to the first data path and is coupled to the second data
Second input in path, to generate the output for being coupled to transmitter.
In a further exemplary embodiment, the theme of the second exemplary embodiment can optionally include: operation link instruction
Practice state machine to execute link training according to by indicating a specified agreement.In a further exemplary embodiment, the example
Property embodiment theme can optionally include for link training associated with an agreement execute ordered set generate.
In a further exemplary embodiment, the theme of the second exemplary embodiment can optionally include: during the training period
It stores data in elastic buffer；And the output of the multiplexer of elastic buffer is coupled in control, will be come from
The training data that the data of elastic buffer are output to transmitter or output is generated when executing link training；It is parallel-to-serial
(P2S) converter is coupled and can be operated to receive the second parallel data from segmentation buffer circuit and by second and line number
According to being converted to the second serial data.
In third exemplary embodiment, a kind of system includes: a pair of of equipment；Retimer is coupled in a pair of of equipment
Between between a pair of of equipment provide both direction on data flow, wherein data flow in each direction is by the following terms
It executes: can operate to receive the receiver of data；For sending the transmitter of data；First data path is coupled to reception
Device and transmitter, and can operate so that during the specific training of agreement transmitter will be transferred to from the received data of receiver,
In, the first data path includes control circuit, controls transmitter in response to the instruction to an agreement in multiple agreements
With the specific training of agreement of one or two of receiver；And second data path, it is coupled to receiver and transmitter,
Wherein, the second data path has a delay lower than the first data path, and for agreement is specific after training will be from connecing
It receives the received data of device and is transferred to transmitter.In a further exemplary embodiment, the theme of the exemplary embodiment can be optional
Ground includes: that the specific training of agreement includes executing balancing procedure.In a further exemplary embodiment, the theme of the exemplary embodiment
Balancing procedure can be optionally included to generate for controlling the balanced transmitter equalizing coefficient executed by transmitter.
In a further exemplary embodiment, the theme of the second exemplary embodiment can optionally include: the second data road
Diameter uses during common clock mode, and the first data path is for during not common clock module and during training.
The some parts of above detailed description be the operation to the data bit in computer storage algorithm and
What the aspect that symbol indicates was presented.These algorithm descriptions and expression are to be used to most have by the technical staff of data processing field
The essence that they work is communicated to the means of others skilled in the art by effect ground.Herein and typically, algorithm quilt
It is considered the self-congruent sequence of steps caused expected result.Step is the step of needing the physical manipulation to physical quantity.It is logical
Often (but not necessarily), this tittle use can be by storage, the electric signal or magnetic that transmission, combine, compare and otherwise manipulate
The form of signal.Sometimes, primarily for general reason, it has proved that these signals are known as bit, value, element, symbol, words
Symbol, term, number etc. are convenient.
However, it should be remembered that all these and similar terms are all associated with appropriate physical quantity, and are only to apply
In the facilitate label of this tittle.It explains separately except non-expert (just as obvious according to following discussion), otherwise should
Understand, throughout the specification, utilizes the term of " processing " or " operation " or " calculating " or " determination " or " display " etc.
The movement and process for referring to computer system or similar electronic computing device are discussed, the computer system or similar electronics calculate
The data for physics (electronics) amount that device manipulation is represented as in the register and memory of computer system are simultaneously converted into
It is similarly represented as in computer system memory or register or other such information storage, transmission or display equipment
Other data of physical quantity.
The invention further relates to apparatus for performing the operations herein.The device can for required purpose special configuration,
Or it may include the general purpose computer being selectively activated or reconfigured by by the computer program stored in a computer.
Such computer program may be stored in a computer readable storage medium, such as, but not limited to: any kind of disk
(disk), including floppy disk, CD, CD-ROM and magneto-optic disk, read-only memory (ROM), random access memory (RAM),
EPROM, EEPROM, magnetic or optical card or any kind of medium suitable for storing e-command, and each medium coupling
Close computer system bus.
Algorithm and display presented herein is not inherently related to any certain computer or other devices.According to herein
Introduction, various general-purpose systems can be used together with program, or the more special device of construction can be proved come needed for executing
Method and step be convenient.Structure needed for these various systems will occur from being described below.In addition, without reference to any spy
Fixed programming language describes the present invention.It will be appreciated that various programming languages can be used to realize the present invention as described herein
Introduction.
Machine readable media includes for storing or sending any of information in the readable form of machine (for example, computer)
Mechanism.For example, machine readable media includes read-only memory (" ROM ")；Random access memory (" RAM ")；Disk storage is situated between
Matter；Optical storage media；Flash memory device；Etc..
Although, undoubtedly will be for ability to many changes and modifications of the invention after the description for having read front
It is become apparent for the those of ordinary skill of domain, but it is to be understood that any spy for being shown and being described by way of explanation
Determine embodiment and be not intended to be considered being limited.Therefore, right is not intended to limit to the reference of the details of various embodiments
It is required that range, it is considered as to those of essential feature of the present invention that described claim itself, which is only recorded,.
Claims (20)
1. a kind of device for being executed when resetting between the first device and the second device according to multiple agreements, described device packet
It includes:
It can operate to receive the receiver of data；
For sending the transmitter of data；
First data path is coupled to the receiver and the transmitter, and can operate in agreement specific training period
Between the transmitter will be transferred to from the received data of the receiver, first data path includes control circuit, use
In controlling one in the transmitter and the receiver in response to the instruction to an agreement in the multiple agreement
Or two specific training of agreement；And
Second data path, is coupled to the receiver and the transmitter, and second data path has than described the
The low delay of one data path, and for institute will to be transferred to from the received data of the receiver after training agreement is specific
State transmitter.
2. device as described in claim 1, wherein the specific training of agreement includes executing balancing procedure.
3. device as claimed in claim 2, wherein the balancing procedure generate for control executed by the transmitter it is equal
The transmitter equalizing coefficient of weighing apparatus.
4. device as described in claim 1, wherein second data path is used during common clock mode, and
And first data path is for during not common clock module and during training.
5. device as described in claim 1, wherein in response to receiving predefined training set, from use it is described second number
Occur according to the switching in path to first data path.
6. device as described in claim 1, further includes: circuit, be used in response to determine for by data from the reception
Device is transferred to the physical layer (PHY) of the transmitter and provides the instruction.
7. device as claimed in claim 6, wherein the circuit can be operated based on band option, sideband signals or training set
Modification is to determine the PHY.
8. device as described in claim 1 further includes multiplexer, defeated be coupled to first data path first
Enter end and is coupled to the second input terminal of second data path and is coupled to the output end of the transmitter.
9. device as described in claim 1, wherein first data path further includes one for the multiple agreement
Or multiple Link Training State Machines, one or more of Link Training State Machines are used for by the control circuit according to by described
Specified one agreement is indicated to execute link training.
10. device as described in claim 1, wherein first data path further include:
Serial-to-parallel (S2P) converter is coupled to that will be converted to by received first serial data of the receiver
One parallel data；
First logic is coupled to the S2P converter to execute alignment, decoding and descrambling if necessary；
Elastic buffer is coupled to first logic with the storing data after any alignment, decoding and descrambling；
Stage buffer circuit is coupled to the elastic buffer and the control circuit, the stage buffer circuit packet
Include multiplexer, in response to one or more control signals by from the elastic buffer data or training data provide
To the transmitter；And
Parallel-to-serial (P2S) converter is coupled and can be operated to receive second simultaneously from the stage buffer circuit
Row data and second parallel data is converted into the second serial data.
11. a kind of method, comprising:
Data are received with the receiver of multi-protocols retimer, wherein the data are according to an agreement in multiple agreements
It is transmitted；And
If transmission by the received data of the receiver via control circuit in response to in the multiple agreement
The instruction of one agreement and agreement that one or two of transmitter and the receiver to the retimer carries out is special
Occur during or before fixed training, then using being coupled to the first data path of the receiver and the transmitter come described
Data are sent between receiver and the transmitter, or
If transmission is occurred after training by the received data of the receiver the agreement is specific, using being coupled to
Second data path of the receiver and the transmitter sends data, institute between the receiver and the transmitter
The second data path is stated with the delay lower than first data path.
12. method as claimed in claim 11, wherein the specific training of agreement includes: including executing balancing procedure with life
At for controlling the balanced transmitter equalizing coefficient executed by the transmitter.
13. method as claimed in claim 11, wherein second data path is used during common clock mode,
And during first data path is used for not common clock module and during the specific training of agreement.
14. method as claimed in claim 11, further includes: in response to receiving predefined training set and from using described
Two data paths are switched to first data path.
15. method as claimed in claim 11, further includes: in response to determining for data to be transferred to institute from the receiver
It states physical layer (PHY) type of transmitter and the instruction is provided.
16. method as claimed in claim 15, wherein determine that the PHY type is based on band option, sideband signals or training
Collection modification.
17. method as claimed in claim 11, further includes:
It stores data in elastic buffer during the training period；And
The output end of the multiplexer of the elastic buffer is coupled in control, by data from the elastic buffer or will be
The training data generated when executing link training is output to the transmitter,
Parallel-to-serial (P2S) converter is coupled and can be operated to receive second simultaneously from the stage buffer circuit
Row data and second parallel data is converted into the second serial data.
18. a kind of system, comprising:
A pair of of equipment；
Retimer is coupled between the pair of equipment to provide the data in both direction between the pair of equipment
Stream, wherein the data flow in each direction is executed by the following terms:
It can operate to receive the receiver of data,
For sending the transmitter of data,
First data path is coupled to the receiver and the transmitter, and can operate in agreement specific training period
Between the transmitter will be transferred to from the received data of the receiver, first data path includes control circuit, use
In controlling one in the transmitter and the receiver in response to the instruction to an agreement in the multiple agreement
Or two specific training of agreement, and
Second data path, is coupled to the receiver and the transmitter, and second data path has than described the
The low delay of one data path, and for institute will to be transferred to from the received data of the receiver after training agreement is specific
State transmitter.
19. system as claimed in claim 18, wherein the specific training of agreement includes: including executing balancing procedure with life
At for controlling the balanced transmitter equalizing coefficient executed by the transmitter.
20. system as claimed in claim 18, wherein second data path is used during common clock mode,
And during first data path is used for not common clock module and during training.
Applications Claiming Priority (3)
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| US15/193,941 US9965439B2 (en) | 2016-06-27 | 2016-06-27 | Low latency multi-protocol retimers |
| PCT/US2017/029704 WO2018004811A1 (en) | 2016-06-27 | 2017-04-26 | Low latency multi-protocol retimers |
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| CN109154927A true CN109154927A (en) | 2019-01-04 |
| CN109154927B CN109154927B (en) | 2023-07-28 |
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| CN201780030035.1A Active CN109154927B (en) | 2016-06-27 | 2017-04-26 | Low-delay multi-protocol re-timer |
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| US (2) | US9965439B2 (en) |
| CN (1) | CN109154927B (en) |
| DE (1) | DE112017003209T5 (en) |
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Also Published As
| Publication number | Publication date |
|---|---|
| WO2018004811A1 (en) | 2018-01-04 |
| CN109154927B (en) | 2023-07-28 |
| US9965439B2 (en) | 2018-05-08 |
| DE112017003209T5 (en) | 2019-03-28 |
| US20170371831A1 (en) | 2017-12-28 |
| US10606793B2 (en) | 2020-03-31 |
| US20180253397A1 (en) | 2018-09-06 |
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