CN108964697B - Digital channelized repeater system and method based on FPGA - Google Patents

Digital channelized repeater system and method based on FPGA Download PDF

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CN108964697B
CN108964697B CN201810797499.1A CN201810797499A CN108964697B CN 108964697 B CN108964697 B CN 108964697B CN 201810797499 A CN201810797499 A CN 201810797499A CN 108964697 B CN108964697 B CN 108964697B
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module
signals
fpga
paths
band
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CN108964697A (en
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席超
刘江春
谷林海
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Space Star Technology Co Ltd
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Space Star Technology Co Ltd
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40Circuits
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00Programme-control systems
    • G05B19/02Programme-control systems electric
    • G05B19/04Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00Programme-control systems
    • G05B19/02Programme-control systems electric
    • G05B19/04Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0423Input/output
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/005Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B7/00Radio transmission systems, i.e. using radiation field
    • H04B7/14Relay systems
    • H04B7/15Active relay systems
    • H04B7/185Space-based or airborne stations; Stations for satellite systems
    • H04B7/1851Systems using a satellite or space-based relay
    • H04B7/18517Transmission equipment in earth stations
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B7/00Radio transmission systems, i.e. using radiation field
    • H04B7/14Relay systems
    • H04B7/15Active relay systems
    • H04B7/185Space-based or airborne stations; Stations for satellite systems
    • H04B7/1851Systems using a satellite or space-based relay
    • H04B7/18519Operations control, administration or maintenance
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00Program-control systems
    • G05B2219/20Pc systems
    • G05B2219/21Pc I-O input output
    • G05B2219/21137Analog to digital conversion, ADC, DAC

Abstract

The invention relates to a digital channelized transponder realized based on FPGA, which mainly has the functions of changing and amplifying satellite signals and frequency, and a radio receiving and transmitting system is formed by the satellite receiving and transmitting antenna and has the excellent performances of high sensitivity, large dynamic range, high test precision, long-term storage of digitalized data and the like. When the repeater is designed, the processing capacity of the repeater on the broadband signal is considered, the transmission quality of the signal is improved, flexible channel switching and beam switching are realized, and approximate accurate analysis and synthesis of the broadband signal are realized.

Description

Digital channelized repeater system and method based on FPGA
Technical Field
The invention particularly relates to a digital channelized repeater and a forwarding method based on an FPGA (field programmable gate array), belonging to the field of satellite communication.
Background
The satellite communication transponder is a space part of a satellite communication network, is a key load of satellite communication, and the performance of the satellite communication transponder directly influences the performance of the whole satellite communication system. The satellite transponder is a device for converting and amplifying the frequency and signal of the satellite communication system, and together with the satellite transceiving antenna, it forms a radio transceiving system.
The first generation of communication satellites of the international communication satellite organization were put into commercial use in 1965, which marked that communication satellites really entered a new stage of practical use, improvement and development. For many years, satellite communication systems have been developed sufficiently and rapidly in the fields of international communications, domestic communications, national defense communications, mobile communications, broadcast television, and interplanetary communications. With the continuous expansion of the application field of communication satellites, people continuously explore new systems and new technologies of satellite communication and greatly improve and develop the new systems and the new technologies. Meanwhile, the application field of the communication satellite is further expanded due to the development of a new system and a new technology. The development of communication satellite systems has been centered around both increasing the weight of the platform carrying the transponder and the ability to provide electrical power to the transponder, and it can be said that the history of the development of communication satellite systems is actually also that of the transponder. To date, repeaters have accomplished a transition from simple signal amplification and retransmission to on-board signal processing, single function to multi-function, single band to multi-band.
At present, repeaters are classified into two categories, namely 'transparent' and 'processing' according to whether a processing function exists or not, wherein the 'transparent' repeater only performs frequency conversion and amplification forwarding tasks on received signals and is 'transparent' for all signals in a working frequency band; the "processing" transponder has functions such as radio frequency beam switching, modulation and demodulation, baseband switching, and multiple access conversion, in addition to the above functions.
The existing repeater can not forward data of any frequency band to any frequency band, and all signals can not interact among different frequency bands, so that signal forwarding can not be effectively and flexibly realized, and uplink coverage and downlink coverage can not be connected.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: aiming at the defects of the design of the scheme of the existing repeater, the scheme design of the digital channelized repeater realized based on the FPGA is provided. The design of the scheme considers the processing capacity of the transponder to the broadband signal, improves the transmission quality of the signal, realizes flexible channel switching and beam switching, and realizes approximate accurate analysis and synthesis of the broadband signal. The invention takes FPGA as a designed hardware platform to realize a stable, reliable and function completely satisfying satellite-borne broadband digital channelized transponder.
The specific technical scheme of the invention is as follows: a digital channelized transponder system implemented based on an FPGA, comprising: the system comprises a multi-channel receiving unit, a channel forwarding module and a multi-channel transmitting unit;
the multi-path receiving unit receives multi-path satellite uplink signals from an external satellite receiving antenna, selects required signals through gating filtering, and obtains multi-path analog intermediate frequency signals through low-noise amplification and down-conversion; sending the multi-channel analog intermediate frequency signals to a channel demultiplexing module;
the channel forwarding module is used for AD sampling the analog intermediate frequency signals to obtain a plurality of paths of digital intermediate frequency signals, respectively carrying out signal shunting on the plurality of paths of digital intermediate frequency signals, exchanging the shunted signals according to signal time slots, combining the exchanged signals to obtain a combined data signal, carrying out DA conversion on the combined data signal to obtain a plurality of paths of analog intermediate frequency signals, and sending the plurality of paths of analog intermediate frequency signals to the plurality of paths of transmitting units;
and the multi-path transmitting unit is used for carrying out up-conversion, band-pass filtering, power amplification and secondary band-pass filtering on the multi-path analog intermediate-frequency signals and feeding the multi-path analog intermediate-frequency signals into the satellite transmitting antenna through an external antenna tuner.
A channel forwarding module comprising: the device comprises an AD sampling module, a shunt module, an exchange module, a combining module and a DA conversion module;
a switching module comprising: an FPGA module;
the AD sampling module carries out AD sampling on the analog intermediate frequency signals sent by the multipath receiving unit to obtain multipath digital intermediate frequency signals, the multipath module carries out signal shunting on the multipath digital intermediate frequency signals respectively, the FPGA module controls the signals after shunting to be exchanged according to a preset route, the combined module combines the exchanged signals to obtain combined data signals, the DA conversion module carries out DA conversion on the combined data signals to obtain multipath analog intermediate frequency signals, and the multipath analog intermediate frequency signals are sent to the multipath transmitting unit.
The multi-path receiving unit comprises a first band-pass filter BPF0, a low-noise amplifier module L NA, a down-conversion module D/C and a second band-pass filter BPF;
the first band-pass filter BPF0 receives multi-path satellite uplink signals from an external satellite receiving antenna, selects required signals through the gating filtering of the first band-pass filter BPF0, performs low-noise amplification on the signals through the low-noise amplification module L NA, performs down-conversion on the signals through the down-conversion module D/C, performs re-filtering on the signals through the second band-pass filter BPF to obtain multi-path analog intermediate-frequency signals, and sends the multi-path analog intermediate-frequency signals to the channel de-multiplexing module.
And a multipath transmitting unit. The method comprises the following steps: an up-conversion module U/C1, a third band-pass filter BPF2, a driving amplifier, a third band-pass filter BPF3 and a high-power amplifier HPA;
the up-conversion module U/C1 up-converts the multi-channel analog intermediate frequency signals sent by the channel forwarding module, performs band-pass filtering through a third band-pass filter BPF2, performs power amplification through a driving amplifier, performs secondary band-pass filtering through a third band-pass filter BPF3, performs high-power amplification through a high-power amplifier HPA, and feeds the signals to a satellite transmitting antenna through an external antenna tuner.
The shunting module is realized by four FPGAs, the switching module is realized by two FPGAs, and the combining module is realized by four FPGAs;
when the multipath receiving unit receives four paths of satellite uplink signals and generates four paths of analog intermediate frequency signals, after AD conversion is carried out, when a shunting clock arrives, four FPGAs of a shunting module divide each path of digital intermediate frequency signals into forty-eight paths of digital signals, the forty-eight paths of digital signals are respectively sent to one FPGA in an exchange module through the four FPGAs after frame synchronization signals are synchronized, 192 paths of signals are input into one FPGA in the exchange module, the FPGA carries out exchange according to a preset route and then sends the signals to the other FPGA in the exchange module, the FPGA carries out gain modulation on the exchanged multipath digital signals, the four paths of signals are divided into four paths and respectively sent to the four FPGAs of a combining module, and each FPGA of the four FPGAs combines the forty-eight paths into one path to form the four paths of digital intermediate frequency signals.
And the FPGA of the shunt module divides each path of digital intermediate-frequency signal into forty-eight paths of digital signals by adopting an analysis filter bank.
The filter function of the analysis filter bank is as follows:
wherein the content of the first and second substances,and filter order N-M-D, N-mD + k (M-0, 1,2, …, M-1; k-0, 1,2, … D-1); d is the number of subband filters of the analysis filterbank, M is of the analysis filterbankThe subband filter order, h the subband filter coefficients of the analysis filterbank, z in the complex domain.
For a switching matrix in which an FPGA switches according to a predetermined route, for an input of n beams, each beam is divided into n channel input data streams, giving such a mathematical abstraction: the input data stream may be equivalently represented by a mathematical matrix of order n x n as follows:
each beam data in the data stream corresponds to row data of the matrix in _ data, and each subband in each beam corresponds to a position corresponding to a subband serial number in a corresponding row of the matrix in _ data. That is, a in the matrix in _ data11…a1nEquivalent to the first beam, a11Then the first subband in a beam is mapped, and so on.
The FPGA of the combiner module combines forty-eight paths into one path by adopting a synthesis filter bank to form four paths of digital intermediate frequency signals.
The synthesis filter function of the synthesis filter bank is as follows:
wherein the content of the first and second substances,k is 0,1,2, … K-1, K is the number of subband filters of the synthesis filterbank, h is the subband filter coefficients of the synthesis filterbank, j is an imaginary unit, e, pi is a constant, and n is in the real domain.
A digital channelized forwarding method based on FPGA comprises the following steps:
(1) a multi-path receiving unit for receiving multi-path satellite uplink signals from an external satellite receiving antenna,
(2) selecting a required signal from the multi-path satellite uplink signal in the step (1) through gating filtering;
(3) performing low-noise amplification on the signals required in the step (2), and performing down-conversion to obtain multiple paths of analog intermediate frequency signals;
(4) sending the multi-channel analog intermediate frequency signals in the step (3) to a channel demultiplexing module;
(5) the channel forwarding module carries out AD sampling on the analog intermediate frequency signals in the step (4) to obtain a plurality of paths of digital intermediate frequency signals;
(6) respectively carrying out signal shunting on the multi-path digital intermediate frequency signals in the step (5), and exchanging the shunted signals according to signal time slots;
(7) combining the signals after the time slot exchange in the step (6) to obtain combined data signals;
(8) DA conversion is carried out on the combined data signal to obtain a plurality of paths of analog intermediate frequency signals, and the analog intermediate frequency signals are sent to a plurality of paths of transmitting units;
(9) and the multi-path transmitting unit is used for carrying out up-conversion, band-pass filtering, power amplification and secondary band-pass filtering on the multi-path analog intermediate-frequency signals and feeding the multi-path analog intermediate-frequency signals into the satellite transmitting antenna through an external antenna tuner.
Compared with the prior art, the invention has the following advantages:
(1) the invention can realize signal transmission with variable paths in the scheme design, is more flexible in the aspects of broadband signal transmission and wave beam switching of the transponder, and improves the efficiency and effectiveness of the transponder.
(2) The signal multiplexer and demultiplexer are realized by using FPGA, the precise analysis and synthesis of the broadband signal can be realized, and the high-speed switching network based on FPGA can exchange each sub-band in the thinned broadband signal.
(3) The invention aims at providing a scheme design of a digital channelized repeater realized based on an FPGA (field programmable gate array), wherein the digital channelized repeater belongs to the class of processing repeaters, the design of the digital channelized repeater is realized by taking the FPGA as a hardware platform, the transmission quality of signals can be greatly improved, the signals are channelized, the flexible forwarding of multi-beam broadband signals can be realized, and the processing speed of the repeater on the signals is also improved to a certain extent.
(4) The broadband satellite transponder breaks through barriers faced by the development of the traditional satellite communication system, and gives the satellite forwarding system the capability of simultaneously carrying out channel division, multi-terminal, multi-service processing and the like.
(5) The invention adopts the technology of an analysis filter bank and a synthesis filter bank in the scheme design, and can realize the full subband exchange between beams and the subband exchange in the beams.
Drawings
FIG. 1 is a general block diagram of a digital channelized transponder design overall scheme;
FIG. 2 is a schematic diagram of a portion of a transponder exchange;
FIG. 3 is a basic block diagram of a single beam transponder switching portion;
FIG. 4 is a graph of a simulated input signal spectrum distribution;
FIG. 5 is a graph of a simulated analysis filter bank spectrum;
fig. 6 is a graph of simulated signal spectral shift.
Detailed Description
The invention is described in detail below with reference to the figures and specific embodiments.
The invention relates to a digital channelized transponder realized based on FPGA, which mainly has the functions of changing and amplifying satellite signals and frequency, and forms a radio transceiving system together with a satellite transceiving antenna, and has the excellent performances of high sensitivity, large dynamic range, high test precision, long-term storage of digitized data and the like. When the repeater is designed, the processing capacity of the repeater on the broadband signal is considered, the transmission quality of the signal is improved, flexible channel switching and beam switching are realized, and approximate accurate analysis and synthesis of the broadband signal are realized.
The broadband repeater supports 2.6MHz channelized exchange forwarding and 200KHz channelized exchange forwarding, the forwarding modes can be switched under the control of software, the output spurs L and S, C are less than or equal to-55 dBc, the output spurs X, Ku and Ka are less than or equal to-50 dBc, the harmonic wave inhibition is less than or equal to 40dBc, and the outer band spurs inhibition is more than or equal to 50 dBc.
The invention relates to a digital channelized repeater system realized based on an FPGA (field programmable gate array), which comprises the following components: the system comprises a multi-channel receiving unit, a channel forwarding module and a multi-channel transmitting unit; therefore, the signal transmission with variable paths can be realized, the broadband signal transmission and the wave beam switching of the repeater are more flexible, and the efficiency and the effectiveness of the repeater are improved;
the multi-path receiving unit comprises a first band-pass filter BPF0, a low-noise amplifier module L NA, a down-conversion module D/C and a second band-pass filter BPF;
the first band-pass filter BPF0 receives a plurality of paths of satellite uplink signals from an external satellite receiving antenna, and selects required signals through the gating filtering of the first band-pass filter BPF 0;
the low-noise amplification module L NA is mainly used for amplifying the received weak signal, so as to facilitate subsequent processing;
the down-conversion module D/C mainly converts radio-frequency signals into intermediate-frequency signals, so that subsequent AD sampling is facilitated;
the second band-pass filter BPF mainly filters out frequency spectrum stray generated by nonlinear devices such as down-conversion devices, power amplifiers and the like, so that the signal quality is improved;
a channel forwarding module comprising: the AD sampling is realized by four FPGAs (field programmable gate arrays), the shunting module is realized by two FPGAs, the combining module is realized by four FPGAs, and a digital-analog conversion DAC (digital-analog converter); the FPGA is used for realizing the purpose of realizing the accurate analysis and synthesis of the broadband signal, and the high-speed switching network based on the FPGA can exchange each sub-band in the thinned broadband signal; meanwhile, the transmission quality of the signals can be greatly improved, the signals are subjected to channelization processing, flexible forwarding of multi-beam broadband signals can be realized, and the processing speed of the repeater on the signals is improved to a certain extent;
the AD sampling module is used for carrying out AD sampling on the analog intermediate frequency signals sent by the multipath receiving unit to obtain multipath digital intermediate frequency signals;
the shunting module is realized by four FPGAs, when a shunting clock arrives, the four FPGAs of the shunting module divide each path of digital intermediate-frequency signals into forty-eight paths of digital signals, the four FPGAs respectively divide the forty-eight paths of digital signals after frame synchronization signal synchronization, and can simultaneously perform capacity shunting in the aspects of channel division, multi-terminal, multi-service processing and the like, the algorithm used by the capacity shunting module is an analysis filter bank, and the filter function is as follows:
wherein the content of the first and second substances,and filter order N-M-D, N-mD + k (M-0, 1,2, …, M-1; k-0, 1,2, … D-1); d is the number of sub-band filters of the analysis filter bank, M is the order of the sub-band filters of the analysis filter bank, h is the coefficient of the sub-band filters of the analysis filter bank, and z is expressed in a complex number domain;
the switching module is realized by two FPGAs, 192 paths of signals are input into one FPGA in the switching module, the signals are transmitted to the other FPGA in the switching module after being switched according to a preset route, the FPGA carries out gain modulation on the switched multipath digital signals, and for input of n beams, each beam is divided into n channels to input data streams, so that a mathematical abstraction is given: the input data stream may be equivalently represented by a mathematical matrix of order n x n as follows:
each beam data in the data stream corresponds to row data of the matrix in _ data, and each subband in each beam corresponds to a position corresponding to a subband serial number in a corresponding row of the matrix in _ data. That is, a in the matrix in _ data11…a1nEquivalent to the first beam, a11Then corresponds to the first sub-band in a beam, whichThe rest is analogized in sequence;
the combiner module is realized by four FPGAs, an exchange module is equally divided into four paths which are respectively sent to the four FPGAs of the combiner module, each FPGA of the four FPGAs synthesizes one path of forty-eight paths to form four paths of digital intermediate frequency signals, the analysis filter bank and synthesis filter bank technology is used, full subband exchange between wave beams and subband exchange in the wave beams can be realized, the algorithm used by the combiner is a synthesis filter bank, and the filter function is as follows:
wherein the content of the first and second substances,k is 0,1,2, … K-1, K is the number of subband filters of the synthesis filter bank, h is the subband filter coefficient of the synthesis filter bank, j is an imaginary unit, e, pi is a constant, n is represented in the real domain;
the digital-to-analog conversion DAC is used for carrying out DA conversion on the combined data signal to obtain a plurality of paths of analog intermediate frequency signals and sending the analog intermediate frequency signals to a plurality of paths of transmitting units;
and a multipath transmitting unit. The method comprises the following steps: an up-conversion module U/C1, a second band-pass filter BPF2, a driving amplifier, a third band-pass filter BPF3 and a high-power amplifier HPA;
the up-conversion module U/C1 up-converts the analog signal intermediate frequency signal into a radio frequency signal;
the second band-pass filter BPF2 is mainly used for filtering out frequency spectrum stray generated by an up-conversion nonlinear device, and the output stray is preferably less than or equal to-50 dbc, so that the signal quality is improved;
the driving amplifier amplifies signals, so that a subsequent power amplifier can amplify the signals better;
the third band-pass filter BPF3 mainly filters out frequency spectrum stray generated by the amplifier nonlinear device, and the output stray requirement is less than or equal to-50 dbc, thereby improving the signal quality;
and the high-power amplifier HPA amplifies signals at high power and feeds the signals to a satellite transmitting antenna through an external antenna tuner.
The digital channelized repeater system realized based on the FPGA comprises the following required FPGA, an analog-to-digital conversion ADC, a digital-to-analog converter DAC, an up-conversion reference index and a power amplifier reference index:
the FPGA can select Virtex-6 series products, K7, Virtex-7 and the like of Xilinx.
The preferred scheme of the analog-to-digital conversion ADC is as follows: the sampling rate is 400MHz in narrow band and 1.6GHz in bandwidth; the quantization digit is more than 12 bits; spurious free dynamic range: not less than 55 dBc; and (3) outputting a signal-to-noise ratio: more than or equal to 50 dBc.
The preferred scheme of the DAC is as follows: the quantization digit is more than 12 bits; the output signal power is 0dBm +/-3 dB.
The low-noise L NA optimization scheme is that the working frequency is 6.424-6.765 GHz, the noise temperature is less than 80K, the gain is 55dB, the in-band fluctuation is +/-0.5, the 1dB compression point is 10dBm, the group delay characteristic is IESS-308, and the working temperature is-40- + 50.
The up-conversion preferred scheme is that the preferred wave band of the input frequency L is 140MHz, the output frequency is 3.55-3.7 GHz, the output level is +20.8dBm, the in-band fluctuation is +/-0.75, the gain is 45dB, the stray and phase noise is IESS-308, the level adjustment range is +/-10 dB, and the working temperature is-40- + 50.
The preferred scheme of the down-conversion is that the input frequency is 6.424-6.765 GHz preferably, the wave band of the output frequency L is 140MHz, the noise coefficient is less than 8, the in-band fluctuation is +/-0.75, the gain is 45dB, the stray and phase noise is IESS-308, the level adjustment range is +/-10 dB, and the working temperature is-40- + 50.
The preferred scheme of the power amplifier is as follows: the frequency is 6.424-6.765 GHz, the output level is +19.8dBm, the in-band fluctuation is +/-0.75, the gain is 45dB, and the local oscillator stability is less than or equal to 10-7Stray and phase noise are IESS-308, the level adjustment range is +/-10 dB, and the working temperature is-40- + 50.
Fig. 1 is a general structure diagram of the system, it can be seen from the figure that the present invention is composed of a multipath receiving unit, a channel forwarding module and a multipath transmitting unit, the multipath receiving unit is mainly composed of a first band pass filter BPF0, a low noise amplifier module L NA, a down conversion module D/C, a second band pass filter BPF, the channel forwarding module includes an a/D conversion module, an FPGA module, and a D/a conversion module, the multipath transmitting unit includes an up conversion module U/C1, a second band pass filter BPF2, a driving amplifier, a third band pass filter BPF3, and a high power amplifier hpa, the whole working flow of the system is:
(1) the first stage of the receiver is a low noise amplifier (L NA). this amplifier adds very little noise to the amplified carrier signal while making the carrier signal sufficiently amplified so that the carrier signal can withstand higher noise at the next converter stage.
(2) The frequency converter is composed of a mixer and a local oscillator and mainly completes the function of frequency conversion. The power drive from the local oscillator to the mixer input is about 10 dBm. The frequency of the oscillator must be highly stable and have low phase noise.
(3) The main function of the driving amplifier is to provide a large gain for the whole receiver, and the signal is converted into a proper intermediate frequency signal through the receiver.
(4) The channel forwarding module performs A/D conversion on received intermediate frequency signals, then enters a digital domain, then is processed through an FPGA (field programmable gate array), and then enters the FPGA with a high-speed switching function to perform multi-channel signal switching after multi-channel signals of signal demultiplexing are completed, the switched signals are processed through the FPGA, and then enter a multi-channel transmitting unit after multiplexing, namely combining, of the multi-channel signals is completed.
(5) The multi-path transmitting unit carries out analog up-conversion (U/C1) on the processed intermediate frequency signals, the BPF2 (band-pass filter) is sent to an HPA (high power amplifier) for amplification after passing through a PA (drive amplifying circuit) and a BPF3 (band-pass filter), and then the amplified signals are fed into a satellite transmitting antenna through an antenna tuner, so that the whole satellite-borne signal exchange process is completed.
Fig. 2 is a schematic diagram of a channel forwarding module, and the flow of the channel forwarding module is as follows:
(1) because the system needs to process data of multiple sub-channels (192 sub-channel signals are taken as an example in the invention), the invention considers the capability of an actual satellite and simulates different exchange capabilities among 4 paths of beams, so that the analog satellite transponder adopts 4 FPGA (FPGA 1-FPGA 4 in a shunting processing board) to respectively realize digital shunting of 4 paths of sub-channel signals of 48 paths, and a high-speed A/D sampling chip is configured on the shunting processing board.
(2) And 2 FPGAs (FPGA5 and FPGA6) are adopted to respectively realize the digital exchange function and the gain adjustment function among the 4 paths of sub-channels.
(3) And 4 FPGAs are adopted in the combining processing board to realize digital combining of 192 paths of sub-channel signals, and a high-speed D/A chip is configured. The FPGA can be selected from Virtex-6 series products and other types of FPGAs.
Fig. 3 is a block diagram showing a basic structure of a single-beam repeater switching part, and the operation principle of a branching processing board and a combining processing board of the repeater switching part is explained by taking one beam as an example, and the operation flow of the whole system is as follows:
(1) data enter the branch processing board and are converted into a plurality of inputs through the multiphase filter, and the scheme uses the FPGA to realize the function of the filter.
(2) The data processing speed is high, which is not convenient for the high-speed switching network part to process, so a CIC filter (as shown in Q in fig. 3) needs to be added for extraction, and the input data is subjected to speed reduction processing, so that the data enters the middle FPGA for the switching processing of the data.
(3) And the processed data enters the circuit combining board, and then interpolation processing is carried out on the processed data by using a CIC filter to improve the speed rate, and then the signal combination is completed.
The basic sub-band channel bandwidth is preferably 2.6MHz, the minimum sub-band channel bandwidth is 1.3MHz, Δ is 0.1MHz, it is assumed that there are 3 input signals, which respectively occupy 1,2, and 4 basic bandwidths, the initial minimum sub-band channel positions are 0, 2, and 6, the signal bandwidths are 2.4MHz, 4.8MHz, and 9.6MHz, a QPSK modulation method is adopted, and the roll-off coefficient is 0.25. The target is that the first signal is shifted to the right by 2 basic bandwidths, the second signal is shifted to the right by 4 basic bandwidths, and the third signal is shifted to the right by 10 basic bandwidths. The prototype filters of the analysis filter bank and the synthesis filter bank are open root raised cosine filters. The simulation results are shown in fig. 4, 5, and 6. FIG. 4 is a graph of the simulated input signal spectral distribution plot with the abscissa representing frequency domain units Hz and the ordinate representing amplitude units dB; FIG. 5 is a graph of a simulated analysis filter bank spectrum with the abscissa representing time units s and the ordinate representing amplitude units dB; the abscissa of the simulated signal spectral displacement diagram of fig. 6 represents the frequency domain units Hz and the ordinate represents the amplitude units dB. After the analysis filter bank, the frequency spectrums of the three signals are shown in fig. 6 after the extraction, interpolation and synthesis filter bank. Therefore, the invention can realize full subband switching between beams and subband switching in the beams.
The invention relates to a digital channelized forwarding method based on FPGA, comprising the following steps:
(1) a multi-path receiving unit for receiving multi-path satellite uplink signals from an external satellite receiving antenna,
(2) selecting a required signal from the multi-path satellite uplink signal in the step (1) through gating filtering;
(3) performing low-noise amplification on the signals required in the step (2), and performing down-conversion to obtain multiple paths of analog intermediate frequency signals;
(4) sending the multi-channel analog intermediate frequency signals in the step (3) to a channel demultiplexing module;
(5) the channel forwarding module carries out AD sampling on the analog intermediate frequency signals in the step (4) to obtain a plurality of paths of digital intermediate frequency signals;
(6) respectively carrying out signal shunting on the multi-path digital intermediate frequency signals in the step (5), and exchanging the shunted signals according to signal time slots;
(7) combining the signals after the time slot exchange in the step (6) to obtain combined data signals;
(8) DA conversion is carried out on the combined data signal to obtain a plurality of paths of analog intermediate frequency signals, and the analog intermediate frequency signals are sent to a plurality of paths of transmitting units;
(9) and the multi-path transmitting unit is used for carrying out up-conversion, band-pass filtering, power amplification and secondary band-pass filtering on the multi-path analog intermediate-frequency signals and feeding the multi-path analog intermediate-frequency signals into the satellite transmitting antenna through an external antenna tuner.
The invention can realize signal transmission with variable paths in the scheme design, is more flexible in the aspects of broadband signal transmission and wave beam switching of the transponder, and improves the efficiency and effectiveness of the transponder. The signal multiplexer and demultiplexer are realized by using FPGA, the precise analysis and synthesis of the broadband signal can be realized, and the high-speed switching network based on FPGA can exchange each sub-band in the thinned broadband signal.
The invention aims at providing a scheme design of a digital channelized repeater realized based on an FPGA (field programmable gate array), wherein the digital channelized repeater belongs to the class of processing repeaters, the design of the digital channelized repeater is realized by taking the FPGA as a hardware platform, the transmission quality of signals can be greatly improved, the signals are channelized, the flexible forwarding of multi-beam broadband signals can be realized, and the processing speed of the repeater on the signals is also improved to a certain extent.
The broadband satellite transponder breaks through barriers faced by the development of the traditional satellite communication system, and gives the satellite forwarding system the capability of simultaneously carrying out channel division, multi-terminal, multi-service processing and the like. The invention adopts the technology of an analysis filter bank and a synthesis filter bank in the scheme design, and can realize the full subband exchange between beams and the subband exchange in the beams.
The embodiments of the present invention have been described in detail with reference to the drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention.

Claims (7)

1. A digital channelized repeater system implemented based on an FPGA, comprising: the system comprises a multi-channel receiving unit, a channel forwarding module and a multi-channel transmitting unit;
the multi-path receiving unit receives multi-path satellite uplink signals from an external satellite receiving antenna, selects required signals through gating filtering, and obtains multi-path analog intermediate frequency signals through low-noise amplification and down-conversion; sending the multi-channel analog intermediate frequency signals to a channel forwarding module;
the channel forwarding module is used for AD sampling the analog intermediate frequency signals to obtain a plurality of paths of digital intermediate frequency signals, respectively carrying out signal shunting on the plurality of paths of digital intermediate frequency signals, exchanging the shunted signals according to signal time slots, combining the exchanged signals to obtain a combined data signal, carrying out DA conversion on the combined data signal to obtain a plurality of paths of analog intermediate frequency signals, and sending the plurality of paths of analog intermediate frequency signals to the plurality of paths of transmitting units;
the multi-path transmitting unit is used for carrying out up-conversion, band-pass filtering, power amplification and secondary band-pass filtering on the multi-path analog intermediate-frequency signals and feeding the multi-path analog intermediate-frequency signals into a satellite transmitting antenna through an external antenna tuner;
a channel forwarding module comprising: the device comprises an AD sampling module, a shunt module, an exchange module, a combining module and a DA conversion module;
a switching module comprising: an FPGA module;
the AD sampling module is used for AD sampling the analog intermediate frequency signals sent by the multipath receiving unit to obtain multipath digital intermediate frequency signals, the multipath digital intermediate frequency signals are respectively subjected to signal shunting by the shunting module, signals after shunting are controlled by the FPGA module to be exchanged according to a preset route, the exchanged signals are combined by the combining module to obtain combined data signals, the combined data signals are subjected to DA conversion by the DA conversion module to obtain multipath analog intermediate frequency signals, and the multipath analog intermediate frequency signals are sent to the multipath transmitting unit;
the shunting module is realized by four FPGAs, the switching module is realized by two FPGAs, and the combining module is realized by four FPGAs;
when the multipath receiving unit receives four paths of satellite uplink signals and generates four paths of analog intermediate frequency signals, after AD conversion is carried out, when a shunting clock arrives, four FPGAs of a shunting module divide each path of digital intermediate frequency signals into forty-eight paths of digital signals, the four FPGAs respectively send the forty-eight paths of digital signals to one FPGA of an exchange module after frame synchronization signals are synchronized, 192 paths of signals are input into one FPGA of the exchange module, one FPGA of the exchange module carries out exchange according to a preset route and then sends the signals to the other FPGA of the exchange module, the other FPGA of the exchange module carries out gain modulation on the exchanged multipath digital signals, the four paths of signals are equally divided into four paths and respectively sent to the four FPGAs of a combining module, and the forty-eight paths of signals are combined into one path by each FPGA of the four FPGAs of the combining module to form the four paths of digital intermediate frequency signals.
2. The digital channelized repeater system realized based on FPGA according to claim 1 is characterized in that the multi-path receiving unit comprises a first band-pass filter BPF0, a low noise amplifier module L NA, a down-conversion module D/C, a second band-pass filter BPF;
the first band-pass filter BPF0 receives multiple satellite uplink signals from an external satellite receiving antenna, selects required signals through gating filtering of the first band-pass filter BPF0, performs low-noise amplification on the signals through the low-noise amplification module L NA, performs down-conversion through the down-conversion module D/C, performs re-filtering through the second band-pass filter BPF2 to obtain multiple analog intermediate-frequency signals, and sends the multiple analog intermediate-frequency signals to the channel forwarding module.
3. The digital channelized repeater system implemented based on FPGA of claim 1, wherein: a multipath transmitting unit; the method comprises the following steps: an up-conversion module U/C1, a second band-pass filter BPF2, a driving amplifier, a third band-pass filter BPF3 and a high-power amplifier HPA;
the up-conversion module U/C1 up-converts the multi-channel analog intermediate frequency signals sent by the channel forwarding module, performs band-pass filtering through the second band-pass filter BPF2, performs power amplification through the driving amplifier, performs secondary band-pass filtering through the third band-pass filter BPF3, performs high-power amplification through the high-power amplifier HPA, and feeds the signals to the satellite transmitting antenna through the external antenna tuner.
4. The digital channelized repeater system implemented based on FPGA of claim 1, wherein: and the FPGA of the shunt module divides each path of digital intermediate-frequency signal into forty-eight paths of digital signals by adopting an analysis filter bank.
5. The digital channelized repeater system implemented based on FPGA of claim 4, wherein: the filter function of the analysis filter bank is related to the number D of the sub-band filters of the analysis filter bank, the order M of the sub-band filters of the analysis filter bank, and the coefficient h of the sub-band filters of the analysis filter bank.
6. The digital channelized repeater system implemented based on FPGA of claim 1, wherein: an FPGA in the switching module performs route switching according to a preset switching matrix, and for n beam inputs, each beam is divided into n channel input data streams, and a mathematical abstraction is given as follows: the input data stream may represent the switching matrix equivalently using a mathematical matrix of order n x n.
7. The digital channelized repeater system implemented based on FPGA of claim 1, wherein: the FPGA of the combiner module combines forty-eight paths into one path by adopting a synthesis filter bank to form four paths of digital intermediate frequency signals.
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