CN108897490A - A kind of data managing method of the heterogeneous mixing memory system of DRAM/PRAM - Google Patents
A kind of data managing method of the heterogeneous mixing memory system of DRAM/PRAM Download PDFInfo
- Publication number
- CN108897490A CN108897490A CN201810455421.1A CN201810455421A CN108897490A CN 108897490 A CN108897490 A CN 108897490A CN 201810455421 A CN201810455421 A CN 201810455421A CN 108897490 A CN108897490 A CN 108897490A
- Authority
- CN
- China
- Prior art keywords
- data page
- write
- fritter
- dram
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0611—Improving I/O performance in relation to response time
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
- G06F12/121—Replacement control using replacement algorithms
- G06F12/122—Replacement control using replacement algorithms of the least frequently used [LFU] type, e.g. with individual count value
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/064—Management of blocks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
- G06F3/0647—Migration mechanisms
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The present invention discloses a kind of data managing method of heterogeneous mixing memory system of DRAM/PRAM.Method of the invention increases write record table and data transferring module for the mixing memory system of the PRAM collocation DRAM of large capacity in Memory Controller Hub；Write record table creates write record entry according to the address for being write internal storage data page, and the information of entry includes that data page address and internal storage data are write number；Data Migration module periodic reading write record table, and frequent data will be write and moved in DRAM from PRAM.
Description
Technical field
The present invention relates to a kind of data managing methods of the heterogeneous mixing memory system of DRAM/PRAM, for a kind of DRAM and
The heterogeneous mixing memory system that PRAM is constituted realizes that mixing main-memory data management, data energy consumption is write in reduction, extends and uses the longevity
Life.
Background technique
Memory is the important feature in computer system, main to store the data from disk, accesses and uses for processor.
The memory of traditional DRAM medium must constantly refresh circuit be to keep data, so that memory occupies the very big ratio of system energy consumption
Example.With being continuously increased for capacity, the energy consumption problem of memory is more serious.Compared to DRAM, phase-change RAM
(PRAM) it due to non-volatile, does not need to continue to refresh to keep data, therefore energy consumption is greatly reduced.Secondly, PRAM is with higher
Storage density, be 2 to 4 times of DRAM, have preferably expansibility.But PRAM also has the deficiency of its own, such as longer
The write operation time and bigger write energy consumption.On the contrary, such problems is then not present in DRAM.
Due to the complementarity of PRAM and DRAM advantage, the integrated heterogeneous mixing memory system of construction of the two is just become very certainly
So.The usually PRAM of large capacity and the DRAM collocation compared with low capacity use.Data in memory system are using data page as granularity
Management, the size of each data page are generally 8KB to 32KB, and each data page has corresponding logical address and physical address.It patrols
Volume address is distributed by operating system, and the physical address then actual storage locations of determination data page in memory.
Memory system serves caching system upwards, receives the reading and writing data access from caching.The management of caching system
Granularity is cache blocks, generally less than internal storage data page, so the read and write access from caching, finally implements to some specific memory
The specific data page fritter of data page.Memory system after data reach mixing memory, is acquiescently deposited downwards from disk access data
It is put into the PRAM of large capacity.Because writing energy consumption and writing the time for PRAM is greater than DRAM, if the data page in PRAM by
It continually writes, just will affect the energy consumption and performance of system.
Therefore consider to move to the data page frequently write in DRAM.But data page migration will also consume resource and energy
Consumption.Number analysis is write according to data page, the frequency that the different data page fritter in same data page is write has differences,
Some data page fritters are write much, and some data page fritters are write few；Moreover, the data page fritter in different data page is write mould
Formula there is also difference, all write much by all pages of fritters in some data pages, only has partial page fritter to be write in some data pages
Much, how all pages of fritters in data page also are not all write.Most wise way be only to write in data page frequency
Numerous data page fritter carries out Data Migration.On the one hand evade the high energy consumption and long delay of data write operation in PRAM, it is another
Face reduces the cost of Data Migration, plays the advantage of mixing memory to the maximum extent.
Summary of the invention
The present invention will overcome the drawbacks described above of the prior art, provide a kind of number of heterogeneous mixing memory system of DRAM/PRAM
According to management method.
The contents of the present invention and feature are exactly：For the optimization data management of the DRAM and PRAM heterogeneous mixing memory constituted
Method.Main feature includes：The write record table of internal storage data page is write in creation, and the data page fritter in internal storage data page moves
It moves, the data page fritter replacement in DRAM.
A kind of data managing method of the heterogeneous mixing memory system of DRAM/PRAM of the invention, walks comprising technology below
Suddenly：
1) the write record table of internal storage data page is write in creation；
When writing internal storage data page operations, write record table will record the address for being write internal storage data page, and by memory
Data page is divided into N number of adjacent datapages fritter of same size, and corresponding each data page fritter creates one 4 countings
Value；Write operation due to writing internal storage data page eventually falls on some specific data page fritter, so write record table can be to the number
According to the logger cumulative 1 of page fritter；
2) migration of the data page fritter in internal storage data page；
Internal storage data page is acquiescently preferably stored in the PRAM of mixing memory, Data Migration module scans write record table,
It was found that the logger value of some data page fritter is greater than the threshold values being previously set in some internal storage data page, then it is responsible for the data
Page fritter moves in DRAM from PRAM；
3) the data page fritter replacement in DRAM；
The data page fritter for moving to DRAM sorts according to recent visit number, then will be nearest when dram space deficiency
The least data page fritter of access times replaces out DRAM and writes back disk, while investigating and belonging to one with current data page fritter
The position of other data page fritters of data page, decides whether to write back disk.
It is an advantage of the invention that：Traditional mixing EMS memory management process is as unit of data page, and the management grain of this method
The data page fritter in smaller-data page is spent, the data page fritter frequently write in data page is moved into DRAM from PRAM, one
Aspect can reduce the cost of Data Migration, on the other hand can evade that frequently PRAM is write high energy consumption caused by data and grown and prolong
When, with smaller cost, the advantage of mixing memory is played to the maximum extent.
Detailed description of the invention
Fig. 1 is the DRAM/PRAM mixing internal storage structure figure of the method for the present invention.
Fig. 2 is the write record table of the method for the present invention.
Specific embodiment
With reference to the accompanying drawing, the technical solution of the method for the present invention is further illustrated.
Fig. 1 is DRAM/PRAM mixing internal storage structure figure, and MC therein is Memory Controller Hub, realizes write record table (Write
Tracking Table) and data transferring module (Data Transfer Module).Write record table includes to be write page
Write record entry, each entry include two-part content, and first part is the address Addr for being write memory, followed by every number
Counter is write according to page fritter is corresponding, the case where page shown in Fig. 2 is divided into 4 data page fritters.Data Migration module can
To access the data in write record table.Entry information in Data Migration module timing scan write record table, by data page fritter
The data page fritter that count value is greater than given threshold values moves to DRAM from PRAM.
A kind of data managing method of the heterogeneous mixing memory system of DRAM/PRAM of the invention, walks comprising technology below
Suddenly：
1. the write record table that internal storage data page is write in creation；
Shown in Fig. 1, when generation caching (Cache) writes internal storage data page, searching, which whether there is in write record table, includes the number
According to the entry of page address.If not provided, write record table creates new entry, new item is set by the address for currently being write data page
Purpose Addr value, corresponding each data page fritter create 4 binary count values and are initialized as 1111 expression data pages
In PRAM；Then it navigates to and writes the page fritter that data actually occur, be by 1111 transposition by the count value of this page of fritter
0001, it indicates that a write operation occurs.If having existed the entry comprising being write data page address in write record table, position
To the page fritter writing data and actually occurring, the count value of page fritter is set according to following several situations.Situation 1：Count value is
If 1111, then being 0001 by count value transposition；Situation 2：Count value is 0000, indicates that page fritter has migrated to DRAM,
It does not need to operate；Situation 3:Count value is greater than 0001 and is less than threshold values, then by count 1.
2. the migration of the data page fritter in internal storage data page；
Data Migration module periodically scans for write record table, and positioning count value is greater than the data page fritter of threshold values, determines
For the target of migration.Because Data Migration will occupy the bandwidth of system, normal data access is influenced, so will be to migratory behaviour
It is scheduled.Data Migration includes two steps：From reading data page fritter in PRAM and it is written in DRAM.Due in memory
It is realized in controller, Data Migration module monitors the data bandwidth of DRAM and PRAM in which can be convenient.Only as PRAM and DRAM
It is in idle condition, Data Migration module can just initiate data migration operation.
Data page fritter replacement in 3.DRAM；
DRAM migrates the internal storage data page fritter that comes from PRAM using chain table organization.The data page fritter of identical access times
Information preservation in same chained list, different chained lists sorts from small to large by access frequency, and periodically adjusts number
According to position of the small block message of page in chained list or even affiliated chained list.When some data page fritter p moves to DRAM, acquiescently will
Its information is placed in the head of the moderate chained list of access frequency.Periodically investigate data page fritter p by read-write situation, do not have
Have and read and write, then the information of data page fritter p is slowly mobile to chained list tail portion from chained list head, until the letter of data page fritter p
Breath removes current chained list, moves into the chained list of access frequency time level-one.On the contrary, if data page fritter p is continually read and write,
Then the information of p is mobile from the tail portion of current chained list to head, enters access until the information of data page fritter p removes current chained list
The higher leveled chained list of frequency.Therefore what is saved in the chained list of the access minimum level-one of frequency is all to be read and write least frequent data
The information of page fritter.When dram space deficiency, the chained list of the access minimum level-one of frequency is found, successively according to data page fritter
Information locating replaces out DRAM to data page fritter.How the data page fritter replaced out is handled？Situation 1 belongs to a number
When being replaced together according to all pages of fritters of page, then disk is write back to；Situation 2 only belongs to the part number an of data page
When being replaced according to page fritter, check whether that the data page fritter for also belonging to same data page is located in PRAM？If so, then will
Data page fritter remaining in PRAM is also write back into disk simultaneously；Otherwise it is directly written back to disk.
Content described in this specification embodiment is only enumerating to the way of realization of inventive concept, protection of the invention
Range should not be construed as being limited to the specific forms stated in the embodiments, and protection scope of the present invention is also and in art technology
Personnel conceive according to the present invention it is conceivable that equivalent technologies mean.
Claims (1)
1. a kind of data managing method of the heterogeneous mixing memory system of DRAM/PRAM, includes the following steps：
1) the write record table of internal storage data page is write in creation；
When writing internal storage data page operations, write record table will record the address for being write internal storage data page, and by internal storage data
Page is divided into N number of adjacent datapages fritter of same size, and corresponding each data page fritter creates one 4 count values；By
Some specific data page fritter is eventually fallen in the write operation for writing internal storage data page, so write record table can be small to the data page
The logger of block cumulative 1；
2) migration of the data page fritter in internal storage data page；
Internal storage data page is acquiescently preferably stored in the PRAM of mixing memory, Data Migration module scans write record table, discovery
The logger value of some data page fritter is greater than the threshold values being previously set in some internal storage data page, then is responsible for the data page is small
Block moves in DRAM from PRAM；
3) the data page fritter replacement in DRAM；
The data page fritter for moving to DRAM sorts according to recent visit number, when dram space deficiency, then by recent visit
The least data page fritter of number replaces out DRAM and writes back disk, while investigating and belonging to a data with current data page fritter
The position of other data page fritters of page, decides whether to write back disk.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810455421.1A CN108897490A (en) | 2018-05-14 | 2018-05-14 | A kind of data managing method of the heterogeneous mixing memory system of DRAM/PRAM |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810455421.1A CN108897490A (en) | 2018-05-14 | 2018-05-14 | A kind of data managing method of the heterogeneous mixing memory system of DRAM/PRAM |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108897490A true CN108897490A (en) | 2018-11-27 |
Family
ID=64342850
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810455421.1A Pending CN108897490A (en) | 2018-05-14 | 2018-05-14 | A kind of data managing method of the heterogeneous mixing memory system of DRAM/PRAM |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108897490A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109656482A (en) * | 2018-12-19 | 2019-04-19 | 哈尔滨工业大学 | It is a kind of that hot Web page predicting method is write based on memory access |
| CN110109614A (en) * | 2019-03-22 | 2019-08-09 | 浙江工商大学 | Data migration method based on probability towards PRAM/DRAM mixing memory |
| CN110347510A (en) * | 2019-07-09 | 2019-10-18 | 中国科学院微电子研究所 | A kind of management method, system, equipment and medium mixing memory |
| CN110543433A (en) * | 2019-08-30 | 2019-12-06 | 中国科学院微电子研究所 | Data migration method and device of hybrid memory |
| CN110706733A (en) * | 2019-08-13 | 2020-01-17 | 浙江工商大学 | DRAM memory row disturbance error solution method |
| CN114281247A (en) * | 2021-11-29 | 2022-04-05 | 深圳三地一芯电子有限责任公司 | Flash bandwidth allocation method and device based on mixed media |
| WO2022068760A1 (en) * | 2020-09-30 | 2022-04-07 | 华为技术有限公司 | Method for memory management, and apparatus for same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140173234A1 (en) * | 2012-12-13 | 2014-06-19 | Samsung Electronics Co., Ltd. | Semiconductor memory device and memory system |
| CN103914406A (en) * | 2014-03-31 | 2014-07-09 | 中国科学院微电子研究所 | Migration method and system of hybrid memory |
| CN106909323A (en) * | 2017-03-02 | 2017-06-30 | 山东大学 | The caching of page method of framework is hosted suitable for DRAM/PRAM mixing and mixing hosts architecture system |
| CN107193646A (en) * | 2017-05-24 | 2017-09-22 | 中国人民解放军理工大学 | A kind of high-efficiency dynamic paging method that framework is hosted based on mixing |
-
2018
- 2018-05-14 CN CN201810455421.1A patent/CN108897490A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140173234A1 (en) * | 2012-12-13 | 2014-06-19 | Samsung Electronics Co., Ltd. | Semiconductor memory device and memory system |
| CN103914406A (en) * | 2014-03-31 | 2014-07-09 | 中国科学院微电子研究所 | Migration method and system of hybrid memory |
| CN106909323A (en) * | 2017-03-02 | 2017-06-30 | 山东大学 | The caching of page method of framework is hosted suitable for DRAM/PRAM mixing and mixing hosts architecture system |
| CN107193646A (en) * | 2017-05-24 | 2017-09-22 | 中国人民解放军理工大学 | A kind of high-efficiency dynamic paging method that framework is hosted based on mixing |
Non-Patent Citations (1)
| Title |
|---|
| 章铁飞: ""基于程序访存模式的存储系统节能技术研究"", 《中国博士学位论文全文数据库信息科技辑》 * |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109656482A (en) * | 2018-12-19 | 2019-04-19 | 哈尔滨工业大学 | It is a kind of that hot Web page predicting method is write based on memory access |
| CN109656482B (en) * | 2018-12-19 | 2022-03-25 | 哈尔滨工业大学 | Write hot page prediction method based on memory access |
| CN110109614A (en) * | 2019-03-22 | 2019-08-09 | 浙江工商大学 | Data migration method based on probability towards PRAM/DRAM mixing memory |
| CN110109614B (en) * | 2019-03-22 | 2022-02-18 | 浙江工商大学 | Probability-based data migration method for PRAM/DRAM (random access memory/dynamic random access memory) |
| CN110347510A (en) * | 2019-07-09 | 2019-10-18 | 中国科学院微电子研究所 | A kind of management method, system, equipment and medium mixing memory |
| CN110706733A (en) * | 2019-08-13 | 2020-01-17 | 浙江工商大学 | DRAM memory row disturbance error solution method |
| CN110543433A (en) * | 2019-08-30 | 2019-12-06 | 中国科学院微电子研究所 | Data migration method and device of hybrid memory |
| CN110543433B (en) * | 2019-08-30 | 2022-02-11 | 中国科学院微电子研究所 | Data migration method and device of hybrid memory |
| WO2022068760A1 (en) * | 2020-09-30 | 2022-04-07 | 华为技术有限公司 | Method for memory management, and apparatus for same |
| CN114281247A (en) * | 2021-11-29 | 2022-04-05 | 深圳三地一芯电子有限责任公司 | Flash bandwidth allocation method and device based on mixed media |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108897490A (en) | A kind of data managing method of the heterogeneous mixing memory system of DRAM/PRAM | |
| CN107193646B (en) | High-efficiency dynamic page scheduling method based on mixed main memory architecture | |
| CN107844269B (en) | Hierarchical hybrid storage system based on consistent hash | |
| US6732241B2 (en) | Technique for migrating data between storage devices for reduced power consumption | |
| CN102364474B (en) | Metadata storage system for cluster file system and metadata management method | |
| US11188262B2 (en) | Memory system including a nonvolatile memory and a volatile memory, and processing method using the memory system | |
| CN101620572B (en) | Nonvolatile memory and control method | |
| CN103150136B (en) | Implementation method of least recently used (LRU) policy in solid state drive (SSD)-based high-capacity cache | |
| CN108829341B (en) | Data management method based on hybrid storage system | |
| CN108762671A (en) | Hybrid memory system based on PCM and DRAM and management method thereof | |
| CN101819509A (en) | Solid state disk read-write method | |
| CN104899154B (en) | The page management method hosted is mixed based on embedded system | |
| CN108121670B (en) | Mapping method for reducing solid state disk metadata back-flushing frequency | |
| KR20100065786A (en) | Cache synchronization method and system for fast power-off | |
| CN101777028A (en) | Realization method and device of mixed secondary storage system | |
| CN102981979B (en) | A kind of method improving memory system data access speed | |
| CN109388341A (en) | A kind of system storage optimization method based on Device Mapper | |
| CN106909323B (en) | Page caching method suitable for DRAM/PRAM mixed main memory architecture and mixed main memory architecture system | |
| CN102999441A (en) | Fine granularity memory access method | |
| US10275363B2 (en) | Cuckoo caching | |
| CN108710581A (en) | Bloom filter-based PCM storage medium wear leveling method | |
| US20100257312A1 (en) | Data Storage Methods and Apparatus | |
| CN108647157A (en) | A kind of mapping management process and solid state disk based on phase transition storage | |
| CN102520885A (en) | Data management system for hybrid hard disk | |
| CN108563586B (en) | Method for separating garbage recovery data and user data in solid-state disk |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20181127 |