CN108628726B - CPU state information recording method and device - Google Patents
CPU state information recording method and device Download PDFInfo
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- CN108628726B CN108628726B CN201710174630.4A CN201710174630A CN108628726B CN 108628726 B CN108628726 B CN 108628726B CN 201710174630 A CN201710174630 A CN 201710174630A CN 108628726 B CN108628726 B CN 108628726B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3024—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a central processing unit [CPU]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44521—Dynamic linking or loading; Link editing at or after load time, e.g. Java class loading
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
- G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
Abstract
The invention provides a method and a device for recording a CPU state, wherein the method comprises the following steps: when the program is executed to a preset instruction, acquiring a storage address from the preset instruction; the preset instruction is inserted into a designated position of the program and used for indicating and recording the state information of the CPU in the current program period, and recording the state information into a storage unit corresponding to a designated storage space which is independent of the storage space where the program is located according to the storage address. In order to realize the recording of the CPU state information when the program is executed, the invention divides a designated storage space from the memory of the CPU independently, the designated storage space is independent of the storage space of the program, the designated storage space is used for storing the CPU state information specially, and because the CPU state information is stored, when the CPU runs and has a fault, the reason of the fault can be analyzed according to the recorded CPU state information, thereby being convenient for eliminating and avoiding the fault.
Description
Technical Field
The invention relates to the technical field of computers, in particular to a method and a device for recording CPU state information.
Background
Currently, there are various diagnostic schemes for a Central Processing Unit (CPU), for example, running states in the CPU can be detected by a watchdog, and a system is reset once a program pointer is abnormal. For another example, each part of the CPU is detected by writing specific code, and the system is down in a software manner after the detection fails.
The existing CPU diagnosis technology is based on the consideration of system safety, and when a CPU fails, the system is directly reset or crashed to avoid the system from accidents. However, when the CPU fails, the system is directly reset or crashed, so that the operation and maintenance personnel cannot deeply know the reason of the failure of the CPU, and thus the reoccurrence of similar failures cannot be fundamentally avoided or eliminated.
Disclosure of Invention
The present invention is directed to solving, at least to some extent, one of the technical problems in the related art.
Therefore, an object of the present invention is to provide a method for recording CPU status information, which is used to record CPU status information, so as to solve the problem that the operation and maintenance personnel cannot deeply know the reason of the CPU failure because the system is directly reset or down when the CPU fails.
Another object of the present invention is to provide a CPU state information recording apparatus.
In order to achieve the above object, a method for recording CPU state information according to an embodiment of the first aspect of the present invention includes:
when a program is executed to a preset instruction, acquiring a storage address from the preset instruction; the preset instruction is inserted into a specified position of the program and used for indicating and recording the state information of the CPU in the current program period;
recording the state information into a corresponding storage unit of a designated storage space according to the storage address; wherein the designated storage space is independent of the storage space of the program.
As an optional implementation manner of the embodiment of the first aspect of the present invention, before the obtaining, when the program executes to the preset instruction, a storage address from the preset instruction, the method further includes:
acquiring a pre-compiled scattered loading file; the distributed loading file comprises allocation information of the CPU memory, wherein the allocation information at least comprises a starting address and a size of the specified storage space;
and determining the designated storage space from the memory according to the scattered loading file.
As an optional implementation manner of the embodiment of the first aspect of the present invention, the determining, according to the scatter load file, the specified storage space from the memory includes:
compiling the scattered loading file through a compiler to generate an image file;
and determining the designated storage space from the memory according to the image file.
As an optional implementation manner of the embodiment of the first aspect of the present invention, the method further includes:
and setting the attribute of the designated storage space as a non-initializable variable.
As an optional implementation manner of the embodiment of the first aspect of the present invention, the method further includes:
and recording the state information of the CPU in N program periods in the appointed storage space by taking the current program period as a starting point.
As an optional implementation manner of the embodiment of the first aspect of the present invention, the method further includes:
and determining the value of the N according to the size of the specified storage space.
As an optional implementation manner of the embodiment of the first aspect of the present invention, the method further includes: the allocation information also includes the start address and size of the ROM, the start address and size of the RAM, and the start position and size of the stack.
As an optional implementation manner of the embodiment of the first aspect of the present invention, the method further includes: and determining the ROM, the RAM and the stack from the memory according to the image file.
As an optional implementation manner of the embodiment of the first aspect of the present invention, the method further includes: the allocation information further includes: the RAM includes a load area and an execution area of the program, a start address and a size of the load area, and a start address and a size of the execution area.
As an optional implementation manner of the embodiment of the first aspect of the present invention, when the program is executed to a preset instruction, the obtaining a storage address from the preset instruction includes:
receiving an instruction to execute the program;
loading the program in the loading area to the execution area according to the starting address of the loading area;
executing the program within the execution area starting from a start address of the execution area;
and when the preset instruction inserted into the program is executed, acquiring the storage address from the preset instruction.
In the method for recording CPU state information provided in the embodiment of the first aspect of the present invention, a specified storage space is separately partitioned from a memory of a CPU, the specified storage space is independent of a storage space where a program is located, and the specified storage space is used to store CPU state information.
In order to achieve the above object, a CPU state information recording apparatus according to an embodiment of a second aspect of the present invention includes:
the first acquisition module is used for acquiring a storage address from a preset instruction when a program is executed to the preset instruction; the preset instruction is inserted into a specified position of the program and used for indicating and recording the state information of the CPU in the current program period;
the recording module is used for recording the state information into a corresponding storage unit of the designated storage space according to the storage address; wherein the designated storage space is independent of the storage space of the program.
As an optional implementation manner of the embodiment of the second aspect of the present invention, the apparatus further includes:
the second acquisition module is used for acquiring a pre-programmed dispersed loading file before the first acquisition module acquires a storage address from a preset instruction when a program is executed to the preset instruction; the distributed loading file comprises allocation information of the CPU memory, wherein the allocation information at least comprises a starting address and a size of the specified storage space;
and the determining module is used for determining the specified storage space from the memory according to the scattered loading file.
As an optional implementation manner of the embodiment of the second aspect of the present invention, the determining module is specifically configured to compile the dispersed loaded file by using a compiler to generate an image file, and determine the specified storage space from the memory according to the image file.
As an optional implementation manner of the embodiment of the second aspect of the present invention, the apparatus further includes:
and the preset module is used for setting the attribute of the specified storage space as a non-initializable variable.
As an optional implementation manner of the embodiment of the second aspect of the present invention, the recording module is specifically configured to record, in the designated storage space, state information of the CPU in N program cycles ahead with a current program cycle as a starting point.
As an optional implementation manner of the embodiment of the second aspect of the present invention, the recording module is further configured to determine the value of N according to the size of the specified storage space.
As an optional implementation manner of the embodiment of the second aspect of the present invention, the allocation information further includes a start address and a size of the ROM, a start address and a size of the RAM, and a start position and a size of the stack.
As an optional implementation manner of the embodiment of the second aspect of the present invention, the determining module is further configured to determine the ROM, the RAM, and the stack from the memory according to the image file.
As an optional implementation manner of the embodiment of the second aspect of the present invention, the allocation information further includes: the RAM includes a load area and an execution area of the program, a start address and a size of the load area, and a start address and a size of the execution area.
As an optional implementation manner of the embodiment of the second aspect of the present invention, the first obtaining module includes:
a receiving unit configured to receive an instruction to execute the program;
a loading unit, configured to load the program in the loading area into the execution area according to a start address of the loading area;
an execution unit for executing the program within the execution area starting from a start address of the execution area;
an obtaining unit, configured to obtain the storage address from the preset instruction when the preset instruction inserted into the program is executed.
In the CPU state information recording apparatus according to the second aspect of the present invention, a designated storage space is separately partitioned from a memory of the CPU, the designated storage space is independent of a storage space where the program is located, and the designated storage space is used to store the CPU state information.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a schematic flowchart of a method for recording CPU state information according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating another method for recording CPU status information according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of an image file according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a CPU status information recording apparatus according to an embodiment of the present invention;
FIG. 5 is a schematic structural diagram of another CPU status information recording apparatus according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a first obtaining module 11 according to an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar modules or modules having the same or similar functionality throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention. On the contrary, the embodiments of the invention include all changes, modifications and equivalents coming within the spirit and terms of the claims appended hereto.
A CPU state information recording method and apparatus of an embodiment of the present invention is described below with reference to the accompanying drawings.
Fig. 1 is a schematic flow chart of a method for recording CPU state information according to an embodiment of the present invention. As shown in fig. 1, the CPU state information recording method includes the steps of:
s101, when a program is executed to a preset instruction, a storage address is obtained from the preset instruction.
The preset instruction is inserted into a designated position of a program and used for indicating and recording the state information of the CPU in the current program period.
And S102, recording the state information into a corresponding storage unit of the designated storage space according to the storage address.
The problem that operation and maintenance personnel cannot deeply know the reason of the CPU failure due to the fact that the system is directly reset or crashed when the CPU fails is solved. In this embodiment, a storage space independent of the storage space where the program is located is allocated in advance from the memory of the CPU, and is referred to as a designated storage space herein, where the designated storage space is used to store the CPU state information in the program cycle.
Further, a preset instruction is inserted into a designated position of the program, and the preset instruction is used for indicating and recording the state information of the CPU in the current program cycle. When the program is executed to the preset instruction, the state information of the CPU is determined to be recorded, and the storage address is obtained from the preset instruction. After the storage address is acquired, the state information of the CPU can be recorded in the storage unit corresponding to the designated storage space according to the storage address, that is, the state information of the CPU can be located in the corresponding storage unit from the designated storage space according to the storage address, and then written in the corresponding storage unit.
For example, because the assembly language can access the memory location corresponding to the memory address, a piece of assembly code can be inserted at a designated position of the program main loop, and the state information of the CPU in the current program cycle can be recorded to the designated memory space through the assembly code. The assembly code includes a memory address of a memory cell to which the state information of the CPU is written. After the program is executed to the assembly code, the storage address can be read from the assembly code, then the corresponding storage unit of the designated storage space is directly accessed, and the state information of the CPU is written into the storage unit.
In the method for recording CPU state information provided in this embodiment, when a program is executed to a preset instruction, a storage address is obtained from the preset instruction; the preset instruction is inserted into a designated position of the program and used for indicating and recording the state information of the CPU in the current program period, and recording the state information into a storage unit corresponding to a designated storage space which is independent of the storage space where the program is located according to the storage address. In order to record the state information of the CPU during program execution, in this embodiment, a designated storage space is separately partitioned from a memory of the CPU, the designated storage space is independent of a storage space where the program is located, the designated storage space is used to store the state information of the CPU, and because the state information of the CPU is stored, when a fault occurs during CPU operation, the reason of the fault occurrence can be analyzed according to the previously recorded state information of the CPU, thereby facilitating the elimination and avoidance of the fault.
Fig. 2 is a flowchart illustrating a method for recording CPU state information according to an embodiment of the present invention. As shown in fig. 2, the CPU state information recording method includes the steps of:
s201, acquiring a pre-edited scattered loading file.
A scatter load (scatter) file is a text file that, as far as program execution is concerned, behaves like a map. After the program is written and compiled, the program needs to be burned into the physical CPU to run. In the burning process, the storage of the program and the data is guided by the scattered loading file. Scatter load file it can be used to describe the information needed by the connector to generate the image file. A distributed loading file is written to specify how to distribute codes of a program, read-only data, readable and writable data, uninitialized data and other storage addresses of various data when a connector of a Reduced Instruction Set (short for short) microprocessor (ARM) generates an image file.
In order to allocate a designated storage space from the memory for storing the CPU state information, in this embodiment, the distributed load file may be modified or written in advance to implement allocation of the designated storage space. Specifically, the distributed load file includes allocation information of the CPU memory, where the allocation information includes a start address and a size of the designated storage space.
S202, determining a designated storage space from the memory according to the scattered loading file.
Specifically, after the written dispersed loading file is obtained, the dispersed loading file is compiled through a compiler to generate an image file. Fig. 3 is a schematic structural diagram of an image file. Specifically, one image file includes a plurality of domains (regions), one domain includes a plurality of output sections (output sections), each output section (output section) includes a plurality of input sections (input sections), and the input sections store program sections, that is, specific codes, data, and the like. The attribute of the storage area in the input section may be set to Read Only (RO) Readable Writable (RW), uninitialized variable (ZI), and uninitialized (No init).
Generally, the code of the program, the permanent data, the read-only variable, and other data properties are set to be read-only. The data with the same attribute are put together, the priority order is RO > RW > ZI/NOINIT, when the program is burned, the data with the attribute of RO is firstly stored, then the data of RW is stored, and finally the data with the attribute of ZI or NOINIT is stored.
Furthermore, the allocation information in the dispersed loading file comprises the starting address and the size of the designated storage space, so that the memory can be divided according to the mirror image file generated by the dispersed loading file, and the designated storage space is determined. Further, the attribute specifying the storage space may also be set as an uninitializable variable. In this embodiment, the attribute is set as a non-initializable variable, so that the data stored in the designated storage space is not initialized and damaged when the system is reset.
Further, the allocation information in the scatter load file also includes the start address and size of the ROM, the start address and size of the RAM, and the start position and size of the stack. Further, the ROM, RAM, and stack may be determined from the memory based on the image file generated by the scatter load file.
In this embodiment, the allocation information in the scatter load file further includes: the RAM is composed of a load area and an execution area of a program, a start address and a size of the load area, and a start address and a size of the execution area.
In this embodiment, the starting addresses of the loader and the execution area may be the same or different, and when the loading area and the execution area do not form a redundancy mechanism at the same time, when the execution program is started, the instruction for executing the program is received first, then the program in the loading area is loaded to the execution area according to the starting address of the loading area, and then the program is executed in the execution area from the starting address of the execution area. After the loader and the execution area of the program are separated, the processing of the code in the execution area does not affect the original code stored in the loading.
For example, in the scatter load file of stm32f207, the following description is given:
in the above code description, the start address of the load area is defined as 0x08000000, the size of the load area is defined as 0x80000, and the attribute is read-only RO. The start address of the execution area of the target code startup _ stm32f2xx is 0x08000000, the size of the execution area is 0x8000, and the attribute is read-only RO. In this case, the start address of the load area and the start address of the execution area are overlapped, the code of the load area does not need to be copied to the execution area but is directly executed, and then the data of the readable and writable RW and the uninitialized variable ZI are placed in the storage area having the start address of 0x20000000 and the size of 0x 18000.
For another example, in the scatter load file of stm32f207, the following description is given:
in the above code description, the start address of the load area is defined as 0x06000000, the size of the load area is defined as 0x80000, and the attribute is read-only RO. The start address of the execution area of the target code startup _ stm32f2xx is 0x08000000, the size of the execution area is 0x8000, and the attribute is read-only RO. In this case, the start address of the load area and the start address of the execution area are overlapped, the code of the load area does not need to be copied to the execution area but is directly executed, and then the data of the readable and writable RW and the uninitialized variable ZI are placed in the storage area having the start address of 0x20000000 and the size of 0x 18000.
S203, receiving an instruction for executing the program.
When the program needs to be executed, a user can send an instruction for instructing the program to be executed through the upper computer, and after the instruction is received, the program is started and executed.
And S204, loading the program in the loading area to the execution area according to the starting address of the loading area.
When the allocation information in the scatter load file further includes: when the RAM is composed of a load area and an execution area of a program, a start address and a size of the load area, and a start address and a size of the execution area, the RAM is divided into the load area and the execution area. When executing the program, the program in the load area needs to be loaded into the execution area according to the start address of the load area, that is, the program stored in the load area is copied to the execution area for execution.
And S205, starting from the initial address of the execution area, executing the program in the execution area.
After the program in the loading area is loaded into the execution area, the program can be executed in the execution area according to the starting address of the execution area. In this embodiment, since the RAM is divided into the loading area and the execution area, and the program executed in the execution area is the backup program, the execution process of the program does not affect the original program in the loading area.
S206, when the preset instruction inserted into the program is executed, the storage address is obtained from the preset instruction.
The preset instruction is inserted into a designated position of the program and used for indicating and recording the state information of the CPU in the current program period.
For a specific description of S206, reference may be made to the description of the relevant contents in the above embodiments, and details are not repeated here.
And S207, recording the state information into a corresponding storage unit of the designated storage space according to the storage address.
When the program is executed to the preset instruction, the state information of the CPU is determined to be recorded, and the storage address is obtained from the preset instruction. After the storage address is acquired, the state information of the CPU can be recorded in the storage unit corresponding to the designated storage space according to the storage address, that is, the state information of the CPU can be located in the corresponding storage unit from the designated storage space according to the storage address, and then written in the corresponding storage unit.
In this embodiment, the state information of the CPU in N program cycles is recorded in the designated memory space from the current program cycle as the starting point. Further, the value of N can be determined according to the size of the designated storage space. That is, the data of the designated storage space is covered once every N program cycles, and the state information of the subsequent CPU can be recorded circularly.
In the method for recording CPU state information provided in this embodiment, because a designated storage space is separately provided for the CPU state information, even if a reset or downtime occurs when a CPU fails, the previous CPU state information recorded in the designated storage space is not lost.
Particularly, for safety critical systems with extremely high safety requirements, such as light rail systems, aerospace systems, and the like, the reason for the safety critical system to fail every time may be complicated. The embodiment can provide monitoring for the safety critical system at the CPU level, and can store the state information of the CPU in the last program cycles, so that after the safety critical system fails, the state information of the CPU in the last times can be read out and analyzed to obtain the failure reason.
For example, if stm32 is in operation, a timing error will cause the CPU to enter a bus error exception mode. The reason of the CPU abnormity can be deduced reversely by looking at information such as a CPU link register. Even the grasped information can be utilized to reproduce the environment when the CPU is abnormal, so that the experiment is carried out, and great convenience is provided for the researchers to analyze the faults.
Fig. 4 is a schematic structural diagram of a CPU state information recording apparatus according to an embodiment of the present invention. As shown in fig. 4, the CPU state information recording apparatus includes: a first acquisition module 11 and a recording module 12.
The first obtaining module 11 is configured to obtain a storage address from a preset instruction when a program is executed to the preset instruction; the preset instruction is inserted into a designated position of the program and used for indicating and recording the state information of the CPU in the current program period.
The recording module 12 is configured to record the state information into a storage unit corresponding to the specified storage space according to the storage address; wherein the designated storage space is independent of the storage space of the program.
The problem that operation and maintenance personnel cannot deeply know the reason of the CPU failure due to the fact that the system is directly reset or crashed when the CPU fails is solved. In this embodiment, a storage space independent of the storage space where the program is located is allocated in advance from the memory of the CPU, and is referred to as a designated storage space herein, where the designated storage space is used to store the CPU state information in the program cycle.
Further, a preset instruction is inserted into a designated position of the program, and the preset instruction is used for indicating and recording the state information of the CPU in the current program cycle. The first obtaining module 11 may determine that the state information of the CPU needs to be recorded when the program is executed to a preset instruction, and obtain the storage address from the preset instruction. After the storage address is obtained, the recording module 12 may record the state information of the CPU into the corresponding storage unit of the designated storage space according to the storage address, that is, may locate the corresponding storage unit from the designated storage space according to the storage address, and then write the state information of the CPU into the corresponding storage unit.
For example, because the assembly language can access the memory location corresponding to the memory address, a piece of assembly code can be inserted at a designated position of the program main loop, and the state information of the CPU in the current program cycle can be recorded to the designated memory space through the assembly code. The assembly code includes a memory address of a memory cell to which the state information of the CPU is written. After the program is executed to the assembly code, the storage address can be read from the assembly code, then the corresponding storage unit of the designated storage space is directly accessed, and the state information of the CPU is written into the storage unit.
In the CPU state information recording apparatus provided in this embodiment, when a program is executed to a preset instruction, a storage address is obtained from the preset instruction; the preset instruction is inserted into a designated position of the program and used for indicating and recording the state information of the CPU in the current program period, and recording the state information into a storage unit corresponding to a designated storage space which is independent of the storage space where the program is located according to the storage address. In order to record the state information of the CPU during program execution, in this embodiment, a designated storage space is separately partitioned from a memory of the CPU, the designated storage space is independent of a storage space where the program is located, the designated storage space is used to store the state information of the CPU, and because the state information of the CPU is stored, when a fault occurs during CPU operation, the reason of the fault occurrence can be analyzed according to the previously recorded state information of the CPU, thereby facilitating the elimination and avoidance of the fault.
Fig. 5 is a schematic structural diagram of a CPU state information recording apparatus according to an embodiment of the present invention. On the basis of the above embodiment, as shown in fig. 5, the CPU state information recording apparatus further includes: a second obtaining module 13, a determining module 14 and a presetting module 15.
A second obtaining module 13, configured to obtain a pre-programmed distributed load file before the first obtaining module 11 obtains a storage address from a preset instruction when the program is executed to the preset instruction; the distributed loading file comprises allocation information of the CPU memory, wherein the allocation information at least comprises a starting address and a size of the specified storage space;
a determining module 14, configured to determine the specified storage space from the memory according to the scattered loading file.
Further, the determining module 14 is specifically configured to compile the dispersed loaded file by using a compiler to generate an image file, and determine the specified storage space from the memory according to the image file.
And the preset module 15 is configured to set the attribute of the specified storage space as an uninitializable variable.
Further, the recording module 12 is specifically configured to record the state information of the CPU in N program cycles in the specified storage space, using the current program cycle as a starting point.
Further, the recording module 12 is further configured to determine a value of the N according to the size of the specified storage space.
Further, the allocation information also includes the start address and size of the ROM, the start address and size of the RAM, and the start position and size of the stack.
Further, the determining module 14 is further configured to determine the ROM, the RAM, and the stack from the memory according to the image file.
Further, the allocation information further includes: the RAM includes a load area and an execution area of the program, a start address and a size of the load area, and a start address and a size of the execution area.
Fig. 6 is a schematic structural diagram of a first obtaining module 11 according to an embodiment of the present invention. As shown in fig. 6, the first obtaining module 11 includes: a receiving unit 111, a loading unit 112, an execution unit 113, and an acquisition unit 114.
A receiving unit 111 for receiving instructions to execute the program.
A loading unit 112, configured to load the program in the loading area into the execution area according to the start address of the loading area.
An execution unit 113 for executing the program in the execution area starting from a start address of the execution area.
A fetching unit 114, configured to, when the preset instruction inserted into the program is executed, fetch the storage address from the preset instruction.
In this embodiment, because a designated storage space is separately provided for the CPU state information, even if a reset or downtime occurs when the CPU fails, the previous CPU state information recorded in the independent designated storage space is not lost.
Particularly, for safety critical systems with extremely high safety requirements, such as light rail systems, aerospace systems, and the like, the reason for the safety critical system to fail every time may be complicated. The embodiment can provide monitoring for the safety critical system at the CPU level, and can store the state information of the CPU in the last program cycles, so that after the safety critical system fails, the state information of the CPU in the last times can be read out and analyzed to obtain the failure reason.
It should be noted that the terms "first," "second," and the like in the description of the present invention are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and alternate implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present invention.
It should be understood that the invention can be implemented in various modules or combinations thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.
In addition, functional units in the embodiments of the present invention may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.
The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (14)
1. A CPU state information recording method, comprising:
when a program is executed to a preset instruction, acquiring a storage address from the preset instruction; the preset instruction is inserted into a specified position of the program and used for indicating and recording the state information of the CPU in the current program period;
recording the state information into a corresponding storage unit of a designated storage space according to the storage address, and recording the state information of the CPU in N program periods in the designated storage space by taking the current program period as a starting point; wherein the designated storage space is independent of the storage space of the program;
when the program is executed to a preset instruction and before the memory address is obtained from the preset instruction, the method further includes:
acquiring a pre-compiled scattered loading file; the distributed loading file comprises allocation information of the CPU memory, wherein the allocation information at least comprises a starting address and a size of the specified storage space;
and determining the specified storage space from the memory according to the scattered loading file, and setting the attribute of the specified storage space as a non-initializable variable.
2. The method of claim 1, wherein determining the designated storage space from the memory according to the scatter load file comprises:
compiling the scattered loading file through a compiler to generate an image file;
and determining the designated storage space from the memory according to the image file.
3. The method of claim 1, further comprising:
and determining the value of the N according to the size of the specified storage space.
4. The method of claim 2, wherein the allocation information further comprises a start address and size of the ROM, a start address and size of the RAM, and a start position and size of the stack.
5. The method of claim 4, further comprising:
and determining the ROM, the RAM and the stack from the memory according to the image file.
6. The method of claim 5, wherein the allocation information further comprises: the RAM includes a load area and an execution area of the program, a start address and a size of the load area, and a start address and a size of the execution area.
7. The method of claim 6, wherein obtaining a memory address from a predetermined instruction when the program is executed to the predetermined instruction comprises:
receiving an instruction to execute the program;
loading the program in the loading area to the execution area according to the starting address of the loading area;
executing the program within the execution area starting from a start address of the execution area;
and when the preset instruction inserted into the program is executed, acquiring the storage address from the preset instruction.
8. A CPU state information recording apparatus, comprising:
the first acquisition module is used for acquiring a storage address from a preset instruction when a program is executed to the preset instruction; the preset instruction is inserted into a specified position of the program and used for indicating and recording the state information of the CPU in the current program period;
the recording module is used for recording the state information into a corresponding storage unit of the designated storage space according to the storage address; wherein the designated storage space is independent of the storage space of the program;
the recording module is specifically configured to record state information of the CPU in N program cycles in the specified storage space forward with a current program cycle as a starting point;
the CPU state information recording apparatus further includes:
the second acquisition module is used for acquiring a pre-programmed dispersed loading file before the first acquisition module acquires a storage address from a preset instruction when a program is executed to the preset instruction; the distributed loading file comprises allocation information of the CPU memory, wherein the allocation information at least comprises a starting address and a size of the specified storage space;
the determining module is used for determining the specified storage space from the memory according to the scattered loading file;
and the preset module is used for setting the attribute of the specified storage space as a non-initializable variable.
9. The apparatus according to claim 8, wherein the determining module is specifically configured to compile the scatter load file by a compiler to generate an image file, and determine the specified storage space from the memory according to the image file.
10. The apparatus of claim 9, wherein the recording module is further configured to determine the value of N according to the size of the designated storage space.
11. The apparatus of claim 9, wherein the allocation information further comprises a start address and size of the ROM, a start address and size of the RAM, and a start position and size of the stack.
12. The apparatus of claim 11, wherein the determining module is further configured to determine the ROM, the RAM, and the stack from the memory according to the image file.
13. The apparatus of claim 12, wherein the allocation information further comprises: the RAM includes a load area and an execution area of the program, a start address and a size of the load area, and a start address and a size of the execution area.
14. The apparatus of claim 13, wherein the first obtaining module comprises:
a receiving unit configured to receive an instruction to execute the program;
a loading unit, configured to load the program in the loading area into the execution area according to a start address of the loading area;
an execution unit for executing the program within the execution area starting from a start address of the execution area;
the obtaining unit is configured to obtain the storage address from the preset instruction when the preset instruction inserted into the program is executed.
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| CN109711539B (en) * | 2018-12-17 | 2020-05-29 | 中科寒武纪科技股份有限公司 | Operation method, device and related product |
| CN111858116B (en) * | 2020-06-19 | 2024-02-13 | 浪潮电子信息产业股份有限公司 | Information recording method, device, equipment and readable storage medium |
| CN114967634A (en) * | 2021-09-16 | 2022-08-30 | 长城汽车股份有限公司 | Processor diagnostic device, processor diagnostic method, and electronic apparatus |
| CN114625233B (en) * | 2022-03-30 | 2023-07-21 | 苏州浪潮智能科技有限公司 | Power management method, system, equipment and storage medium |
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