CN108538840A - 混合型三维存储器 - Google Patents

混合型三维存储器 Download PDF

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Publication number
CN108538840A
CN108538840A CN201710119051.XA CN201710119051A CN108538840A CN 108538840 A CN108538840 A CN 108538840A CN 201710119051 A CN201710119051 A CN 201710119051A CN 108538840 A CN108538840 A CN 108538840A
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storage array
storage
memory block
3d
further characterized
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CN201710119051.XA
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张国飙
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成都海存艾匹科技有限公司
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Priority to CN201710119051.XA priority Critical patent/CN108538840A/zh
Priority claimed from US15/494,539 external-priority patent/US10446193B2/en
Publication of CN108538840A publication Critical patent/CN108538840A/zh

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/11206Programmable ROM [PROM], e.g. memory cells comprising a transistor and a fuse or an antifuse
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/11213ROM only
    • H01L27/1128ROM only with transistors on different levels, e.g. 3D ROM

Abstract

本发明提出一种混合型三维存储器(3D‑Mx),数据和代码存储在同一3D‑Mx芯片中。不需要高速读取但要求低成本的数据存储在大存储阵列中,需要高速读取而对成本不敏感的代码存储在小存储阵列中。

Description

混合型三维存储器

技术领域

[0001] 本发明涉及集成电路存储器领域,更确切地说,涉及三维存储器(3D-M)。

背景技术

[0002] 三维存储器(3D-M)是一种单体(monolithic)半导体存储器,它含有多个相互堆叠 的存储元(也被称为存储器件)3D-M包括三维只读存储器(3D-ROM)和三维随机读取存储器 (3D-RAM) JD-R0M可以进一步划分为三维掩膜编程只读存储器(3D-MPR0M)和三维电编程只 读存储器(3D-EPR0M)。基于其编程机制,3D-M可以含有memristor、resistive random-access memory (RRAM或ReRAM)、phase-change memory(PCM)、programmable metallization memory(PMM)、或conductive-bridging random-access memory(CBRAM) 等。

[0003] 美国专利5,835,396披露了一种30,(3〇-1«)^1)(图1六)。它含有一半导体衬底〇以及 位于其上的衬底电路OK。一层平面化的绝缘介质〇d覆盖衬底电路OK。在绝缘介质层0d之上 形成第一存储层10,接着在第一存储层10之上形成第二存储层20。第一和第二存储层10、 20通过接触通道孔13a、23a与衬底电路0K耦合。

[0004] 每个存储层(如10、2〇)含有多条顶地址线(S卩y地址线,如12a-12d、22a-22d)、多条 底地址线(即x地址线,如lla、21a)和多个位于顶地址线和底地址线交叉处的存储器件(如 laa-lad、2aa_2ad)。每个存储层(如2〇)含有至少一存储阵列(如200A)。存储阵列200A是在 存储层20中至少共享一条地址线的所有存储器件2aa-2ad的集合。在一个存储阵列200A中, 所有地址线2la、22a-22d均是连续的;在相邻存储阵列中,地址线不连续。

[0005] —个3D-M芯片含有多个存储块1〇〇。图1A中的结构就是存储块100的一部分。存储 块100最上面的存储层仅含有一个存储阵列200A。换句话说,在存储块100的最顶存储层20 中,所有地址线21a、22a_22d均是连续的,其边缘均在存储块10〇的边缘附近。过去,在同一 3D-M芯片1000中,所有存储块laa-ldd都有相同大小;在每一存储块1〇〇中,不同存储层1〇、 20上的所有存储阵列100A、200A都有相同大小。

[0006]每个存储器件是一种含有至少两种状态的二端口器件。常用的存储器件包括二极 管或类二极管器件。具体说来,存储器件laa含有一二极管膜和一可编程膜(图1A)。二极管 膜的电气特征与二极管类似,二极管泛指任何具有如下特征的二端口器件:当其外加电压 的数值小于读电压或外加电压的方向与读电压相反时,其电阻远大于其在读电压下的电 阻。可编程膜的状态可以在制造过程中(即掩膜编程,如图丨A)或制造完成后改变(即电编 程)。

[0007]当存储芯片的容量尚小时,单一存储芯片一般只会存储单一类别的信息。但是,随 着3D-M存储容量的增加(3D-M的单芯存储容量可达到丨此),一个单一3D—M芯片将存储各种 信息。例如,一个单一3D-M芯片上可以同时存储数据(如数码书籍、数码地图、音乐、电影、 和/或视频等)和代码(如操作系统、软件、和/或游戏等)。虽然数据读取速度要求不高,代码 对读取速度要求很高。此外,数据对存储成本有较高要求。现有技术中,所有存储阵列(或, 所有存储块)有相同大小。这会导致诸多问题:如果存储阵列太小,较高的芯片成本将难以 满足数据对成本的要求;如果存储阵列太大,较慢的读取速度则不能满足代码对速度的要 求。

发明内容

[0008] 本发明的主要目的是在同一3D-M芯片中存储数据和代码。

[0009] 本发明的另一目的是优化3D-M的存储成本和读取速度。

[0010] 为了实现这些以及别的目的,本发明提出一种混合型三维存储器(3D-MX),其存储 阵列(或,存储块)有不同大小。不需要高速读取但要求低成本的数据(如数码书籍、数码地 图、音乐、电影、和/或视频等)存储在大存储阵列(或,存储块)中,需要高速读取而对成本不 敏感的代码(如操作系统、软件、和/或游戏等)存储在小存储阵列(或,存储块)中。3D-MX可 以含有混合存储块、混合存储阵列、或它们的组合。在含有混合存储块的3D-MX中,具有不同 大小的存储块可以肩并肩地排列在一起。在含有混合存储阵列的3D-MX中,一个大存储阵列 下面可以含有多个肩并肩排列的小存储阵列。

[0011] 相应地,本发明提出一种含有混合存储块的3D-MX,其特征在于包括:。

[0012] 本发明还提出一种含有混合存储阵列的3D-MX,其特征在于包括:。

附图说明

[0013]图1A是一种现有技术中3D-M的截面图;图1B是一现有技术中3D-M的芯片示意图。 [0014]图2显示阵列效率、读取速度与阵列大小之间的关系。

[0015]图3是一种含有混合存储块3D-MX的芯片示意图。

[0016] 图4是一种含有混合存储阵列3D-MX的芯片截面图。

[0017] 注意到,这些附图仅是概要图,它们不按比例绘图。为了显眼和方便起见,图中的 部分尺寸和结构可能做了放大或缩小。在不同实施例中,相同的符号一般表示对应或类似 的结构。虽然本说明书显示的例子均为3D-MPR0M,本发明的概念可以很容易地推广到其它 3D-M 中。

具体实施方式

[0018] 图2显示阵列效率、读取速度与阵列大小之间的关系。对于小存储阵列,由于每个 存储阵列的周边电路大小基本固定,故阵列效率较低。随着存储阵列的变大,虽然阵列效率 增加了,但是由于寄生电阻和电容增加,读取速度降低。

[0019] 为了将数据和代码存储在同一3D-M芯片中,且能满足它们对成本和速度不同的要 求,本发明提出一种混合型三维存储器(3D-MX),其存储阵列(或,存储块)有不同大小。不需 要高速读取但要求低成本的数据(如数码书籍、数码地图、音乐、电影、和/或视频等)存储在 大存储阵列(或,存储块)中,需要高速读取而对成本不敏感的代码(如操作系统、软件、和/ 或游戏等)存储在小存储阵列(或,存储块)中。3D-Mx可以含有混合存储块、混合存储阵列、 或它们的组合。在含有混合存储块的3D-MX中,具有不同大小的存储块可以肩并肩地排列在 一起。在含有混合存储阵列的3D-MX*,一个大存储阵列下面可以含有多个肩并肩排列的小 存储阵列。

[0020] 图3显示一种含有混合存储块3D-Mx芯片2000。它含有多个存储块la、lb、lac-ldd。 其中,存储块la、lb比存储块lac-ldd大。因此,存储块la、lb可以用来存储不需要高速读取 的数据(如数码书籍、数码地图、音乐、电影、和/或视频等),而存储块1ac_ldd可以用来存储 需要高速读取的代码(如操作系统、软件、和/或游戏等)。

[0021] 图4显示一种含有混合存储阵列3〇-Mx芯片。该实施例含有2个存储层1〇、20,存储 层20堆叠在存储层10之上。存储层2〇是最高存储层,它含有存储阵列200A,而存储层10是一 中间存储层,它含有2个肩并肩排列的存储阵列l〇〇A、l〇〇A’。很明显,存储层20中的存储阵 列200A比存储层10中的存储阵列l〇〇A、100A’大。因此,存储层20中的存储阵列200A可以用 来存储不需要高速读取的数据(如数码书籍、数码地图、音乐、电影、和/或视频等),而存储 层10中的存储阵列l〇〇A、l〇〇A’可以用来存储需要高速读取的代码(如操作系统、软件、和/ 或游戏等)。

[0022]应该了解,在不远离本发明的精神和范围的前提下,可以对本发明的形式和细节 进行改动,这并不妨碍它们应用本发明的精神。因此,除了根据附加的权利要求书的精神, 本发明不应受到任何限制。

Claims (10)

1. 一种混合型三维存储器(3D-Mx),其特征在于包括: 一存储数据的第一存储块(la),该第一存储块(la)含有相互堆叠、包括第一最高存 层的多个存储层,该第一最高存储层只含有一第一存储阵列; 一存储代码的第二存储块(lac),该第二存储块(lac)含有相互堆叠、包括第二最高 储层的多个存储层,该第二最高存储层只含有一第二存储阵列; 阵列第一存储块(la)与该第二存储块(lac)肩并肩排列,该第一存储阵列比该第二存储
2.—种混合型二维存储器(3D_MX),其特征在于含有一存储块,该存储块包括: 相互^叠、包括一最高存储层(2〇)和至少一中间存储层(1〇)的多个存储层(1〇,2〇); 该最高存储层(20)只含有一第一存储阵列(2〇〇A); ’ 该中间存储层含有第二和第三存储阵列(l〇〇A,100A,),该第二和第三存储阵列不;it 孚地址线; 该第一存储阵列(200A)完全覆盖该第二和第三存储阵列(1〇〇A,1〇〇A,)。
3.根据权利要求2所述的存储器,其特征还在于:该第一存储阵列(2〇〇A)存储数据。
4.根据权利要求1或3所述的存储器,其特征还在于:该数据包括数码书籍。
5. 根据权利要求1或3所述的存储器,其特征还在于:该数据包括数码地图。
6. 根据权利要求1或3所述的存储器,其特征还在于:该数据包括音乐。
7.根据权利要求1或3所述的存储器,其特征还在于:该数据包括电影和/或视频。
8.根据权利要求2所述的存储器,其特征还在于:该第二和第三存储阵列d〇〇八, l〇〇A’)存储代码。 一
9.根据权利要求1或8所述的存储器,其特征还在于:该代码包括操作系统和/或软件。
10.根据权利要求1或8所述的存储器,其特征还在于:该代码包括游戏。
CN201710119051.XA 2017-03-02 2017-03-02 混合型三维存储器 CN108538840A (zh)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104979352A (zh) * 2014-04-14 2015-10-14 成都海存艾匹科技有限公司 混合型三维印录存储器

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104979352A (zh) * 2014-04-14 2015-10-14 成都海存艾匹科技有限公司 混合型三维印录存储器

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Application publication date: 20180914